1 Version 9.0 Build 132 02/25/2009 SJ Full Version
17 -- Start Library Paths --
18 -- End Library Paths --
19 -- Start VHDL Libraries --
20 -- End VHDL Libraries --
29 d3e7ceaac9b26558f3ae0434c87e1
39 |opt|quartus|quartus|lmf|synplcty.lmf
40 3057712873b497a38b70a3917f30cc38
51 ..|..|syn|rev_1|vga.vqm
52 75b23e99ee7fd7794044e77b9ba64bf9
58 |opt|quartus|quartus|lmf|synplcty.lmf
59 3057712873b497a38b70a3917f30cc38
70 ..|..|syn|rev_1|vga.vqm
71 75b23e99ee7fd7794044e77b9ba64bf9
74 vga:inst|vga_driver:vga_driver_unit
77 |opt|quartus|quartus|lmf|synplcty.lmf
78 3057712873b497a38b70a3917f30cc38
89 ..|..|syn|rev_1|vga.vqm
90 75b23e99ee7fd7794044e77b9ba64bf9
93 vga:inst|vga_control:vga_control_unit
96 |opt|quartus|quartus|lmf|synplcty.lmf
97 3057712873b497a38b70a3917f30cc38
113 ccc2bcb05887d5721243fd22481948be
116 HDL_INITIAL_FANOUT_LIMIT
118 AUTO_RESOURCE_SHARING
129 |opt|quartus|quartus|lmf|maxplus2.lmf
130 9a59d39b0706640b4b2718e8a1ff1f
141 |opt|quartus|quartus|libraries|megafunctions|altpll.tdf
142 d980162588d7aa8b78874932c782e18
169 INCLK0_INPUT_FREQUENCY
173 INCLK1_INPUT_FREQUENCY
193 VALID_LOCK_MULTIPLIER
197 INVALID_LOCK_MULTIPLIER
201 SWITCH_OVER_ON_LOSSCLK
205 SWITCH_OVER_ON_GATED_LOCK
209 ENABLE_SWITCH_OVER_COUNTER
245 SELF_RESET_ON_GATED_LOSS_LOCK
249 SELF_RESET_ON_LOSS_LOCK
437 CLK9_USE_EVEN_COUNTER_MODE
441 CLK8_USE_EVEN_COUNTER_MODE
445 CLK7_USE_EVEN_COUNTER_MODE
449 CLK6_USE_EVEN_COUNTER_MODE
453 CLK5_USE_EVEN_COUNTER_MODE
457 CLK4_USE_EVEN_COUNTER_MODE
461 CLK3_USE_EVEN_COUNTER_MODE
465 CLK2_USE_EVEN_COUNTER_MODE
469 CLK1_USE_EVEN_COUNTER_MODE
473 CLK0_USE_EVEN_COUNTER_MODE
477 CLK9_USE_EVEN_COUNTER_VALUE
481 CLK8_USE_EVEN_COUNTER_VALUE
485 CLK7_USE_EVEN_COUNTER_VALUE
489 CLK6_USE_EVEN_COUNTER_VALUE
493 CLK5_USE_EVEN_COUNTER_VALUE
497 CLK4_USE_EVEN_COUNTER_VALUE
501 CLK3_USE_EVEN_COUNTER_VALUE
505 CLK2_USE_EVEN_COUNTER_VALUE
509 CLK1_USE_EVEN_COUNTER_VALUE
513 CLK0_USE_EVEN_COUNTER_VALUE
525 VCO_RANGE_DETECTOR_LOW_BITS
529 VCO_RANGE_DETECTOR_HIGH_BITS
1249 CHARGE_PUMP_CURRENT_BITS
1265 CLK2_OUTPUT_FREQUENCY
1269 CLK1_OUTPUT_FREQUENCY
1273 CLK0_OUTPUT_FREQUENCY
1277 INTENDED_DEVICE_FAMILY
1493 PORT_PHASECOUNTERSELECT
1553 VCO_FREQUENCY_CONTROL
1557 VCO_PHASE_SHIFT_STEP
1565 WIDTH_PHASECOUNTERSELECT
1569 USING_FBMIMICBIDIR_PORT
1581 SIM_GATE_LOCK_DEVICE_BEHAVIOR
1589 IGNORE_CARRY_BUFFERS
1597 IGNORE_CASCADE_BUFFERS
1650 |opt|quartus|quartus|libraries|megafunctions|aglobal90.inc
1651 99832fdf63412df51d7531202d74e75
1652 |opt|quartus|quartus|libraries|megafunctions|stratixii_pll.inc
1653 6d1985e16ab5f59a1fd6b0ae20978a4e
1654 |opt|quartus|quartus|libraries|megafunctions|cycloneii_pll.inc
1655 39a0d9d1237d1db39c848c3f9faffc
1656 |opt|quartus|quartus|libraries|megafunctions|stratix_pll.inc
1657 5f8211898149ceae8264a0ea5036254f
1660 vpll:inst1|altpll:altpll_component
1663 |opt|quartus|quartus|lmf|synplcty.lmf
1664 3057712873b497a38b70a3917f30cc38