1 Analysis & Synthesis report for vga_pll
2 Thu Oct 29 17:12:32 2009
3 Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version
10 2. Analysis & Synthesis Summary
11 3. Analysis & Synthesis Settings
12 4. Analysis & Synthesis Source Files Read
13 5. Analysis & Synthesis Resource Usage Summary
14 6. Analysis & Synthesis Resource Utilization by Entity
15 7. General Register Statistics
16 8. Parameter Settings for User Entity Instance: vpll:inst1|altpll:altpll_component
17 9. altpll Parameter Settings by Entity Instance
18 10. Analysis & Synthesis Messages
25 Copyright (C) 1991-2009 Altera Corporation
26 Your use of Altera Corporation's design tools, logic functions
27 and other software and tools, and its AMPP partner logic
28 functions, and any output files from any of the foregoing
29 (including device programming or simulation files), and any
30 associated documentation or information are expressly subject
31 to the terms and conditions of the Altera Program License
32 Subscription Agreement, Altera MegaCore Function License
33 Agreement, or other applicable license agreement, including,
34 without limitation, that your use is for the sole purpose of
35 programming logic devices manufactured by Altera and sold by
36 Altera or its authorized distributors. Please refer to the
37 applicable agreement for further details.
41 +------------------------------------------------------------------------+
42 ; Analysis & Synthesis Summary ;
43 +-----------------------------+------------------------------------------+
44 ; Analysis & Synthesis Status ; Successful - Thu Oct 29 17:12:32 2009 ;
45 ; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Full Version ;
46 ; Revision Name ; vga_pll ;
47 ; Top-level Entity Name ; vga_pll ;
49 ; Total logic elements ; 143 ;
51 ; Total virtual pins ; 0 ;
52 ; Total memory bits ; 0 ;
53 ; DSP block 9-bit elements ; 0 ;
56 +-----------------------------+------------------------------------------+
59 +----------------------------------------------------------------------------------------------------------+
60 ; Analysis & Synthesis Settings ;
61 +----------------------------------------------------------------+--------------------+--------------------+
62 ; Option ; Setting ; Default Value ;
63 +----------------------------------------------------------------+--------------------+--------------------+
64 ; Device ; EP1S25F672C6 ; ;
65 ; Top-level entity name ; vga_pll ; vga_pll ;
66 ; Family name ; Stratix ; Stratix ;
67 ; Type of Retiming Performed During Resynthesis ; Full ; ;
68 ; Resynthesis Optimization Effort ; Normal ; ;
69 ; Physical Synthesis Level for Resynthesis ; Normal ; ;
70 ; Use Generated Physical Constraints File ; On ; ;
71 ; Use smart compilation ; Off ; Off ;
72 ; Restructure Multiplexers ; Auto ; Auto ;
73 ; Create Debugging Nodes for IP Cores ; Off ; Off ;
74 ; Preserve fewer node names ; On ; On ;
75 ; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
76 ; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
77 ; VHDL Version ; VHDL93 ; VHDL93 ;
78 ; State Machine Processing ; Auto ; Auto ;
79 ; Safe State Machine ; Off ; Off ;
80 ; Extract Verilog State Machines ; On ; On ;
81 ; Extract VHDL State Machines ; On ; On ;
82 ; Ignore Verilog initial constructs ; Off ; Off ;
83 ; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
84 ; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
85 ; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
86 ; Parallel Synthesis ; Off ; Off ;
87 ; DSP Block Balancing ; Auto ; Auto ;
88 ; NOT Gate Push-Back ; On ; On ;
89 ; Power-Up Don't Care ; On ; On ;
90 ; Remove Redundant Logic Cells ; Off ; Off ;
91 ; Remove Duplicate Registers ; On ; On ;
92 ; Ignore CARRY Buffers ; Off ; Off ;
93 ; Ignore CASCADE Buffers ; Off ; Off ;
94 ; Ignore GLOBAL Buffers ; Off ; Off ;
95 ; Ignore ROW GLOBAL Buffers ; Off ; Off ;
96 ; Ignore LCELL Buffers ; Off ; Off ;
97 ; Ignore SOFT Buffers ; On ; On ;
98 ; Limit AHDL Integers to 32 Bits ; Off ; Off ;
99 ; Optimization Technique ; Balanced ; Balanced ;
100 ; Carry Chain Length ; 70 ; 70 ;
101 ; Auto Carry Chains ; On ; On ;
102 ; Auto Open-Drain Pins ; On ; On ;
103 ; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
104 ; Auto ROM Replacement ; On ; On ;
105 ; Auto RAM Replacement ; On ; On ;
106 ; Auto DSP Block Replacement ; On ; On ;
107 ; Auto Shift Register Replacement ; Auto ; Auto ;
108 ; Auto Clock Enable Replacement ; On ; On ;
109 ; Strict RAM Replacement ; Off ; Off ;
110 ; Allow Synchronous Control Signals ; On ; On ;
111 ; Force Use of Synchronous Clear Signals ; Off ; Off ;
112 ; Auto RAM Block Balancing ; On ; On ;
113 ; Auto RAM to Logic Cell Conversion ; Off ; Off ;
114 ; Auto Resource Sharing ; Off ; Off ;
115 ; Allow Any RAM Size For Recognition ; Off ; Off ;
116 ; Allow Any ROM Size For Recognition ; Off ; Off ;
117 ; Allow Any Shift Register Size For Recognition ; Off ; Off ;
118 ; Use LogicLock Constraints during Resource Balancing ; On ; On ;
119 ; Ignore translate_off and synthesis_off directives ; Off ; Off ;
120 ; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
121 ; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
122 ; Synchronization Register Chain Length ; 2 ; 2 ;
123 ; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
124 ; HDL message level ; Level2 ; Level2 ;
125 ; Suppress Register Optimization Related Messages ; Off ; Off ;
126 ; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
127 ; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
128 ; Clock MUX Protection ; On ; On ;
129 ; Block Design Naming ; Auto ; Auto ;
130 ; Synthesis Effort ; Auto ; Auto ;
131 ; Allows Asynchronous Clear Usage For Shift Register Replacement ; On ; On ;
132 ; Analysis & Synthesis Message Level ; Medium ; Medium ;
133 +----------------------------------------------------------------+--------------------+--------------------+
136 +----------------------------------------------------------------------------------------------------------------------------------------------------------+
137 ; Analysis & Synthesis Source Files Read ;
138 +----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------+
139 ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
140 +----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------+
141 ; ../../src/vga_pll.bdf ; yes ; User Block Diagram/Schematic File ; /homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pll.bdf ;
142 ; ../../syn/rev_1/vga.vqm ; yes ; User Verilog Quartus Mapping File ; /homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm ;
143 ; ../../src/vpll.vhd ; yes ; User Wizard-Generated File ; /homes/burban/didelu/dide_16/bsp3/Designflow/src/vpll.vhd ;
144 ; altpll.tdf ; yes ; Megafunction ; /opt/quartus/quartus/libraries/megafunctions/altpll.tdf ;
145 ; aglobal90.inc ; yes ; Megafunction ; /opt/quartus/quartus/libraries/megafunctions/aglobal90.inc ;
146 ; stratix_pll.inc ; yes ; Megafunction ; /opt/quartus/quartus/libraries/megafunctions/stratix_pll.inc ;
147 ; stratixii_pll.inc ; yes ; Megafunction ; /opt/quartus/quartus/libraries/megafunctions/stratixii_pll.inc ;
148 ; cycloneii_pll.inc ; yes ; Megafunction ; /opt/quartus/quartus/libraries/megafunctions/cycloneii_pll.inc ;
149 +----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------+
152 +----------------------------------------------------------------------------------------+
153 ; Analysis & Synthesis Resource Usage Summary ;
154 +---------------------------------------------+------------------------------------------+
156 +---------------------------------------------+------------------------------------------+
157 ; Total logic elements ; 143 ;
158 ; -- Combinational with no register ; 81 ;
159 ; -- Register only ; 3 ;
160 ; -- Combinational with a register ; 59 ;
162 ; Logic element usage by number of LUT inputs ; ;
163 ; -- 4 input functions ; 53 ;
164 ; -- 3 input functions ; 32 ;
165 ; -- 2 input functions ; 54 ;
166 ; -- 1 input functions ; 1 ;
167 ; -- 0 input functions ; 0 ;
169 ; Logic elements by mode ; ;
170 ; -- normal mode ; 109 ;
171 ; -- arithmetic mode ; 34 ;
173 ; -- register cascade mode ; 0 ;
174 ; -- synchronous clear/load mode ; 48 ;
175 ; -- asynchronous clear/load mode ; 3 ;
177 ; Total registers ; 62 ;
178 ; Total logic cells in carry chains ; 40 ;
181 ; Maximum fan-out node ; vpll:inst1|altpll:altpll_component|_clk0 ;
182 ; Maximum fan-out ; 63 ;
183 ; Total fan-out ; 667 ;
184 ; Average fan-out ; 2.84 ;
185 +---------------------------------------------+------------------------------------------+
188 +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
189 ; Analysis & Synthesis Resource Utilization by Entity ;
190 +--------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------+--------------+
191 ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
192 +--------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------+--------------+
193 ; |vga_pll ; 143 (0) ; 62 ; 0 ; 0 ; 0 ; 0 ; 0 ; 91 ; 0 ; 81 (0) ; 3 (0) ; 59 (0) ; 40 (0) ; 0 (0) ; |vga_pll ; work ;
194 ; |vga:inst| ; 143 (2) ; 62 ; 0 ; 0 ; 0 ; 0 ; 0 ; 90 ; 0 ; 81 (0) ; 3 (0) ; 59 (2) ; 40 (0) ; 0 (0) ; |vga_pll|vga:inst ; work ;
195 ; |vga_control:vga_control_unit| ; 10 (10) ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 (0) ; |vga_pll|vga:inst|vga_control:vga_control_unit ; work ;
196 ; |vga_driver:vga_driver_unit| ; 131 (131) ; 57 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 74 (74) ; 3 (3) ; 54 (54) ; 40 (40) ; 0 (0) ; |vga_pll|vga:inst|vga_driver:vga_driver_unit ; work ;
197 ; |vpll:inst1| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |vga_pll|vpll:inst1 ; work ;
198 ; |altpll:altpll_component| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |vga_pll|vpll:inst1|altpll:altpll_component ; work ;
199 +--------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------+--------------+
200 Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
203 +------------------------------------------------------+
204 ; General Register Statistics ;
205 +----------------------------------------------+-------+
206 ; Statistic ; Value ;
207 +----------------------------------------------+-------+
208 ; Total registers ; 62 ;
209 ; Number of registers using Synchronous Clear ; 48 ;
210 ; Number of registers using Synchronous Load ; 20 ;
211 ; Number of registers using Asynchronous Clear ; 3 ;
212 ; Number of registers using Asynchronous Load ; 0 ;
213 ; Number of registers using Clock Enable ; 12 ;
214 ; Number of registers using Preset ; 0 ;
215 +----------------------------------------------+-------+
218 +---------------------------------------------------------------------------------+
219 ; Parameter Settings for User Entity Instance: vpll:inst1|altpll:altpll_component ;
220 +-------------------------------+-------------------+-----------------------------+
221 ; Parameter Name ; Value ; Type ;
222 +-------------------------------+-------------------+-----------------------------+
223 ; OPERATION_MODE ; NORMAL ; Untyped ;
224 ; PLL_TYPE ; AUTO ; Untyped ;
225 ; QUALIFY_CONF_DONE ; OFF ; Untyped ;
226 ; COMPENSATE_CLOCK ; CLK0 ; Untyped ;
227 ; SCAN_CHAIN ; LONG ; Untyped ;
228 ; PRIMARY_CLOCK ; INCLK0 ; Untyped ;
229 ; INCLK0_INPUT_FREQUENCY ; 30003 ; Signed Integer ;
230 ; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ;
231 ; GATE_LOCK_SIGNAL ; NO ; Untyped ;
232 ; GATE_LOCK_COUNTER ; 0 ; Untyped ;
233 ; LOCK_HIGH ; 1 ; Untyped ;
234 ; LOCK_LOW ; 1 ; Untyped ;
235 ; VALID_LOCK_MULTIPLIER ; 1 ; Signed Integer ;
236 ; INVALID_LOCK_MULTIPLIER ; 5 ; Signed Integer ;
237 ; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ;
238 ; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ;
239 ; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ;
240 ; SKIP_VCO ; OFF ; Untyped ;
241 ; SWITCH_OVER_COUNTER ; 0 ; Untyped ;
242 ; SWITCH_OVER_TYPE ; AUTO ; Untyped ;
243 ; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ;
244 ; BANDWIDTH ; 0 ; Untyped ;
245 ; BANDWIDTH_TYPE ; AUTO ; Untyped ;
246 ; SPREAD_FREQUENCY ; 0 ; Signed Integer ;
247 ; DOWN_SPREAD ; 0 ; Untyped ;
248 ; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ;
249 ; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ;
250 ; CLK9_MULTIPLY_BY ; 0 ; Untyped ;
251 ; CLK8_MULTIPLY_BY ; 0 ; Untyped ;
252 ; CLK7_MULTIPLY_BY ; 0 ; Untyped ;
253 ; CLK6_MULTIPLY_BY ; 0 ; Untyped ;
254 ; CLK5_MULTIPLY_BY ; 1 ; Untyped ;
255 ; CLK4_MULTIPLY_BY ; 1 ; Untyped ;
256 ; CLK3_MULTIPLY_BY ; 1 ; Untyped ;
257 ; CLK2_MULTIPLY_BY ; 1 ; Untyped ;
258 ; CLK1_MULTIPLY_BY ; 1 ; Untyped ;
259 ; CLK0_MULTIPLY_BY ; 5435 ; Signed Integer ;
260 ; CLK9_DIVIDE_BY ; 0 ; Untyped ;
261 ; CLK8_DIVIDE_BY ; 0 ; Untyped ;
262 ; CLK7_DIVIDE_BY ; 0 ; Untyped ;
263 ; CLK6_DIVIDE_BY ; 0 ; Untyped ;
264 ; CLK5_DIVIDE_BY ; 1 ; Untyped ;
265 ; CLK4_DIVIDE_BY ; 1 ; Untyped ;
266 ; CLK3_DIVIDE_BY ; 1 ; Untyped ;
267 ; CLK2_DIVIDE_BY ; 1 ; Untyped ;
268 ; CLK1_DIVIDE_BY ; 1 ; Untyped ;
269 ; CLK0_DIVIDE_BY ; 6666 ; Signed Integer ;
270 ; CLK9_PHASE_SHIFT ; 0 ; Untyped ;
271 ; CLK8_PHASE_SHIFT ; 0 ; Untyped ;
272 ; CLK7_PHASE_SHIFT ; 0 ; Untyped ;
273 ; CLK6_PHASE_SHIFT ; 0 ; Untyped ;
274 ; CLK5_PHASE_SHIFT ; 0 ; Untyped ;
275 ; CLK4_PHASE_SHIFT ; 0 ; Untyped ;
276 ; CLK3_PHASE_SHIFT ; 0 ; Untyped ;
277 ; CLK2_PHASE_SHIFT ; 0 ; Untyped ;
278 ; CLK1_PHASE_SHIFT ; 0 ; Untyped ;
279 ; CLK0_PHASE_SHIFT ; 0 ; Untyped ;
280 ; CLK5_TIME_DELAY ; 0 ; Untyped ;
281 ; CLK4_TIME_DELAY ; 0 ; Untyped ;
282 ; CLK3_TIME_DELAY ; 0 ; Untyped ;
283 ; CLK2_TIME_DELAY ; 0 ; Untyped ;
284 ; CLK1_TIME_DELAY ; 0 ; Untyped ;
285 ; CLK0_TIME_DELAY ; 0 ; Untyped ;
286 ; CLK9_DUTY_CYCLE ; 50 ; Untyped ;
287 ; CLK8_DUTY_CYCLE ; 50 ; Untyped ;
288 ; CLK7_DUTY_CYCLE ; 50 ; Untyped ;
289 ; CLK6_DUTY_CYCLE ; 50 ; Untyped ;
290 ; CLK5_DUTY_CYCLE ; 50 ; Untyped ;
291 ; CLK4_DUTY_CYCLE ; 50 ; Untyped ;
292 ; CLK3_DUTY_CYCLE ; 50 ; Untyped ;
293 ; CLK2_DUTY_CYCLE ; 50 ; Untyped ;
294 ; CLK1_DUTY_CYCLE ; 50 ; Untyped ;
295 ; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ;
296 ; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
297 ; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
298 ; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
299 ; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
300 ; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
301 ; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
302 ; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
303 ; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
304 ; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
305 ; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
306 ; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
307 ; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
308 ; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
309 ; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
310 ; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
311 ; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
312 ; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
313 ; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
314 ; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
315 ; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
316 ; LOCK_WINDOW_UI ; 0.05 ; Untyped ;
317 ; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ;
318 ; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ;
319 ; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ;
320 ; DPA_MULTIPLY_BY ; 0 ; Untyped ;
321 ; DPA_DIVIDE_BY ; 1 ; Untyped ;
322 ; DPA_DIVIDER ; 0 ; Untyped ;
323 ; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ;
324 ; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ;
325 ; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ;
326 ; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ;
327 ; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ;
328 ; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ;
329 ; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ;
330 ; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ;
331 ; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ;
332 ; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ;
333 ; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ;
334 ; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ;
335 ; EXTCLK3_TIME_DELAY ; 0 ; Untyped ;
336 ; EXTCLK2_TIME_DELAY ; 0 ; Untyped ;
337 ; EXTCLK1_TIME_DELAY ; 0 ; Untyped ;
338 ; EXTCLK0_TIME_DELAY ; 0 ; Untyped ;
339 ; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ;
340 ; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ;
341 ; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ;
342 ; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ;
343 ; VCO_MULTIPLY_BY ; 0 ; Untyped ;
344 ; VCO_DIVIDE_BY ; 0 ; Untyped ;
345 ; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ;
346 ; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ;
347 ; VCO_MIN ; 0 ; Untyped ;
348 ; VCO_MAX ; 0 ; Untyped ;
349 ; VCO_CENTER ; 0 ; Untyped ;
350 ; PFD_MIN ; 0 ; Untyped ;
351 ; PFD_MAX ; 0 ; Untyped ;
352 ; M_INITIAL ; 0 ; Untyped ;
358 ; C0_HIGH ; 0 ; Untyped ;
359 ; C1_HIGH ; 0 ; Untyped ;
360 ; C2_HIGH ; 0 ; Untyped ;
361 ; C3_HIGH ; 0 ; Untyped ;
362 ; C4_HIGH ; 0 ; Untyped ;
363 ; C5_HIGH ; 0 ; Untyped ;
364 ; C6_HIGH ; 0 ; Untyped ;
365 ; C7_HIGH ; 0 ; Untyped ;
366 ; C8_HIGH ; 0 ; Untyped ;
367 ; C9_HIGH ; 0 ; Untyped ;
368 ; C0_LOW ; 0 ; Untyped ;
369 ; C1_LOW ; 0 ; Untyped ;
370 ; C2_LOW ; 0 ; Untyped ;
371 ; C3_LOW ; 0 ; Untyped ;
372 ; C4_LOW ; 0 ; Untyped ;
373 ; C5_LOW ; 0 ; Untyped ;
374 ; C6_LOW ; 0 ; Untyped ;
375 ; C7_LOW ; 0 ; Untyped ;
376 ; C8_LOW ; 0 ; Untyped ;
377 ; C9_LOW ; 0 ; Untyped ;
378 ; C0_INITIAL ; 0 ; Untyped ;
379 ; C1_INITIAL ; 0 ; Untyped ;
380 ; C2_INITIAL ; 0 ; Untyped ;
381 ; C3_INITIAL ; 0 ; Untyped ;
382 ; C4_INITIAL ; 0 ; Untyped ;
383 ; C5_INITIAL ; 0 ; Untyped ;
384 ; C6_INITIAL ; 0 ; Untyped ;
385 ; C7_INITIAL ; 0 ; Untyped ;
386 ; C8_INITIAL ; 0 ; Untyped ;
387 ; C9_INITIAL ; 0 ; Untyped ;
388 ; C0_MODE ; BYPASS ; Untyped ;
389 ; C1_MODE ; BYPASS ; Untyped ;
390 ; C2_MODE ; BYPASS ; Untyped ;
391 ; C3_MODE ; BYPASS ; Untyped ;
392 ; C4_MODE ; BYPASS ; Untyped ;
393 ; C5_MODE ; BYPASS ; Untyped ;
394 ; C6_MODE ; BYPASS ; Untyped ;
395 ; C7_MODE ; BYPASS ; Untyped ;
396 ; C8_MODE ; BYPASS ; Untyped ;
397 ; C9_MODE ; BYPASS ; Untyped ;
398 ; C0_PH ; 0 ; Untyped ;
399 ; C1_PH ; 0 ; Untyped ;
400 ; C2_PH ; 0 ; Untyped ;
401 ; C3_PH ; 0 ; Untyped ;
402 ; C4_PH ; 0 ; Untyped ;
403 ; C5_PH ; 0 ; Untyped ;
404 ; C6_PH ; 0 ; Untyped ;
405 ; C7_PH ; 0 ; Untyped ;
406 ; C8_PH ; 0 ; Untyped ;
407 ; C9_PH ; 0 ; Untyped ;
408 ; L0_HIGH ; 1 ; Untyped ;
409 ; L1_HIGH ; 1 ; Untyped ;
410 ; G0_HIGH ; 1 ; Untyped ;
411 ; G1_HIGH ; 1 ; Untyped ;
412 ; G2_HIGH ; 1 ; Untyped ;
413 ; G3_HIGH ; 1 ; Untyped ;
414 ; E0_HIGH ; 1 ; Untyped ;
415 ; E1_HIGH ; 1 ; Untyped ;
416 ; E2_HIGH ; 1 ; Untyped ;
417 ; E3_HIGH ; 1 ; Untyped ;
418 ; L0_LOW ; 1 ; Untyped ;
419 ; L1_LOW ; 1 ; Untyped ;
420 ; G0_LOW ; 1 ; Untyped ;
421 ; G1_LOW ; 1 ; Untyped ;
422 ; G2_LOW ; 1 ; Untyped ;
423 ; G3_LOW ; 1 ; Untyped ;
424 ; E0_LOW ; 1 ; Untyped ;
425 ; E1_LOW ; 1 ; Untyped ;
426 ; E2_LOW ; 1 ; Untyped ;
427 ; E3_LOW ; 1 ; Untyped ;
428 ; L0_INITIAL ; 1 ; Untyped ;
429 ; L1_INITIAL ; 1 ; Untyped ;
430 ; G0_INITIAL ; 1 ; Untyped ;
431 ; G1_INITIAL ; 1 ; Untyped ;
432 ; G2_INITIAL ; 1 ; Untyped ;
433 ; G3_INITIAL ; 1 ; Untyped ;
434 ; E0_INITIAL ; 1 ; Untyped ;
435 ; E1_INITIAL ; 1 ; Untyped ;
436 ; E2_INITIAL ; 1 ; Untyped ;
437 ; E3_INITIAL ; 1 ; Untyped ;
438 ; L0_MODE ; BYPASS ; Untyped ;
439 ; L1_MODE ; BYPASS ; Untyped ;
440 ; G0_MODE ; BYPASS ; Untyped ;
441 ; G1_MODE ; BYPASS ; Untyped ;
442 ; G2_MODE ; BYPASS ; Untyped ;
443 ; G3_MODE ; BYPASS ; Untyped ;
444 ; E0_MODE ; BYPASS ; Untyped ;
445 ; E1_MODE ; BYPASS ; Untyped ;
446 ; E2_MODE ; BYPASS ; Untyped ;
447 ; E3_MODE ; BYPASS ; Untyped ;
448 ; L0_PH ; 0 ; Untyped ;
449 ; L1_PH ; 0 ; Untyped ;
450 ; G0_PH ; 0 ; Untyped ;
451 ; G1_PH ; 0 ; Untyped ;
452 ; G2_PH ; 0 ; Untyped ;
453 ; G3_PH ; 0 ; Untyped ;
454 ; E0_PH ; 0 ; Untyped ;
455 ; E1_PH ; 0 ; Untyped ;
456 ; E2_PH ; 0 ; Untyped ;
457 ; E3_PH ; 0 ; Untyped ;
458 ; M_PH ; 0 ; Untyped ;
459 ; C1_USE_CASC_IN ; OFF ; Untyped ;
460 ; C2_USE_CASC_IN ; OFF ; Untyped ;
461 ; C3_USE_CASC_IN ; OFF ; Untyped ;
462 ; C4_USE_CASC_IN ; OFF ; Untyped ;
463 ; C5_USE_CASC_IN ; OFF ; Untyped ;
464 ; C6_USE_CASC_IN ; OFF ; Untyped ;
465 ; C7_USE_CASC_IN ; OFF ; Untyped ;
466 ; C8_USE_CASC_IN ; OFF ; Untyped ;
467 ; C9_USE_CASC_IN ; OFF ; Untyped ;
468 ; CLK0_COUNTER ; G0 ; Untyped ;
469 ; CLK1_COUNTER ; G0 ; Untyped ;
470 ; CLK2_COUNTER ; G0 ; Untyped ;
471 ; CLK3_COUNTER ; G0 ; Untyped ;
472 ; CLK4_COUNTER ; G0 ; Untyped ;
473 ; CLK5_COUNTER ; G0 ; Untyped ;
474 ; CLK6_COUNTER ; E0 ; Untyped ;
475 ; CLK7_COUNTER ; E1 ; Untyped ;
476 ; CLK8_COUNTER ; E2 ; Untyped ;
477 ; CLK9_COUNTER ; E3 ; Untyped ;
478 ; L0_TIME_DELAY ; 0 ; Untyped ;
479 ; L1_TIME_DELAY ; 0 ; Untyped ;
480 ; G0_TIME_DELAY ; 0 ; Untyped ;
481 ; G1_TIME_DELAY ; 0 ; Untyped ;
482 ; G2_TIME_DELAY ; 0 ; Untyped ;
483 ; G3_TIME_DELAY ; 0 ; Untyped ;
484 ; E0_TIME_DELAY ; 0 ; Untyped ;
485 ; E1_TIME_DELAY ; 0 ; Untyped ;
486 ; E2_TIME_DELAY ; 0 ; Untyped ;
487 ; E3_TIME_DELAY ; 0 ; Untyped ;
488 ; M_TIME_DELAY ; 0 ; Untyped ;
489 ; N_TIME_DELAY ; 0 ; Untyped ;
490 ; EXTCLK3_COUNTER ; E3 ; Untyped ;
491 ; EXTCLK2_COUNTER ; E2 ; Untyped ;
492 ; EXTCLK1_COUNTER ; E1 ; Untyped ;
493 ; EXTCLK0_COUNTER ; E0 ; Untyped ;
494 ; ENABLE0_COUNTER ; L0 ; Untyped ;
495 ; ENABLE1_COUNTER ; L0 ; Untyped ;
496 ; CHARGE_PUMP_CURRENT ; 2 ; Untyped ;
497 ; LOOP_FILTER_R ; 1.000000 ; Untyped ;
498 ; LOOP_FILTER_C ; 5 ; Untyped ;
499 ; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ;
500 ; LOOP_FILTER_R_BITS ; 9999 ; Untyped ;
501 ; LOOP_FILTER_C_BITS ; 9999 ; Untyped ;
502 ; VCO_POST_SCALE ; 0 ; Untyped ;
503 ; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ;
504 ; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ;
505 ; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ;
506 ; INTENDED_DEVICE_FAMILY ; Stratix ; Untyped ;
507 ; PORT_CLKENA0 ; PORT_CONNECTIVITY ; Untyped ;
508 ; PORT_CLKENA1 ; PORT_CONNECTIVITY ; Untyped ;
509 ; PORT_CLKENA2 ; PORT_CONNECTIVITY ; Untyped ;
510 ; PORT_CLKENA3 ; PORT_CONNECTIVITY ; Untyped ;
511 ; PORT_CLKENA4 ; PORT_CONNECTIVITY ; Untyped ;
512 ; PORT_CLKENA5 ; PORT_CONNECTIVITY ; Untyped ;
513 ; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ;
514 ; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ;
515 ; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ;
516 ; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ;
517 ; PORT_EXTCLK0 ; PORT_CONNECTIVITY ; Untyped ;
518 ; PORT_EXTCLK1 ; PORT_CONNECTIVITY ; Untyped ;
519 ; PORT_EXTCLK2 ; PORT_CONNECTIVITY ; Untyped ;
520 ; PORT_EXTCLK3 ; PORT_CONNECTIVITY ; Untyped ;
521 ; PORT_CLKBAD0 ; PORT_CONNECTIVITY ; Untyped ;
522 ; PORT_CLKBAD1 ; PORT_CONNECTIVITY ; Untyped ;
523 ; PORT_CLK0 ; PORT_CONNECTIVITY ; Untyped ;
524 ; PORT_CLK1 ; PORT_CONNECTIVITY ; Untyped ;
525 ; PORT_CLK2 ; PORT_CONNECTIVITY ; Untyped ;
526 ; PORT_CLK3 ; PORT_CONNECTIVITY ; Untyped ;
527 ; PORT_CLK4 ; PORT_CONNECTIVITY ; Untyped ;
528 ; PORT_CLK5 ; PORT_CONNECTIVITY ; Untyped ;
529 ; PORT_CLK6 ; PORT_UNUSED ; Untyped ;
530 ; PORT_CLK7 ; PORT_UNUSED ; Untyped ;
531 ; PORT_CLK8 ; PORT_UNUSED ; Untyped ;
532 ; PORT_CLK9 ; PORT_UNUSED ; Untyped ;
533 ; PORT_SCANDATA ; PORT_CONNECTIVITY ; Untyped ;
534 ; PORT_SCANDATAOUT ; PORT_CONNECTIVITY ; Untyped ;
535 ; PORT_SCANDONE ; PORT_CONNECTIVITY ; Untyped ;
536 ; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ;
537 ; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ;
538 ; PORT_ACTIVECLOCK ; PORT_CONNECTIVITY ; Untyped ;
539 ; PORT_CLKLOSS ; PORT_CONNECTIVITY ; Untyped ;
540 ; PORT_INCLK1 ; PORT_CONNECTIVITY ; Untyped ;
541 ; PORT_INCLK0 ; PORT_CONNECTIVITY ; Untyped ;
542 ; PORT_FBIN ; PORT_CONNECTIVITY ; Untyped ;
543 ; PORT_PLLENA ; PORT_CONNECTIVITY ; Untyped ;
544 ; PORT_CLKSWITCH ; PORT_CONNECTIVITY ; Untyped ;
545 ; PORT_ARESET ; PORT_CONNECTIVITY ; Untyped ;
546 ; PORT_PFDENA ; PORT_CONNECTIVITY ; Untyped ;
547 ; PORT_SCANCLK ; PORT_CONNECTIVITY ; Untyped ;
548 ; PORT_SCANACLR ; PORT_CONNECTIVITY ; Untyped ;
549 ; PORT_SCANREAD ; PORT_CONNECTIVITY ; Untyped ;
550 ; PORT_SCANWRITE ; PORT_CONNECTIVITY ; Untyped ;
551 ; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ;
552 ; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ;
553 ; PORT_LOCKED ; PORT_CONNECTIVITY ; Untyped ;
554 ; PORT_CONFIGUPDATE ; PORT_CONNECTIVITY ; Untyped ;
555 ; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ;
556 ; PORT_PHASEDONE ; PORT_CONNECTIVITY ; Untyped ;
557 ; PORT_PHASESTEP ; PORT_CONNECTIVITY ; Untyped ;
558 ; PORT_PHASEUPDOWN ; PORT_CONNECTIVITY ; Untyped ;
559 ; PORT_SCANCLKENA ; PORT_CONNECTIVITY ; Untyped ;
560 ; PORT_PHASECOUNTERSELECT ; PORT_CONNECTIVITY ; Untyped ;
561 ; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ;
562 ; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ;
563 ; M_TEST_SOURCE ; 5 ; Untyped ;
564 ; C0_TEST_SOURCE ; 5 ; Untyped ;
565 ; C1_TEST_SOURCE ; 5 ; Untyped ;
566 ; C2_TEST_SOURCE ; 5 ; Untyped ;
567 ; C3_TEST_SOURCE ; 5 ; Untyped ;
568 ; C4_TEST_SOURCE ; 5 ; Untyped ;
569 ; C5_TEST_SOURCE ; 5 ; Untyped ;
570 ; C6_TEST_SOURCE ; 5 ; Untyped ;
571 ; C7_TEST_SOURCE ; 5 ; Untyped ;
572 ; C8_TEST_SOURCE ; 5 ; Untyped ;
573 ; C9_TEST_SOURCE ; 5 ; Untyped ;
574 ; CBXI_PARAMETER ; NOTHING ; Untyped ;
575 ; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ;
576 ; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ;
577 ; WIDTH_CLOCK ; 6 ; Untyped ;
578 ; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ;
579 ; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ;
580 ; DEVICE_FAMILY ; Stratix ; Untyped ;
581 ; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ;
582 ; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ;
583 ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
584 ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
585 ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
586 ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
587 +-------------------------------+-------------------+-----------------------------+
588 Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
591 +--------------------------------------------------------------------+
592 ; altpll Parameter Settings by Entity Instance ;
593 +-------------------------------+------------------------------------+
595 +-------------------------------+------------------------------------+
596 ; Number of entity instances ; 1 ;
597 ; Entity Instance ; vpll:inst1|altpll:altpll_component ;
598 ; -- OPERATION_MODE ; NORMAL ;
599 ; -- PLL_TYPE ; AUTO ;
600 ; -- PRIMARY_CLOCK ; INCLK0 ;
601 ; -- INCLK0_INPUT_FREQUENCY ; 30003 ;
602 ; -- INCLK1_INPUT_FREQUENCY ; 0 ;
603 ; -- VCO_MULTIPLY_BY ; 0 ;
604 ; -- VCO_DIVIDE_BY ; 0 ;
605 +-------------------------------+------------------------------------+
608 +-------------------------------+
609 ; Analysis & Synthesis Messages ;
610 +-------------------------------+
611 Info: *******************************************************************
612 Info: Running Quartus II Analysis & Synthesis
613 Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
614 Info: Processing started: Thu Oct 29 17:12:28 2009
615 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off vga_pll -c vga_pll
616 Info: Revision "vga_pll" was previously opened in Quartus II software version 6.0. Created Quartus II Default Settings File /homes/burban/didelu/dide_16/bsp3/Designflow/ppr/download/vga_pll_assignment_defaults.qdf, which contains the default assignment setting information from Quartus II software version 6.0.
617 Info: Default assignment values were changed in the current version of the Quartus II software -- changes to default assignments values are contained in file /opt/quartus/quartus/linux/assignment_defaults.qdf
618 Info: Found 1 design units, including 1 entities, in source file ../../src/vga_pll.bdf
619 Info: Found entity 1: vga_pll
620 Info: Found 3 design units, including 3 entities, in source file ../../syn/rev_1/vga.vqm
621 Info: Found entity 1: vga_driver
622 Info: Found entity 2: vga_control
623 Info: Found entity 3: vga
624 Info: Found 2 design units, including 1 entities, in source file ../../src/vpll.vhd
625 Info: Found design unit 1: vpll-SYN
626 Info: Found entity 1: vpll
627 Info: Elaborating entity "vga_pll" for the top level hierarchy
628 Info: Elaborating entity "vga" for hierarchy "vga:inst"
629 Info: Elaborating entity "vga_driver" for hierarchy "vga:inst|vga_driver:vga_driver_unit"
630 Info: Elaborating entity "vga_control" for hierarchy "vga:inst|vga_control:vga_control_unit"
631 Info: Elaborating entity "vpll" for hierarchy "vpll:inst1"
632 Warning (10036): Verilog HDL or VHDL warning at vpll.vhd(73): object "locked" assigned a value but never read
633 Info: Elaborating entity "altpll" for hierarchy "vpll:inst1|altpll:altpll_component"
634 Info: Elaborated megafunction instantiation "vpll:inst1|altpll:altpll_component"
635 Info: Instantiated megafunction "vpll:inst1|altpll:altpll_component" with the following parameter:
636 Info: Parameter "bandwidth_type" = "AUTO"
637 Info: Parameter "clk0_duty_cycle" = "50"
638 Info: Parameter "lpm_type" = "altpll"
639 Info: Parameter "clk0_multiply_by" = "5435"
640 Info: Parameter "invalid_lock_multiplier" = "5"
641 Info: Parameter "inclk0_input_frequency" = "30003"
642 Info: Parameter "gate_lock_signal" = "NO"
643 Info: Parameter "clk0_divide_by" = "6666"
644 Info: Parameter "pll_type" = "AUTO"
645 Info: Parameter "valid_lock_multiplier" = "1"
646 Info: Parameter "clk0_time_delay" = "0"
647 Info: Parameter "spread_frequency" = "0"
648 Info: Parameter "intended_device_family" = "Stratix"
649 Info: Parameter "operation_mode" = "NORMAL"
650 Info: Parameter "compensate_clock" = "CLK0"
651 Info: Parameter "clk0_phase_shift" = "0"
652 Info: WYSIWYG I/O primitives converted to equivalent logic
653 Info: WYSIWYG I/O primitive "vga:inst|clk_pin_in" converted to equivalent logic
654 Info: Implemented 235 device resources after synthesis - the final resource count might be different
655 Info: Implemented 2 input pins
656 Info: Implemented 89 output pins
657 Info: Implemented 143 logic cells
658 Info: Implemented 1 ClockLock PLLs
659 Warning: Output port clk0 of PLL "vpll:inst1|altpll:altpll_component|pll" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
660 Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
661 Info: Peak virtual memory: 204 megabytes
662 Info: Processing ended: Thu Oct 29 17:12:32 2009
663 Info: Elapsed time: 00:00:04
664 Info: Total CPU time (on all processors): 00:00:03
projects / dide_16.git / blob