bsp3/Designflow/ppr/download/vga_pll.tcl

   1 # Copyright (C) 1991-2006 Altera Corporation\r
   2 # Your use of Altera Corporation's design tools, logic functions \r
   3 # and other software and tools, and its AMPP partner logic \r
   4 # functions, and any output files any of the foregoing \r
   5 # (including device programming or simulation files), and any \r
   6 # associated documentation or information are expressly subject \r
   7 # to the terms and conditions of the Altera Program License \r
   8 # Subscription Agreement, Altera MegaCore Function License \r
   9 # Agreement, or other applicable license agreement, including, \r
  10 # without limitation, that your use is for the sole purpose of \r
  11 # programming logic devices manufactured by Altera and sold by \r
  12 # Altera or its authorized distributors.  Please refer to the \r
  13 # applicable agreement for further details.\r
  14 \r
  15 # Quartus II: Generate Tcl File for Project\r
  16 # File: vga_pll.tcl\r
  17 # Generated on: Fri Sep 29 09:31:24 2006\r
  18 \r
  19 # Load Quartus II Tcl Project package\r
  20 package require ::quartus::project\r
  21 package require ::quartus::flow\r
  22 \r
  23 set need_to_close_project 0\r
  24 set make_assignments 1\r
  25 \r
  26 # Check that the right project is open\r
  27 if {[is_project_open]} {\r
  28         if {[string compare $quartus(project) "vga_pll"]} {\r
  29                 puts "Project vga_pll is not open"\r
  30                 set make_assignments 0\r
  31         }\r
  32 } else {\r
  33         # Only open if not already open\r
  34         if {[project_exists vga_pll]} {\r
  35                 project_open -cmp vga_pll vga_pll\r
  36         } else {\r
  37                 project_new -cmp vga_pll vga_pll\r
  38         }\r
  39         set need_to_close_project 1\r
  40 }\r
  41 \r
  42 # Make assignments\r
  43 if {$make_assignments} {\r
  44         catch { set_global_assignment -name FAMILY Stratix } result\r
  45         catch { set_global_assignment -name DEVICE EP1S25F672C6 } result\r
  46         catch { set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0 } result\r
  47         catch { set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:04:10  SEPTEMBER 29, 2006" } result\r
  48         catch { set_global_assignment -name LAST_QUARTUS_VERSION 6.0 } result\r
  49         catch { set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Synplify Pro" } result\r
  50         catch { set_global_assignment -name EDA_LMF_FILE synplcty.lmf -section_id eda_design_synthesis } result\r
  51         catch { set_global_assignment -name EDA_INPUT_DATA_FORMAT VQM -section_id eda_design_synthesis } result\r
  52         catch { set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" } result\r
  53         catch { set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation } result\r
  54         catch { set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation } result\r
  55         catch { set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA } result\r
  56         catch { set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672 } result\r
  57         catch { set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 } result\r
  58         catch { set_global_assignment -name BSF_FILE ../../src/vpll.bsf } result\r
  59         catch { set_global_assignment -name VHDL_FILE ../../src/vpll.vhd } result\r
  60         catch { set_global_assignment -name BDF_FILE ../../src/vga_pll.bdf } result\r
  61         catch { set_global_assignment -name VQM_FILE ../../syn/rev_1/vga.vqm } result\r
  62 \r
  63         set_location_assignment PIN_E24 -to b0_pin\r
  64         set_location_assignment PIN_T6 -to b1_pin\r
  65         set_location_assignment PIN_N3 -to board_clk\r
  66         set_location_assignment PIN_E23 -to g0_pin\r
  67         set_location_assignment PIN_T5 -to g1_pin\r
  68         set_location_assignment PIN_T24 -to g2_pin\r
  69         set_location_assignment PIN_F1 -to hsync_pin\r
  70         set_location_assignment PIN_E22 -to r0_pin\r
  71         set_location_assignment PIN_T4 -to r1_pin\r
  72         set_location_assignment PIN_T7 -to r2_pin\r
  73         set_location_assignment PIN_A5 -to reset\r
  74         set_location_assignment PIN_F2 -to vsync_pin\r
  75         set_location_assignment PIN_Y5 -to d_hsync_state[0]\r
  76         set_location_assignment PIN_F19 -to d_hsync_state[1]\r
  77         set_location_assignment PIN_F17 -to d_hsync_state[2]\r
  78         set_location_assignment PIN_Y2 -to d_hsync_state[3]\r
  79         set_location_assignment PIN_F10 -to d_hsync_state[4]\r
  80         set_location_assignment PIN_F9 -to d_hsync_state[5]\r
  81         set_location_assignment PIN_F6 -to d_hsync_state[6]\r
  82         set_location_assignment PIN_H4 -to d_hsync_counter[0]\r
  83         set_location_assignment PIN_G25 -to d_hsync_counter[7]\r
  84         set_location_assignment PIN_G22 -to d_hsync_counter[8]\r
  85         set_location_assignment PIN_G18 -to d_hsync_counter[9]\r
  86         set_location_assignment PIN_F5 -to d_vsync_state[0]\r
  87         set_location_assignment PIN_F4 -to d_vsync_state[1]\r
  88         set_location_assignment PIN_F3 -to d_vsync_state[2]\r
  89         set_location_assignment PIN_M19 -to d_vsync_state[3]\r
  90         set_location_assignment PIN_M18 -to d_vsync_state[4]\r
  91         set_location_assignment PIN_M7 -to d_vsync_state[5]\r
  92         set_location_assignment PIN_M4 -to d_vsync_state[6]\r
  93         set_location_assignment PIN_G9 -to d_vsync_counter[0]\r
  94         set_location_assignment PIN_G6 -to d_vsync_counter[7]\r
  95         set_location_assignment PIN_G4 -to d_vsync_counter[8]\r
  96         set_location_assignment PIN_G2 -to d_vsync_counter[9]\r
  97         set_location_assignment PIN_K6 -to d_line_counter[0]\r
  98         set_location_assignment PIN_K4 -to d_line_counter[1]\r
  99         set_location_assignment PIN_J22 -to d_line_counter[2]\r
 100         set_location_assignment PIN_M9 -to d_line_counter[3]\r
 101         set_location_assignment PIN_M8 -to d_line_counter[4]\r
 102         set_location_assignment PIN_M6 -to d_line_counter[5]\r
 103         set_location_assignment PIN_M5 -to d_line_counter[6]\r
 104         set_location_assignment PIN_L24 -to d_line_counter[7]\r
 105         set_location_assignment PIN_L25 -to d_line_counter[8]\r
 106         set_location_assignment PIN_L23 -to d_column_counter[0]\r
 107         set_location_assignment PIN_L22 -to d_column_counter[1]\r
 108         set_location_assignment PIN_L21 -to d_column_counter[2]\r
 109         set_location_assignment PIN_L20 -to d_column_counter[3]\r
 110         set_location_assignment PIN_L6 -to d_column_counter[4]\r
 111         set_location_assignment PIN_L4 -to d_column_counter[5]\r
 112         set_location_assignment PIN_L2 -to d_column_counter[6]\r
 113         set_location_assignment PIN_K23 -to d_column_counter[7]\r
 114         set_location_assignment PIN_K19 -to d_column_counter[8]\r
 115         set_location_assignment PIN_K5 -to d_column_counter[9]\r
 116         set_location_assignment PIN_L7 -to d_hsync\r
 117         set_location_assignment PIN_L5 -to d_vsync\r
 118         set_location_assignment PIN_F26 -to d_set_hsync_counter\r
 119         set_location_assignment PIN_F24 -to d_set_vsync_counter\r
 120         set_location_assignment PIN_F21 -to d_set_line_counter\r
 121         set_location_assignment PIN_Y23 -to d_set_column_counter\r
 122         set_location_assignment PIN_L3 -to d_r\r
 123         set_location_assignment PIN_K24 -to d_g\r
 124         set_location_assignment PIN_K20 -to d_b\r
 125         set_location_assignment PIN_H18 -to d_v_enable\r
 126         set_location_assignment PIN_J21 -to d_h_enable\r
 127         set_location_assignment PIN_R8 -to seven_seg_pin[0]\r
 128         set_location_assignment PIN_R9 -to seven_seg_pin[1]\r
 129         set_location_assignment PIN_R19 -to seven_seg_pin[2]\r
 130         set_location_assignment PIN_R20 -to seven_seg_pin[3]\r
 131         set_location_assignment PIN_R21 -to seven_seg_pin[4]\r
 132         set_location_assignment PIN_R22 -to seven_seg_pin[5]\r
 133         set_location_assignment PIN_R23 -to seven_seg_pin[6]\r
 134         set_location_assignment PIN_Y11 -to seven_seg_pin[7]\r
 135         set_location_assignment PIN_N7 -to seven_seg_pin[8]\r
 136         set_location_assignment PIN_N8 -to seven_seg_pin[9]\r
 137         set_location_assignment PIN_R4 -to seven_seg_pin[10]\r
 138         set_location_assignment PIN_R6 -to seven_seg_pin[11]\r
 139         set_location_assignment PIN_AA11 -to seven_seg_pin[12]\r
 140         set_location_assignment PIN_T2 -to seven_seg_pin[13]\r
 141         set_location_assignment PIN_K3 -to d_state_clk\r
 142         set_instance_assignment -name SLOW_SLEW_RATE ON -to d_column_counter\r
 143         set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter\r
 144         set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[1]\r
 145         set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[2]\r
 146         set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[3]\r
 147         set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[4]\r
 148         set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[5]\r
 149         set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[6]\r
 150         set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_state\r
 151         set_instance_assignment -name SLOW_SLEW_RATE ON -to d_line_counter\r
 152         set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter\r
 153         set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[1]\r
 154         set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[2]\r
 155         set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[3]\r
 156         set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[4]\r
 157         set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[5]\r
 158         set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[6]\r
 159         set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_state\r
 160         set_instance_assignment -name SLOW_SLEW_RATE ON -to seven_seg_pin\r
 161 \r
 162 \r
 163         # Commit assignments\r
 164         export_assignments\r
 165 \r
 166 execute_flow -compile\r
 167 \r
 168         # Close project\r
 169         if {$need_to_close_project} {\r
 170                 project_close\r
 171         }\r
 172 }\r