1 -------------------------------------------------------------------------------
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2 -- Title : vga architecture
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3 -- Project : LU Digital Design
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4 -------------------------------------------------------------------------------
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6 -- Author : Thomas Handl
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8 -- Created : 2004-04-07
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9 -- Last update: 2006-02-24
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10 -------------------------------------------------------------------------------
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11 -- Description: arch of top level module, the sub-modules are connected here
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12 -------------------------------------------------------------------------------
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13 -- Copyright (c) 2004 TU Wien
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14 -------------------------------------------------------------------------------
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16 -- Date Version Author Description
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17 -- 2004-04-07 1.0 handl Created
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18 -- 2006-02-24 2.0 ST revised
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19 -------------------------------------------------------------------------------
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21 -------------------------------------------------------------------------------
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23 -------------------------------------------------------------------------------
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26 use IEEE.std_logic_1164.all;
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27 use IEEE.std_logic_unsigned.all;
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28 use IEEE.std_logic_arith.all;
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30 use work.vga_pak.all; -- include package
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32 -------------------------------------------------------------------------------
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34 -------------------------------------------------------------------------------
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36 architecture behav of vga is
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38 attribute syn_preserve : boolean;
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39 attribute syn_preserve of behav : architecture is true;
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42 -------------------------------------------------------------------------------
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43 -- component declarations for the modules
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44 -------------------------------------------------------------------------------
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46 component vga_driver
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49 reset : in std_logic;
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50 column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0);
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51 line_counter : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0);
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52 h_enable : out std_logic;
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53 v_enable : out std_logic;
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54 hsync : out std_logic;
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55 vsync : out std_logic;
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56 d_hsync_state : out hsync_state_type;
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57 d_vsync_state : out vsync_state_type;
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58 d_hsync_counter : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0);
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59 d_vsync_counter : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0);
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60 d_set_hsync_counter : out std_logic;
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61 d_set_vsync_counter : out std_logic;
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62 d_set_column_counter : out std_logic;
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63 d_set_line_counter : out std_logic);
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67 component vga_control
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70 reset : in std_logic;
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71 column_counter : in std_logic_vector(COL_CNT_WIDTH-1 downto 0);
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72 line_counter : in std_logic_vector(LINE_CNT_WIDTH-1 downto 0);
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73 h_enable : in std_logic;
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74 v_enable : in std_logic;
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75 r, g, b : out std_logic
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80 component board_driver
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82 reset : in std_logic;
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83 seven_seg : out std_logic_vector(2*SEG_WIDTH-1 downto 0));
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87 -- declare signals needed for internal wiring of these components later
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88 signal column_counter_sig : std_logic_vector(COL_CNT_WIDTH-1 downto 0);
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89 signal line_counter_sig : std_logic_vector(LINE_CNT_WIDTH-1 downto 0);
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90 signal h_enable_sig : std_logic;
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91 signal v_enable_sig : std_logic;
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92 signal r_sig, g_sig, b_sig : std_logic;
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93 signal hsync_sig, vsync_sig : std_logic;
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95 -- declare signals needed for prolongation of reset
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96 signal dly_counter : std_logic_vector(1 downto 0);
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97 signal dly_counter_next : std_logic_vector(1 downto 0);
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98 constant MAX_DLY : std_logic_vector(1 downto 0) := "11";
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99 signal reset_dly : std_logic; --
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100 signal safe_reset : std_logic;
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103 -------------------------------------------------------------------------------
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104 -- prolong duration of reset to prevent glitches at power-up
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105 -------------------------------------------------------------------------------
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109 DELAY_RESET_syn : process(clk_pin) -- synchronous capture
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111 if clk_pin'event and clk_pin = '1' then -- upon rising clock
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112 dly_counter <= dly_counter_next; -- ... capture new counter value
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116 DELAY_RESET_next : process(dly_counter, reset_pin) -- next state logic
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118 if reset_pin = RES_ACT then -- upon reset
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119 dly_counter_next <= (others => '0'); -- ...clear dly counter
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120 elsif dly_counter < MAX_DLY then -- if no oflo
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121 dly_counter_next <= dly_counter + '1'; -- ...increment dly counter
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123 dly_counter_next <= dly_counter; -- freeze dly counter when oflo
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127 DELAY_RESET_out: process(dly_counter)
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129 if dly_counter < MAX_DLY then -- until dly counter reaches maximum
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130 reset_dly <= RES_ACT; -- ...activate delayed reset signal
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131 else -- upon counter oflo
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132 reset_dly <= not(RES_ACT); -- ...finally deactivate delayed reset
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138 COMBINE_RESET: process(reset_pin, reset_dly) -- generate "safe" reset signal
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140 if reset_pin = RES_ACT or reset_dly = RES_ACT then -- ...by combining delayed reset with non-delayed reset input
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141 safe_reset <= RES_ACT;
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143 safe_reset <= not(RES_ACT);
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148 -------------------------------------------------------------------------------
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149 -- instantiate the components and connect to internal and external signals
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150 -------------------------------------------------------------------------------
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153 board_driver_unit : board_driver
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155 reset => safe_reset,
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156 seven_seg => seven_seg_pin);
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159 vga_driver_unit : vga_driver
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162 reset => safe_reset,
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163 column_counter => column_counter_sig,
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164 line_counter => line_counter_sig,
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165 h_enable => h_enable_sig,
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166 v_enable => v_enable_sig,
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167 hsync => hsync_sig,
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168 vsync => vsync_sig,
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169 d_hsync_state => d_hsync_state,
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170 d_vsync_state => d_vsync_state,
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171 d_hsync_counter => d_hsync_counter,
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172 d_vsync_counter => d_vsync_counter,
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173 d_set_hsync_counter => d_set_hsync_counter,
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174 d_set_vsync_counter => d_set_vsync_counter,
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175 d_set_column_counter => d_set_column_counter,
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176 d_set_line_counter => d_set_line_counter);
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178 -- make the wiring for hsync and vsync pins
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179 -- (pin is output only => internal _sig version required to allow readback of signal)
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180 vsync_pin <= vsync_sig;
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181 hsync_pin <= hsync_sig;
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184 vga_control_unit : vga_control
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187 reset => safe_reset,
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188 column_counter => column_counter_sig,
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189 line_counter => line_counter_sig,
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190 h_enable => h_enable_sig,
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191 v_enable => v_enable_sig,
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196 -- make the wiring for RGB pins: drive all pins for same color from one source ("8 color mode")
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197 r0_pin <= r_sig; r1_pin <= r_sig; r2_pin <= r_sig;
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198 g0_pin <= g_sig; g1_pin <= g_sig; g2_pin <= g_sig;
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199 b0_pin <= b_sig; b1_pin <= b_sig;
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202 -- make extra pin connections for debug signals
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203 d_hsync <= hsync_sig; -- make duplicate of signal for debug connector
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204 d_vsync <= vsync_sig; -- make duplicate of signal for debug connector
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205 d_column_counter <= column_counter_sig;
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206 d_line_counter <= line_counter_sig;
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207 d_h_enable <= h_enable_sig;
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208 d_v_enable <= v_enable_sig;
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212 d_state_clk <= clk_pin; -- make duplicate of signal for debug connector
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217 -------------------------------------------------------------------------------
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218 -- END ARCHITECTURE
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219 -------------------------------------------------------------------------------
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