4er slot (3. bsp fertig)

[dide_16.git] / bsp3 / Designflow / ppr / sim / simulation / modelsim / vga.sft

set tool_name "ModelSim-Altera (VHDL)"
set corner_file_list {
        {{"Slow Model"} {vga.vho vga_vhd.sdo}}
}