4er slot (3. bsp fertig)
[dide_16.git] / bsp3 / Designflow / syn / rev_1 / syntmp / vga_flink.htm
1 <table border="0" cellpadding="0" cellspacing="2">
2 <tr>
3 <td nowrap class="content" valign="top">
4 <body bgcolor="#e0e0ff">
5 <font size=3><b>Log File Links:</b><br></font>
6 <br><b>rev_1</b><br>
7 <dt><a href="/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/rpt_vga.areasrr:@XP_FILE" target="srrFrame">Hierarchical Area Report (/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/rpt_vga)</a> (16:49 29-Oct)</dt><br>
8 <br><br><a href="/homes/burban/stdout.log:@XP_FILE" target="srrFrame">Session Log</a><br>