1 Flow report for vga_pll
2 Thu Oct 29 17:13:31 2009
3 Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version
12 4. Flow Non-Default Global Settings
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25 functions, and any output files from any of the foregoing
26 (including device programming or simulation files), and any
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38 +---------------------------------------------------------------------+
40 +--------------------------+------------------------------------------+
41 ; Flow Status ; Successful - Thu Oct 29 17:13:31 2009 ;
42 ; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Full Version ;
43 ; Revision Name ; vga_pll ;
44 ; Top-level Entity Name ; vga_pll ;
46 ; Device ; EP1S25F672C6 ;
47 ; Timing Models ; Final ;
48 ; Met timing requirements ; Yes ;
49 ; Total logic elements ; 141 / 25,660 ( < 1 % ) ;
50 ; Total pins ; 91 / 474 ( 19 % ) ;
51 ; Total virtual pins ; 0 ;
52 ; Total memory bits ; 0 / 1,944,576 ( 0 % ) ;
53 ; DSP block 9-bit elements ; 0 / 80 ( 0 % ) ;
54 ; Total PLLs ; 1 / 6 ( 17 % ) ;
55 ; Total DLLs ; 0 / 2 ( 0 % ) ;
56 +--------------------------+------------------------------------------+
59 +-----------------------------------------+
61 +-------------------+---------------------+
63 +-------------------+---------------------+
64 ; Start date & time ; 10/29/2009 17:12:29 ;
65 ; Main task ; Compilation ;
66 ; Revision Name ; vga_pll ;
67 +-------------------+---------------------+
70 +-----------------------------------------------------------------------------------------------------------------------+
71 ; Flow Non-Default Global Settings ;
72 +------------------------------------+-----------------------------+---------------+-------------+----------------------+
73 ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
74 +------------------------------------+-----------------------------+---------------+-------------+----------------------+
75 ; COMPILER_SIGNATURE_ID ; 91815334056.125683274905785 ; -- ; -- ; -- ;
76 ; EDA_DESIGN_ENTRY_SYNTHESIS_TOOL ; Synplify Pro ; <None> ; -- ; -- ;
77 ; EDA_INPUT_DATA_FORMAT ; Vqm ; -- ; -- ; eda_design_synthesis ;
78 ; EDA_LMF_FILE ; synplcty.lmf ; -- ; -- ; eda_design_synthesis ;
79 ; EDA_OUTPUT_DATA_FORMAT ; Verilog ; -- ; -- ; eda_simulation ;
80 ; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; <None> ; -- ; -- ;
81 ; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
82 ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
83 ; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
84 ; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ;
85 +------------------------------------+-----------------------------+---------------+-------------+----------------------+
88 +-----------------------------------------------------------------------------------------------------------------------------+
90 +-------------------------+--------------+-------------------------+---------------------+------------------------------------+
91 ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
92 +-------------------------+--------------+-------------------------+---------------------+------------------------------------+
93 ; Analysis & Synthesis ; 00:00:04 ; 1.0 ; -- ; 00:00:03 ;
94 ; Fitter ; 00:00:28 ; 1.0 ; -- ; 00:00:28 ;
95 ; Assembler ; 00:00:18 ; 1.0 ; -- ; 00:00:17 ;
96 ; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; -- ; 00:00:00 ;
97 ; EDA Netlist Writer ; 00:00:00 ; 1.0 ; -- ; 00:00:01 ;
98 ; Total ; 00:00:50 ; -- ; -- ; 00:00:49 ;
99 +-------------------------+--------------+-------------------------+---------------------+------------------------------------+
102 +------------------------------------------------------------------------------------+
104 +-------------------------+------------------+---------+------------+----------------+
105 ; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
106 +-------------------------+------------------+---------+------------+----------------+
107 ; Analysis & Synthesis ; ti14 ; Red Hat ; 5 ; x86_64 ;
108 ; Fitter ; ti14 ; Red Hat ; 5 ; x86_64 ;
109 ; Assembler ; ti14 ; Red Hat ; 5 ; x86_64 ;
110 ; Classic Timing Analyzer ; ti14 ; Red Hat ; 5 ; x86_64 ;
111 ; EDA Netlist Writer ; ti14 ; Red Hat ; 5 ; x86_64 ;
112 +-------------------------+------------------+---------+------------+----------------+
118 quartus_map --read_settings_files=on --write_settings_files=off vga_pll -c vga_pll
119 quartus_fit --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll
120 quartus_asm --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll
121 quartus_tan --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll --timing_analysis_only
122 quartus_eda --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll