1 Analysis & Synthesis report for vga
2 Thu Oct 29 16:59:53 2009
3 Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version
10 2. Analysis & Synthesis Summary
11 3. Analysis & Synthesis Settings
12 4. Analysis & Synthesis Source Files Read
13 5. Analysis & Synthesis Resource Usage Summary
14 6. Analysis & Synthesis Resource Utilization by Entity
15 7. General Register Statistics
16 8. Analysis & Synthesis Messages
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39 +------------------------------------------------------------------------+
40 ; Analysis & Synthesis Summary ;
41 +-----------------------------+------------------------------------------+
42 ; Analysis & Synthesis Status ; Successful - Thu Oct 29 16:59:53 2009 ;
43 ; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Full Version ;
44 ; Revision Name ; vga ;
45 ; Top-level Entity Name ; vga ;
47 ; Total logic elements ; 143 ;
49 ; Total virtual pins ; 0 ;
50 ; Total memory bits ; 0 ;
51 ; DSP block 9-bit elements ; 0 ;
54 +-----------------------------+------------------------------------------+
57 +----------------------------------------------------------------------------------------------------------+
58 ; Analysis & Synthesis Settings ;
59 +----------------------------------------------------------------+--------------------+--------------------+
60 ; Option ; Setting ; Default Value ;
61 +----------------------------------------------------------------+--------------------+--------------------+
62 ; Device ; EP1S25F672C6 ; ;
63 ; Top-level entity name ; vga ; vga ;
64 ; Family name ; Stratix ; Stratix II ;
65 ; Type of Retiming Performed During Resynthesis ; Full ; ;
66 ; Resynthesis Optimization Effort ; Normal ; ;
67 ; Physical Synthesis Level for Resynthesis ; Normal ; ;
68 ; Use Generated Physical Constraints File ; On ; ;
69 ; Use smart compilation ; Off ; Off ;
70 ; Restructure Multiplexers ; Auto ; Auto ;
71 ; Create Debugging Nodes for IP Cores ; Off ; Off ;
72 ; Preserve fewer node names ; On ; On ;
73 ; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
74 ; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
75 ; VHDL Version ; VHDL93 ; VHDL93 ;
76 ; State Machine Processing ; Auto ; Auto ;
77 ; Safe State Machine ; Off ; Off ;
78 ; Extract Verilog State Machines ; On ; On ;
79 ; Extract VHDL State Machines ; On ; On ;
80 ; Ignore Verilog initial constructs ; Off ; Off ;
81 ; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
82 ; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
83 ; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
84 ; Parallel Synthesis ; Off ; Off ;
85 ; DSP Block Balancing ; Auto ; Auto ;
86 ; NOT Gate Push-Back ; On ; On ;
87 ; Power-Up Don't Care ; On ; On ;
88 ; Remove Redundant Logic Cells ; Off ; Off ;
89 ; Remove Duplicate Registers ; On ; On ;
90 ; Ignore CARRY Buffers ; Off ; Off ;
91 ; Ignore CASCADE Buffers ; Off ; Off ;
92 ; Ignore GLOBAL Buffers ; Off ; Off ;
93 ; Ignore ROW GLOBAL Buffers ; Off ; Off ;
94 ; Ignore LCELL Buffers ; Off ; Off ;
95 ; Ignore SOFT Buffers ; On ; On ;
96 ; Limit AHDL Integers to 32 Bits ; Off ; Off ;
97 ; Optimization Technique ; Balanced ; Balanced ;
98 ; Carry Chain Length ; 70 ; 70 ;
99 ; Auto Carry Chains ; On ; On ;
100 ; Auto Open-Drain Pins ; On ; On ;
101 ; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
102 ; Auto ROM Replacement ; On ; On ;
103 ; Auto RAM Replacement ; On ; On ;
104 ; Auto DSP Block Replacement ; On ; On ;
105 ; Auto Shift Register Replacement ; Auto ; Auto ;
106 ; Auto Clock Enable Replacement ; On ; On ;
107 ; Strict RAM Replacement ; Off ; Off ;
108 ; Allow Synchronous Control Signals ; On ; On ;
109 ; Force Use of Synchronous Clear Signals ; Off ; Off ;
110 ; Auto RAM Block Balancing ; On ; On ;
111 ; Auto RAM to Logic Cell Conversion ; Off ; Off ;
112 ; Auto Resource Sharing ; Off ; Off ;
113 ; Allow Any RAM Size For Recognition ; Off ; Off ;
114 ; Allow Any ROM Size For Recognition ; Off ; Off ;
115 ; Allow Any Shift Register Size For Recognition ; Off ; Off ;
116 ; Use LogicLock Constraints during Resource Balancing ; On ; On ;
117 ; Ignore translate_off and synthesis_off directives ; Off ; Off ;
118 ; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
119 ; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
120 ; Synchronization Register Chain Length ; 2 ; 2 ;
121 ; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
122 ; HDL message level ; Level2 ; Level2 ;
123 ; Suppress Register Optimization Related Messages ; Off ; Off ;
124 ; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
125 ; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
126 ; Clock MUX Protection ; On ; On ;
127 ; Block Design Naming ; Auto ; Auto ;
128 ; Synthesis Effort ; Auto ; Auto ;
129 ; Allows Asynchronous Clear Usage For Shift Register Replacement ; On ; On ;
130 ; Analysis & Synthesis Message Level ; Medium ; Medium ;
131 +----------------------------------------------------------------+--------------------+--------------------+
134 +----------------------------------------------------------------------------------------------------------------------------------------------------------+
135 ; Analysis & Synthesis Source Files Read ;
136 +----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------+
137 ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
138 +----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------+
139 ; ../../syn/rev_1/vga.vqm ; yes ; User Verilog Quartus Mapping File ; /homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm ;
140 +----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------+
143 +-------------------------------------------------------+
144 ; Analysis & Synthesis Resource Usage Summary ;
145 +---------------------------------------------+---------+
147 +---------------------------------------------+---------+
148 ; Total logic elements ; 143 ;
149 ; -- Combinational with no register ; 81 ;
150 ; -- Register only ; 3 ;
151 ; -- Combinational with a register ; 59 ;
153 ; Logic element usage by number of LUT inputs ; ;
154 ; -- 4 input functions ; 53 ;
155 ; -- 3 input functions ; 32 ;
156 ; -- 2 input functions ; 54 ;
157 ; -- 1 input functions ; 1 ;
158 ; -- 0 input functions ; 0 ;
160 ; Logic elements by mode ; ;
161 ; -- normal mode ; 109 ;
162 ; -- arithmetic mode ; 34 ;
164 ; -- register cascade mode ; 0 ;
165 ; -- synchronous clear/load mode ; 48 ;
166 ; -- asynchronous clear/load mode ; 3 ;
168 ; Total registers ; 62 ;
169 ; Total logic cells in carry chains ; 40 ;
171 ; Maximum fan-out node ; clk_pin ;
172 ; Maximum fan-out ; 63 ;
173 ; Total fan-out ; 666 ;
174 ; Average fan-out ; 2.85 ;
175 +---------------------------------------------+---------+
178 +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
179 ; Analysis & Synthesis Resource Utilization by Entity ;
180 +-----------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------+--------------+
181 ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
182 +-----------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------+--------------+
183 ; |vga ; 143 (2) ; 62 ; 0 ; 0 ; 0 ; 0 ; 0 ; 91 ; 0 ; 81 (0) ; 3 (0) ; 59 (2) ; 40 (0) ; 0 (0) ; |vga ; work ;
184 ; |vga_control:vga_control_unit| ; 10 (10) ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 (0) ; |vga|vga_control:vga_control_unit ; work ;
185 ; |vga_driver:vga_driver_unit| ; 131 (131) ; 57 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 74 (74) ; 3 (3) ; 54 (54) ; 40 (40) ; 0 (0) ; |vga|vga_driver:vga_driver_unit ; work ;
186 +-----------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------+--------------+
187 Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
190 +------------------------------------------------------+
191 ; General Register Statistics ;
192 +----------------------------------------------+-------+
193 ; Statistic ; Value ;
194 +----------------------------------------------+-------+
195 ; Total registers ; 62 ;
196 ; Number of registers using Synchronous Clear ; 48 ;
197 ; Number of registers using Synchronous Load ; 20 ;
198 ; Number of registers using Asynchronous Clear ; 3 ;
199 ; Number of registers using Asynchronous Load ; 0 ;
200 ; Number of registers using Clock Enable ; 12 ;
201 ; Number of registers using Preset ; 0 ;
202 +----------------------------------------------+-------+
205 +-------------------------------+
206 ; Analysis & Synthesis Messages ;
207 +-------------------------------+
208 Info: *******************************************************************
209 Info: Running Quartus II Analysis & Synthesis
210 Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
211 Info: Processing started: Thu Oct 29 16:59:47 2009
212 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off vga -c vga
213 Info: Found 3 design units, including 3 entities, in source file ../../syn/rev_1/vga.vqm
214 Info: Found entity 1: vga_driver
215 Info: Found entity 2: vga_control
216 Info: Found entity 3: vga
217 Info: Elaborating entity "vga" for the top level hierarchy
218 Info: Elaborating entity "vga_driver" for hierarchy "vga_driver:vga_driver_unit"
219 Info: Elaborating entity "vga_control" for hierarchy "vga_control:vga_control_unit"
220 Info: Implemented 234 device resources after synthesis - the final resource count might be different
221 Info: Implemented 2 input pins
222 Info: Implemented 89 output pins
223 Info: Implemented 143 logic cells
224 Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
225 Info: Peak virtual memory: 185 megabytes
226 Info: Processing ended: Thu Oct 29 16:59:53 2009
227 Info: Elapsed time: 00:00:06
228 Info: Total CPU time (on all processors): 00:00:02
projects / dide_16.git / blob