bsp3/Designflow/syn/rev_1/vga.vqm

   1 //
   2 // Written by Synplify
   3 // Product Version "C-2009.06"
   4 // Program "Synplify Pro", Mapper "map450rc, Build 029R"
   5 // Thu Oct 29 16:49:33 2009
   6 //
   7 // Source file index table:
   8 // Object locations will have the form <file>:<line>
   9 // file 0 "noname"
  10 // file 1 "\/opt/synplify/fpga_c200906/lib/vhd/std.vhd "
  11 // file 2 "\/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pak.vhd "
  12 // file 3 "\/opt/synplify/fpga_c200906/lib/vhd/std1164.vhd "
  13 // file 4 "\/opt/synplify/fpga_c200906/lib/vhd/unsigned.vhd "
  14 // file 5 "\/opt/synplify/fpga_c200906/lib/vhd/arith.vhd "
  15 // file 6 "\/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_ent.vhd "
  16 // file 7 "\/homes/burban/didelu/dide_16/bsp3/Designflow/src/board_driver_ent.vhd "
  17 // file 8 "\/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_control_ent.vhd "
  18 // file 9 "\/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_driver_ent.vhd "
  19 // file 10 "\/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_arc.vhd "
  20 // file 11 "\/homes/burban/didelu/dide_16/bsp3/Designflow/src/board_driver_arc.vhd "
  21 // file 12 "\/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_control_arc.vhd "
  22 // file 13 "\/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_driver_arc.vhd "
  23
  24 // VQM4.1+
  25 module vga_driver (
  26   line_counter_sig_0,
  27   line_counter_sig_1,
  28   line_counter_sig_2,
  29   line_counter_sig_3,
  30   line_counter_sig_4,
  31   line_counter_sig_5,
  32   line_counter_sig_6,
  33   line_counter_sig_7,
  34   line_counter_sig_8,
  35   dly_counter_1,
  36   dly_counter_0,
  37   vsync_state_2,
  38   vsync_state_5,
  39   vsync_state_3,
  40   vsync_state_6,
  41   vsync_state_4,
  42   vsync_state_1,
  43   vsync_state_0,
  44   hsync_state_2,
  45   hsync_state_4,
  46   hsync_state_0,
  47   hsync_state_5,
  48   hsync_state_1,
  49   hsync_state_3,
  50   hsync_state_6,
  51   column_counter_sig_0,
  52   column_counter_sig_1,
  53   column_counter_sig_2,
  54   column_counter_sig_3,
  55   column_counter_sig_4,
  56   column_counter_sig_5,
  57   column_counter_sig_6,
  58   column_counter_sig_7,
  59   column_counter_sig_8,
  60   column_counter_sig_9,
  61   vsync_counter_9,
  62   vsync_counter_8,
  63   vsync_counter_7,
  64   vsync_counter_6,
  65   vsync_counter_5,
  66   vsync_counter_4,
  67   vsync_counter_3,
  68   vsync_counter_2,
  69   vsync_counter_1,
  70   vsync_counter_0,
  71   hsync_counter_9,
  72   hsync_counter_8,
  73   hsync_counter_7,
  74   hsync_counter_6,
  75   hsync_counter_5,
  76   hsync_counter_4,
  77   hsync_counter_3,
  78   hsync_counter_2,
  79   hsync_counter_1,
  80   hsync_counter_0,
  81   d_set_vsync_counter,
  82   un10_column_counter_siglt6_1,
  83   un10_column_counter_siglt6_3,
  84   v_sync,
  85   h_sync,
  86   h_enable_sig,
  87   v_enable_sig,
  88   reset_pin_c,
  89   un6_dly_counter_0_x,
  90   d_set_hsync_counter,
  91   clk_pin_c
  92 )
  93 ;
  94 output line_counter_sig_0 ;
  95 output line_counter_sig_1 ;
  96 output line_counter_sig_2 ;
  97 output line_counter_sig_3 ;
  98 output line_counter_sig_4 ;
  99 output line_counter_sig_5 ;
 100 output line_counter_sig_6 ;
 101 output line_counter_sig_7 ;
 102 output line_counter_sig_8 ;
 103 input dly_counter_1 ;
 104 input dly_counter_0 ;
 105 output vsync_state_2 ;
 106 output vsync_state_5 ;
 107 output vsync_state_3 ;
 108 output vsync_state_6 ;
 109 output vsync_state_4 ;
 110 output vsync_state_1 ;
 111 output vsync_state_0 ;
 112 output hsync_state_2 ;
 113 output hsync_state_4 ;
 114 output hsync_state_0 ;
 115 output hsync_state_5 ;
 116 output hsync_state_1 ;
 117 output hsync_state_3 ;
 118 output hsync_state_6 ;
 119 output column_counter_sig_0 ;
 120 output column_counter_sig_1 ;
 121 output column_counter_sig_2 ;
 122 output column_counter_sig_3 ;
 123 output column_counter_sig_4 ;
 124 output column_counter_sig_5 ;
 125 output column_counter_sig_6 ;
 126 output column_counter_sig_7 ;
 127 output column_counter_sig_8 ;
 128 output column_counter_sig_9 ;
 129 output vsync_counter_9 ;
 130 output vsync_counter_8 ;
 131 output vsync_counter_7 ;
 132 output vsync_counter_6 ;
 133 output vsync_counter_5 ;
 134 output vsync_counter_4 ;
 135 output vsync_counter_3 ;
 136 output vsync_counter_2 ;
 137 output vsync_counter_1 ;
 138 output vsync_counter_0 ;
 139 output hsync_counter_9 ;
 140 output hsync_counter_8 ;
 141 output hsync_counter_7 ;
 142 output hsync_counter_6 ;
 143 output hsync_counter_5 ;
 144 output hsync_counter_4 ;
 145 output hsync_counter_3 ;
 146 output hsync_counter_2 ;
 147 output hsync_counter_1 ;
 148 output hsync_counter_0 ;
 149 output d_set_vsync_counter ;
 150 output un10_column_counter_siglt6_1 ;
 151 output un10_column_counter_siglt6_3 ;
 152 output v_sync ;
 153 output h_sync ;
 154 output h_enable_sig ;
 155 output v_enable_sig ;
 156 input reset_pin_c ;
 157 output un6_dly_counter_0_x ;
 158 output d_set_hsync_counter ;
 159 input clk_pin_c ;
 160 wire line_counter_sig_0 ;
 161 wire line_counter_sig_1 ;
 162 wire line_counter_sig_2 ;
 163 wire line_counter_sig_3 ;
 164 wire line_counter_sig_4 ;
 165 wire line_counter_sig_5 ;
 166 wire line_counter_sig_6 ;
 167 wire line_counter_sig_7 ;
 168 wire line_counter_sig_8 ;
 169 wire dly_counter_1 ;
 170 wire dly_counter_0 ;
 171 wire vsync_state_2 ;
 172 wire vsync_state_5 ;
 173 wire vsync_state_3 ;
 174 wire vsync_state_6 ;
 175 wire vsync_state_4 ;
 176 wire vsync_state_1 ;
 177 wire vsync_state_0 ;
 178 wire hsync_state_2 ;
 179 wire hsync_state_4 ;
 180 wire hsync_state_0 ;
 181 wire hsync_state_5 ;
 182 wire hsync_state_1 ;
 183 wire hsync_state_3 ;
 184 wire hsync_state_6 ;
 185 wire column_counter_sig_0 ;
 186 wire column_counter_sig_1 ;
 187 wire column_counter_sig_2 ;
 188 wire column_counter_sig_3 ;
 189 wire column_counter_sig_4 ;
 190 wire column_counter_sig_5 ;
 191 wire column_counter_sig_6 ;
 192 wire column_counter_sig_7 ;
 193 wire column_counter_sig_8 ;
 194 wire column_counter_sig_9 ;
 195 wire vsync_counter_9 ;
 196 wire vsync_counter_8 ;
 197 wire vsync_counter_7 ;
 198 wire vsync_counter_6 ;
 199 wire vsync_counter_5 ;
 200 wire vsync_counter_4 ;
 201 wire vsync_counter_3 ;
 202 wire vsync_counter_2 ;
 203 wire vsync_counter_1 ;
 204 wire vsync_counter_0 ;
 205 wire hsync_counter_9 ;
 206 wire hsync_counter_8 ;
 207 wire hsync_counter_7 ;
 208 wire hsync_counter_6 ;
 209 wire hsync_counter_5 ;
 210 wire hsync_counter_4 ;
 211 wire hsync_counter_3 ;
 212 wire hsync_counter_2 ;
 213 wire hsync_counter_1 ;
 214 wire hsync_counter_0 ;
 215 wire d_set_vsync_counter ;
 216 wire un10_column_counter_siglt6_1 ;
 217 wire un10_column_counter_siglt6_3 ;
 218 wire v_sync ;
 219 wire h_sync ;
 220 wire h_enable_sig ;
 221 wire v_enable_sig ;
 222 wire reset_pin_c ;
 223 wire un6_dly_counter_0_x ;
 224 wire d_set_hsync_counter ;
 225 wire clk_pin_c ;
 226 wire [8:0] hsync_counter_cout;
 227 wire [8:0] vsync_counter_cout;
 228 wire [9:1] un2_column_counter_next_combout;
 229 wire [9:1] un1_line_counter_sig_combout;
 230 wire [7:1] un1_line_counter_sig_cout;
 231 wire [1:1] un1_line_counter_sig_a_cout;
 232 wire [7:0] un2_column_counter_next_cout;
 233 wire hsync_counter_next_1_sqmuxa ;
 234 wire G_2_i ;
 235 wire un9_hsync_counterlt9 ;
 236 wire vsync_counter_next_1_sqmuxa ;
 237 wire G_16_i ;
 238 wire un9_vsync_counterlt9 ;
 239 wire un10_column_counter_siglto9 ;
 240 wire column_counter_next_0_sqmuxa_1_1 ;
 241 wire vsync_state_3_iv_0_0__g0_0_a3_0 ;
 242 wire vsync_state_next_2_sqmuxa ;
 243 wire un12_vsync_counter_7 ;
 244 wire un13_vsync_counter_4 ;
 245 wire un10_line_counter_siglto8 ;
 246 wire line_counter_next_0_sqmuxa_1_1 ;
 247 wire v_enable_sig_1_0_0_0_g0_i_o4 ;
 248 wire h_enable_sig_1_0_0_0_g0_i_o4 ;
 249 wire h_sync_1_0_0_0_g1 ;
 250 wire v_sync_1_0_0_0_g1 ;
 251 wire un14_vsync_counter_8 ;
 252 wire hsync_state_3_0_0_0__g0_0 ;
 253 wire un10_hsync_counter_3 ;
 254 wire un10_hsync_counter_1 ;
 255 wire un10_hsync_counter_4 ;
 256 wire un12_hsync_counter ;
 257 wire un11_hsync_counter_2 ;
 258 wire un11_hsync_counter_3 ;
 259 wire un13_hsync_counter ;
 260 wire vsync_state_next_1_sqmuxa_1 ;
 261 wire vsync_state_next_1_sqmuxa_3 ;
 262 wire un1_vsync_state_next_1_sqmuxa_0 ;
 263 wire hsync_state_next_1_sqmuxa_1 ;
 264 wire hsync_state_next_1_sqmuxa_2 ;
 265 wire un1_hsync_state_next_1_sqmuxa_0 ;
 266 wire un12_vsync_counter_6 ;
 267 wire un15_vsync_counter_4 ;
 268 wire vsync_state_next_1_sqmuxa_2 ;
 269 wire un10_column_counter_siglt6 ;
 270 wire un10_line_counter_siglto5 ;
 271 wire un9_vsync_counterlt9_5 ;
 272 wire un9_vsync_counterlt9_6 ;
 273 wire un12_hsync_counter_3 ;
 274 wire un12_hsync_counter_4 ;
 275 wire un13_hsync_counter_2 ;
 276 wire un13_hsync_counter_7 ;
 277 wire un9_hsync_counterlt9_3 ;
 278 wire un10_line_counter_siglt4_2 ;
 279 wire un13_vsync_counter_3 ;
 280 wire un15_vsync_counter_3 ;
 281 wire un1_vsync_state_2_0 ;
 282 wire un1_hsync_state_3_0 ;
 283 wire VCC ;
 284 wire GND ;
 285 wire line_counter_next_0_sqmuxa_1_1_i ;
 286 wire column_counter_next_0_sqmuxa_1_1_i ;
 287 wire un9_vsync_counterlt9_i ;
 288 wire G_16_i_i ;
 289 wire un9_hsync_counterlt9_i ;
 290 wire G_2_i_i ;
 291 //@1:1
 292   assign VCC = 1'b1;
 293   assign GND = 1'b0;
 294 // @13:158
 295   stratix_lcell hsync_counter_0_ (
 296         .regout(hsync_counter_0),
 297         .cout(hsync_counter_cout[0]),
 298         .clk(clk_pin_c),
 299         .dataa(hsync_counter_0),
 300         .datab(VCC),
 301         .datac(hsync_counter_next_1_sqmuxa),
 302         .datad(VCC),
 303         .aclr(GND),
 304         .sclr(G_2_i_i),
 305         .sload(un9_hsync_counterlt9_i),
 306         .ena(VCC),
 307         .inverta(GND),
 308         .aload(GND),
 309         .regcascin(GND)
 310 );
 311 defparam hsync_counter_0_.operation_mode="arithmetic";
 312 defparam hsync_counter_0_.output_mode="reg_only";
 313 defparam hsync_counter_0_.lut_mask="55aa";
 314 defparam hsync_counter_0_.synch_mode="on";
 315 defparam hsync_counter_0_.sum_lutc_input="datac";
 316 // @13:158
 317   stratix_lcell hsync_counter_1_ (
 318         .regout(hsync_counter_1),
 319         .cout(hsync_counter_cout[1]),
 320         .clk(clk_pin_c),
 321         .dataa(hsync_counter_1),
 322         .datab(VCC),
 323         .datac(hsync_counter_next_1_sqmuxa),
 324         .datad(VCC),
 325         .aclr(GND),
 326         .sclr(G_2_i_i),
 327         .sload(un9_hsync_counterlt9_i),
 328         .ena(VCC),
 329         .cin(hsync_counter_cout[0]),
 330         .inverta(GND),
 331         .aload(GND),
 332         .regcascin(GND)
 333 );
 334 defparam hsync_counter_1_.cin_used="true";
 335 defparam hsync_counter_1_.operation_mode="arithmetic";
 336 defparam hsync_counter_1_.output_mode="reg_only";
 337 defparam hsync_counter_1_.lut_mask="5aa0";
 338 defparam hsync_counter_1_.synch_mode="on";
 339 defparam hsync_counter_1_.sum_lutc_input="cin";
 340 // @13:158
 341   stratix_lcell hsync_counter_2_ (
 342         .regout(hsync_counter_2),
 343         .cout(hsync_counter_cout[2]),
 344         .clk(clk_pin_c),
 345         .dataa(hsync_counter_2),
 346         .datab(VCC),
 347         .datac(hsync_counter_next_1_sqmuxa),
 348         .datad(VCC),
 349         .aclr(GND),
 350         .sclr(G_2_i_i),
 351         .sload(un9_hsync_counterlt9_i),
 352         .ena(VCC),
 353         .cin(hsync_counter_cout[1]),
 354         .inverta(GND),
 355         .aload(GND),
 356         .regcascin(GND)
 357 );
 358 defparam hsync_counter_2_.cin_used="true";
 359 defparam hsync_counter_2_.operation_mode="arithmetic";
 360 defparam hsync_counter_2_.output_mode="reg_only";
 361 defparam hsync_counter_2_.lut_mask="5aa0";
 362 defparam hsync_counter_2_.synch_mode="on";
 363 defparam hsync_counter_2_.sum_lutc_input="cin";
 364 // @13:158
 365   stratix_lcell hsync_counter_3_ (
 366         .regout(hsync_counter_3),
 367         .cout(hsync_counter_cout[3]),
 368         .clk(clk_pin_c),
 369         .dataa(hsync_counter_3),
 370         .datab(VCC),
 371         .datac(hsync_counter_next_1_sqmuxa),
 372         .datad(VCC),
 373         .aclr(GND),
 374         .sclr(G_2_i_i),
 375         .sload(un9_hsync_counterlt9_i),
 376         .ena(VCC),
 377         .cin(hsync_counter_cout[2]),
 378         .inverta(GND),
 379         .aload(GND),
 380         .regcascin(GND)
 381 );
 382 defparam hsync_counter_3_.cin_used="true";
 383 defparam hsync_counter_3_.operation_mode="arithmetic";
 384 defparam hsync_counter_3_.output_mode="reg_only";
 385 defparam hsync_counter_3_.lut_mask="5aa0";
 386 defparam hsync_counter_3_.synch_mode="on";
 387 defparam hsync_counter_3_.sum_lutc_input="cin";
 388 // @13:158
 389   stratix_lcell hsync_counter_4_ (
 390         .regout(hsync_counter_4),
 391         .cout(hsync_counter_cout[4]),
 392         .clk(clk_pin_c),
 393         .dataa(hsync_counter_4),
 394         .datab(VCC),
 395         .datac(hsync_counter_next_1_sqmuxa),
 396         .datad(VCC),
 397         .aclr(GND),
 398         .sclr(G_2_i_i),
 399         .sload(un9_hsync_counterlt9_i),
 400         .ena(VCC),
 401         .cin(hsync_counter_cout[3]),
 402         .inverta(GND),
 403         .aload(GND),
 404         .regcascin(GND)
 405 );
 406 defparam hsync_counter_4_.cin_used="true";
 407 defparam hsync_counter_4_.operation_mode="arithmetic";
 408 defparam hsync_counter_4_.output_mode="reg_only";
 409 defparam hsync_counter_4_.lut_mask="5aa0";
 410 defparam hsync_counter_4_.synch_mode="on";
 411 defparam hsync_counter_4_.sum_lutc_input="cin";
 412 // @13:158
 413   stratix_lcell hsync_counter_5_ (
 414         .regout(hsync_counter_5),
 415         .cout(hsync_counter_cout[5]),
 416         .clk(clk_pin_c),
 417         .dataa(hsync_counter_5),
 418         .datab(VCC),
 419         .datac(hsync_counter_next_1_sqmuxa),
 420         .datad(VCC),
 421         .aclr(GND),
 422         .sclr(G_2_i_i),
 423         .sload(un9_hsync_counterlt9_i),
 424         .ena(VCC),
 425         .cin(hsync_counter_cout[4]),
 426         .inverta(GND),
 427         .aload(GND),
 428         .regcascin(GND)
 429 );
 430 defparam hsync_counter_5_.cin_used="true";
 431 defparam hsync_counter_5_.operation_mode="arithmetic";
 432 defparam hsync_counter_5_.output_mode="reg_only";
 433 defparam hsync_counter_5_.lut_mask="5aa0";
 434 defparam hsync_counter_5_.synch_mode="on";
 435 defparam hsync_counter_5_.sum_lutc_input="cin";
 436 // @13:158
 437   stratix_lcell hsync_counter_6_ (
 438         .regout(hsync_counter_6),
 439         .cout(hsync_counter_cout[6]),
 440         .clk(clk_pin_c),
 441         .dataa(hsync_counter_6),
 442         .datab(VCC),
 443         .datac(hsync_counter_next_1_sqmuxa),
 444         .datad(VCC),
 445         .aclr(GND),
 446         .sclr(G_2_i_i),
 447         .sload(un9_hsync_counterlt9_i),
 448         .ena(VCC),
 449         .cin(hsync_counter_cout[5]),
 450         .inverta(GND),
 451         .aload(GND),
 452         .regcascin(GND)
 453 );
 454 defparam hsync_counter_6_.cin_used="true";
 455 defparam hsync_counter_6_.operation_mode="arithmetic";
 456 defparam hsync_counter_6_.output_mode="reg_only";
 457 defparam hsync_counter_6_.lut_mask="5aa0";
 458 defparam hsync_counter_6_.synch_mode="on";
 459 defparam hsync_counter_6_.sum_lutc_input="cin";
 460 // @13:158
 461   stratix_lcell hsync_counter_7_ (
 462         .regout(hsync_counter_7),
 463         .cout(hsync_counter_cout[7]),
 464         .clk(clk_pin_c),
 465         .dataa(hsync_counter_7),
 466         .datab(VCC),
 467         .datac(hsync_counter_next_1_sqmuxa),
 468         .datad(VCC),
 469         .aclr(GND),
 470         .sclr(G_2_i_i),
 471         .sload(un9_hsync_counterlt9_i),
 472         .ena(VCC),
 473         .cin(hsync_counter_cout[6]),
 474         .inverta(GND),
 475         .aload(GND),
 476         .regcascin(GND)
 477 );
 478 defparam hsync_counter_7_.cin_used="true";
 479 defparam hsync_counter_7_.operation_mode="arithmetic";
 480 defparam hsync_counter_7_.output_mode="reg_only";
 481 defparam hsync_counter_7_.lut_mask="5aa0";
 482 defparam hsync_counter_7_.synch_mode="on";
 483 defparam hsync_counter_7_.sum_lutc_input="cin";
 484 // @13:158
 485   stratix_lcell hsync_counter_8_ (
 486         .regout(hsync_counter_8),
 487         .cout(hsync_counter_cout[8]),
 488         .clk(clk_pin_c),
 489         .dataa(hsync_counter_8),
 490         .datab(VCC),
 491         .datac(hsync_counter_next_1_sqmuxa),
 492         .datad(VCC),
 493         .aclr(GND),
 494         .sclr(G_2_i_i),
 495         .sload(un9_hsync_counterlt9_i),
 496         .ena(VCC),
 497         .cin(hsync_counter_cout[7]),
 498         .inverta(GND),
 499         .aload(GND),
 500         .regcascin(GND)
 501 );
 502 defparam hsync_counter_8_.cin_used="true";
 503 defparam hsync_counter_8_.operation_mode="arithmetic";
 504 defparam hsync_counter_8_.output_mode="reg_only";
 505 defparam hsync_counter_8_.lut_mask="5aa0";
 506 defparam hsync_counter_8_.synch_mode="on";
 507 defparam hsync_counter_8_.sum_lutc_input="cin";
 508 // @13:158
 509   stratix_lcell hsync_counter_9_ (
 510         .regout(hsync_counter_9),
 511         .clk(clk_pin_c),
 512         .dataa(hsync_counter_9),
 513         .datab(VCC),
 514         .datac(hsync_counter_next_1_sqmuxa),
 515         .datad(VCC),
 516         .aclr(GND),
 517         .sclr(G_2_i_i),
 518         .sload(un9_hsync_counterlt9_i),
 519         .ena(VCC),
 520         .cin(hsync_counter_cout[8]),
 521         .inverta(GND),
 522         .aload(GND),
 523         .regcascin(GND)
 524 );
 525 defparam hsync_counter_9_.cin_used="true";
 526 defparam hsync_counter_9_.operation_mode="normal";
 527 defparam hsync_counter_9_.output_mode="reg_only";
 528 defparam hsync_counter_9_.lut_mask="5a5a";
 529 defparam hsync_counter_9_.synch_mode="on";
 530 defparam hsync_counter_9_.sum_lutc_input="cin";
 531 // @13:267
 532   stratix_lcell vsync_counter_0_ (
 533         .regout(vsync_counter_0),
 534         .cout(vsync_counter_cout[0]),
 535         .clk(clk_pin_c),
 536         .dataa(vsync_counter_0),
 537         .datab(d_set_hsync_counter),
 538         .datac(vsync_counter_next_1_sqmuxa),
 539         .datad(VCC),
 540         .aclr(GND),
 541         .sclr(G_16_i_i),
 542         .sload(un9_vsync_counterlt9_i),
 543         .ena(VCC),
 544         .inverta(GND),
 545         .aload(GND),
 546         .regcascin(GND)
 547 );
 548 defparam vsync_counter_0_.operation_mode="arithmetic";
 549 defparam vsync_counter_0_.output_mode="reg_only";
 550 defparam vsync_counter_0_.lut_mask="6688";
 551 defparam vsync_counter_0_.synch_mode="on";
 552 defparam vsync_counter_0_.sum_lutc_input="datac";
 553 // @13:267
 554   stratix_lcell vsync_counter_1_ (
 555         .regout(vsync_counter_1),
 556         .cout(vsync_counter_cout[1]),
 557         .clk(clk_pin_c),
 558         .dataa(vsync_counter_1),
 559         .datab(VCC),
 560         .datac(vsync_counter_next_1_sqmuxa),
 561         .datad(VCC),
 562         .aclr(GND),
 563         .sclr(G_16_i_i),
 564         .sload(un9_vsync_counterlt9_i),
 565         .ena(VCC),
 566         .cin(vsync_counter_cout[0]),
 567         .inverta(GND),
 568         .aload(GND),
 569         .regcascin(GND)
 570 );
 571 defparam vsync_counter_1_.cin_used="true";
 572 defparam vsync_counter_1_.operation_mode="arithmetic";
 573 defparam vsync_counter_1_.output_mode="reg_only";
 574 defparam vsync_counter_1_.lut_mask="5aa0";
 575 defparam vsync_counter_1_.synch_mode="on";
 576 defparam vsync_counter_1_.sum_lutc_input="cin";
 577 // @13:267
 578   stratix_lcell vsync_counter_2_ (
 579         .regout(vsync_counter_2),
 580         .cout(vsync_counter_cout[2]),
 581         .clk(clk_pin_c),
 582         .dataa(vsync_counter_2),
 583         .datab(VCC),
 584         .datac(vsync_counter_next_1_sqmuxa),
 585         .datad(VCC),
 586         .aclr(GND),
 587         .sclr(G_16_i_i),
 588         .sload(un9_vsync_counterlt9_i),
 589         .ena(VCC),
 590         .cin(vsync_counter_cout[1]),
 591         .inverta(GND),
 592         .aload(GND),
 593         .regcascin(GND)
 594 );
 595 defparam vsync_counter_2_.cin_used="true";
 596 defparam vsync_counter_2_.operation_mode="arithmetic";
 597 defparam vsync_counter_2_.output_mode="reg_only";
 598 defparam vsync_counter_2_.lut_mask="5aa0";
 599 defparam vsync_counter_2_.synch_mode="on";
 600 defparam vsync_counter_2_.sum_lutc_input="cin";
 601 // @13:267
 602   stratix_lcell vsync_counter_3_ (
 603         .regout(vsync_counter_3),
 604         .cout(vsync_counter_cout[3]),
 605         .clk(clk_pin_c),
 606         .dataa(vsync_counter_3),
 607         .datab(VCC),
 608         .datac(vsync_counter_next_1_sqmuxa),
 609         .datad(VCC),
 610         .aclr(GND),
 611         .sclr(G_16_i_i),
 612         .sload(un9_vsync_counterlt9_i),
 613         .ena(VCC),
 614         .cin(vsync_counter_cout[2]),
 615         .inverta(GND),
 616         .aload(GND),
 617         .regcascin(GND)
 618 );
 619 defparam vsync_counter_3_.cin_used="true";
 620 defparam vsync_counter_3_.operation_mode="arithmetic";
 621 defparam vsync_counter_3_.output_mode="reg_only";
 622 defparam vsync_counter_3_.lut_mask="5aa0";
 623 defparam vsync_counter_3_.synch_mode="on";
 624 defparam vsync_counter_3_.sum_lutc_input="cin";
 625 // @13:267
 626   stratix_lcell vsync_counter_4_ (
 627         .regout(vsync_counter_4),
 628         .cout(vsync_counter_cout[4]),
 629         .clk(clk_pin_c),
 630         .dataa(vsync_counter_4),
 631         .datab(VCC),
 632         .datac(vsync_counter_next_1_sqmuxa),
 633         .datad(VCC),
 634         .aclr(GND),
 635         .sclr(G_16_i_i),
 636         .sload(un9_vsync_counterlt9_i),
 637         .ena(VCC),
 638         .cin(vsync_counter_cout[3]),
 639         .inverta(GND),
 640         .aload(GND),
 641         .regcascin(GND)
 642 );
 643 defparam vsync_counter_4_.cin_used="true";
 644 defparam vsync_counter_4_.operation_mode="arithmetic";
 645 defparam vsync_counter_4_.output_mode="reg_only";
 646 defparam vsync_counter_4_.lut_mask="5aa0";
 647 defparam vsync_counter_4_.synch_mode="on";
 648 defparam vsync_counter_4_.sum_lutc_input="cin";
 649 // @13:267
 650   stratix_lcell vsync_counter_5_ (
 651         .regout(vsync_counter_5),
 652         .cout(vsync_counter_cout[5]),
 653         .clk(clk_pin_c),
 654         .dataa(vsync_counter_5),
 655         .datab(VCC),
 656         .datac(vsync_counter_next_1_sqmuxa),
 657         .datad(VCC),
 658         .aclr(GND),
 659         .sclr(G_16_i_i),
 660         .sload(un9_vsync_counterlt9_i),
 661         .ena(VCC),
 662         .cin(vsync_counter_cout[4]),
 663         .inverta(GND),
 664         .aload(GND),
 665         .regcascin(GND)
 666 );
 667 defparam vsync_counter_5_.cin_used="true";
 668 defparam vsync_counter_5_.operation_mode="arithmetic";
 669 defparam vsync_counter_5_.output_mode="reg_only";
 670 defparam vsync_counter_5_.lut_mask="5aa0";
 671 defparam vsync_counter_5_.synch_mode="on";
 672 defparam vsync_counter_5_.sum_lutc_input="cin";
 673 // @13:267
 674   stratix_lcell vsync_counter_6_ (
 675         .regout(vsync_counter_6),
 676         .cout(vsync_counter_cout[6]),
 677         .clk(clk_pin_c),
 678         .dataa(vsync_counter_6),
 679         .datab(VCC),
 680         .datac(vsync_counter_next_1_sqmuxa),
 681         .datad(VCC),
 682         .aclr(GND),
 683         .sclr(G_16_i_i),
 684         .sload(un9_vsync_counterlt9_i),
 685         .ena(VCC),
 686         .cin(vsync_counter_cout[5]),
 687         .inverta(GND),
 688         .aload(GND),
 689         .regcascin(GND)
 690 );
 691 defparam vsync_counter_6_.cin_used="true";
 692 defparam vsync_counter_6_.operation_mode="arithmetic";
 693 defparam vsync_counter_6_.output_mode="reg_only";
 694 defparam vsync_counter_6_.lut_mask="5aa0";
 695 defparam vsync_counter_6_.synch_mode="on";
 696 defparam vsync_counter_6_.sum_lutc_input="cin";
 697 // @13:267
 698   stratix_lcell vsync_counter_7_ (
 699         .regout(vsync_counter_7),
 700         .cout(vsync_counter_cout[7]),
 701         .clk(clk_pin_c),
 702         .dataa(vsync_counter_7),
 703         .datab(VCC),
 704         .datac(vsync_counter_next_1_sqmuxa),
 705         .datad(VCC),
 706         .aclr(GND),
 707         .sclr(G_16_i_i),
 708         .sload(un9_vsync_counterlt9_i),
 709         .ena(VCC),
 710         .cin(vsync_counter_cout[6]),
 711         .inverta(GND),
 712         .aload(GND),
 713         .regcascin(GND)
 714 );
 715 defparam vsync_counter_7_.cin_used="true";
 716 defparam vsync_counter_7_.operation_mode="arithmetic";
 717 defparam vsync_counter_7_.output_mode="reg_only";
 718 defparam vsync_counter_7_.lut_mask="5aa0";
 719 defparam vsync_counter_7_.synch_mode="on";
 720 defparam vsync_counter_7_.sum_lutc_input="cin";
 721 // @13:267
 722   stratix_lcell vsync_counter_8_ (
 723         .regout(vsync_counter_8),
 724         .cout(vsync_counter_cout[8]),
 725         .clk(clk_pin_c),
 726         .dataa(vsync_counter_8),
 727         .datab(VCC),
 728         .datac(vsync_counter_next_1_sqmuxa),
 729         .datad(VCC),
 730         .aclr(GND),
 731         .sclr(G_16_i_i),
 732         .sload(un9_vsync_counterlt9_i),
 733         .ena(VCC),
 734         .cin(vsync_counter_cout[7]),
 735         .inverta(GND),
 736         .aload(GND),
 737         .regcascin(GND)
 738 );
 739 defparam vsync_counter_8_.cin_used="true";
 740 defparam vsync_counter_8_.operation_mode="arithmetic";
 741 defparam vsync_counter_8_.output_mode="reg_only";
 742 defparam vsync_counter_8_.lut_mask="5aa0";
 743 defparam vsync_counter_8_.synch_mode="on";
 744 defparam vsync_counter_8_.sum_lutc_input="cin";
 745 // @13:267
 746   stratix_lcell vsync_counter_9_ (
 747         .regout(vsync_counter_9),
 748         .clk(clk_pin_c),
 749         .dataa(vsync_counter_9),
 750         .datab(VCC),
 751         .datac(vsync_counter_next_1_sqmuxa),
 752         .datad(VCC),
 753         .aclr(GND),
 754         .sclr(G_16_i_i),
 755         .sload(un9_vsync_counterlt9_i),
 756         .ena(VCC),
 757         .cin(vsync_counter_cout[8]),
 758         .inverta(GND),
 759         .aload(GND),
 760         .regcascin(GND)
 761 );
 762 defparam vsync_counter_9_.cin_used="true";
 763 defparam vsync_counter_9_.operation_mode="normal";
 764 defparam vsync_counter_9_.output_mode="reg_only";
 765 defparam vsync_counter_9_.lut_mask="5a5a";
 766 defparam vsync_counter_9_.synch_mode="on";
 767 defparam vsync_counter_9_.sum_lutc_input="cin";
 768 // @13:97
 769   stratix_lcell column_counter_sig_9_ (
 770         .regout(column_counter_sig_9),
 771         .clk(clk_pin_c),
 772         .dataa(un2_column_counter_next_combout[9]),
 773         .datab(un10_column_counter_siglto9),
 774         .datac(VCC),
 775         .datad(VCC),
 776         .aclr(GND),
 777         .sclr(column_counter_next_0_sqmuxa_1_1_i),
 778         .sload(GND),
 779         .ena(VCC),
 780         .inverta(GND),
 781         .aload(GND),
 782         .regcascin(GND)
 783 );
 784 defparam column_counter_sig_9_.operation_mode="normal";
 785 defparam column_counter_sig_9_.output_mode="reg_only";
 786 defparam column_counter_sig_9_.lut_mask="bbbb";
 787 defparam column_counter_sig_9_.synch_mode="on";
 788 defparam column_counter_sig_9_.sum_lutc_input="datac";
 789 // @13:97
 790   stratix_lcell column_counter_sig_8_ (
 791         .regout(column_counter_sig_8),
 792         .clk(clk_pin_c),
 793         .dataa(un2_column_counter_next_combout[8]),
 794         .datab(column_counter_next_0_sqmuxa_1_1),
 795         .datac(un10_column_counter_siglto9),
 796         .datad(VCC),
 797         .aclr(GND),
 798         .sclr(GND),
 799         .sload(GND),
 800         .ena(VCC),
 801         .inverta(GND),
 802         .aload(GND),
 803         .regcascin(GND)
 804 );
 805 defparam column_counter_sig_8_.operation_mode="normal";
 806 defparam column_counter_sig_8_.output_mode="reg_only";
 807 defparam column_counter_sig_8_.lut_mask="8080";
 808 defparam column_counter_sig_8_.synch_mode="off";
 809 defparam column_counter_sig_8_.sum_lutc_input="datac";
 810 // @13:97
 811   stratix_lcell column_counter_sig_7_ (
 812         .regout(column_counter_sig_7),
 813         .clk(clk_pin_c),
 814         .dataa(un2_column_counter_next_combout[7]),
 815         .datab(column_counter_next_0_sqmuxa_1_1),
 816         .datac(un10_column_counter_siglto9),
 817         .datad(VCC),
 818         .aclr(GND),
 819         .sclr(GND),
 820         .sload(GND),
 821         .ena(VCC),
 822         .inverta(GND),
 823         .aload(GND),
 824         .regcascin(GND)
 825 );
 826 defparam column_counter_sig_7_.operation_mode="normal";
 827 defparam column_counter_sig_7_.output_mode="reg_only";
 828 defparam column_counter_sig_7_.lut_mask="8080";
 829 defparam column_counter_sig_7_.synch_mode="off";
 830 defparam column_counter_sig_7_.sum_lutc_input="datac";
 831 // @13:97
 832   stratix_lcell column_counter_sig_6_ (
 833         .regout(column_counter_sig_6),
 834         .clk(clk_pin_c),
 835         .dataa(un2_column_counter_next_combout[6]),
 836         .datab(un10_column_counter_siglto9),
 837         .datac(VCC),
 838         .datad(VCC),
 839         .aclr(GND),
 840         .sclr(column_counter_next_0_sqmuxa_1_1_i),
 841         .sload(GND),
 842         .ena(VCC),
 843         .inverta(GND),
 844         .aload(GND),
 845         .regcascin(GND)
 846 );
 847 defparam column_counter_sig_6_.operation_mode="normal";
 848 defparam column_counter_sig_6_.output_mode="reg_only";
 849 defparam column_counter_sig_6_.lut_mask="bbbb";
 850 defparam column_counter_sig_6_.synch_mode="on";
 851 defparam column_counter_sig_6_.sum_lutc_input="datac";
 852 // @13:97
 853   stratix_lcell column_counter_sig_5_ (
 854         .regout(column_counter_sig_5),
 855         .clk(clk_pin_c),
 856         .dataa(un2_column_counter_next_combout[5]),
 857         .datab(un10_column_counter_siglto9),
 858         .datac(VCC),
 859         .datad(VCC),
 860         .aclr(GND),
 861         .sclr(column_counter_next_0_sqmuxa_1_1_i),
 862         .sload(GND),
 863         .ena(VCC),
 864         .inverta(GND),
 865         .aload(GND),
 866         .regcascin(GND)
 867 );
 868 defparam column_counter_sig_5_.operation_mode="normal";
 869 defparam column_counter_sig_5_.output_mode="reg_only";
 870 defparam column_counter_sig_5_.lut_mask="bbbb";
 871 defparam column_counter_sig_5_.synch_mode="on";
 872 defparam column_counter_sig_5_.sum_lutc_input="datac";
 873 // @13:97
 874   stratix_lcell column_counter_sig_4_ (
 875         .regout(column_counter_sig_4),
 876         .clk(clk_pin_c),
 877         .dataa(un2_column_counter_next_combout[4]),
 878         .datab(un10_column_counter_siglto9),
 879         .datac(VCC),
 880         .datad(VCC),
 881         .aclr(GND),
 882         .sclr(column_counter_next_0_sqmuxa_1_1_i),
 883         .sload(GND),
 884         .ena(VCC),
 885         .inverta(GND),
 886         .aload(GND),
 887         .regcascin(GND)
 888 );
 889 defparam column_counter_sig_4_.operation_mode="normal";
 890 defparam column_counter_sig_4_.output_mode="reg_only";
 891 defparam column_counter_sig_4_.lut_mask="bbbb";
 892 defparam column_counter_sig_4_.synch_mode="on";
 893 defparam column_counter_sig_4_.sum_lutc_input="datac";
 894 // @13:97
 895   stratix_lcell column_counter_sig_3_ (
 896         .regout(column_counter_sig_3),
 897         .clk(clk_pin_c),
 898         .dataa(un2_column_counter_next_combout[3]),
 899         .datab(un10_column_counter_siglto9),
 900         .datac(VCC),
 901         .datad(VCC),
 902         .aclr(GND),
 903         .sclr(column_counter_next_0_sqmuxa_1_1_i),
 904         .sload(GND),
 905         .ena(VCC),
 906         .inverta(GND),
 907         .aload(GND),
 908         .regcascin(GND)
 909 );
 910 defparam column_counter_sig_3_.operation_mode="normal";
 911 defparam column_counter_sig_3_.output_mode="reg_only";
 912 defparam column_counter_sig_3_.lut_mask="bbbb";
 913 defparam column_counter_sig_3_.synch_mode="on";
 914 defparam column_counter_sig_3_.sum_lutc_input="datac";
 915 // @13:97
 916   stratix_lcell column_counter_sig_2_ (
 917         .regout(column_counter_sig_2),
 918         .clk(clk_pin_c),
 919         .dataa(un2_column_counter_next_combout[2]),
 920         .datab(un10_column_counter_siglto9),
 921         .datac(VCC),
 922         .datad(VCC),
 923         .aclr(GND),
 924         .sclr(column_counter_next_0_sqmuxa_1_1_i),
 925         .sload(GND),
 926         .ena(VCC),
 927         .inverta(GND),
 928         .aload(GND),
 929         .regcascin(GND)
 930 );
 931 defparam column_counter_sig_2_.operation_mode="normal";
 932 defparam column_counter_sig_2_.output_mode="reg_only";
 933 defparam column_counter_sig_2_.lut_mask="bbbb";
 934 defparam column_counter_sig_2_.synch_mode="on";
 935 defparam column_counter_sig_2_.sum_lutc_input="datac";
 936 // @13:97
 937   stratix_lcell column_counter_sig_1_ (
 938         .regout(column_counter_sig_1),
 939         .clk(clk_pin_c),
 940         .dataa(un2_column_counter_next_combout[1]),
 941         .datab(un10_column_counter_siglto9),
 942         .datac(VCC),
 943         .datad(VCC),
 944         .aclr(GND),
 945         .sclr(column_counter_next_0_sqmuxa_1_1_i),
 946         .sload(GND),
 947         .ena(VCC),
 948         .inverta(GND),
 949         .aload(GND),
 950         .regcascin(GND)
 951 );
 952 defparam column_counter_sig_1_.operation_mode="normal";
 953 defparam column_counter_sig_1_.output_mode="reg_only";
 954 defparam column_counter_sig_1_.lut_mask="bbbb";
 955 defparam column_counter_sig_1_.synch_mode="on";
 956 defparam column_counter_sig_1_.sum_lutc_input="datac";
 957 // @13:97
 958   stratix_lcell column_counter_sig_0_ (
 959         .regout(column_counter_sig_0),
 960         .clk(clk_pin_c),
 961         .dataa(column_counter_sig_0),
 962         .datab(un10_column_counter_siglto9),
 963         .datac(VCC),
 964         .datad(VCC),
 965         .aclr(GND),
 966         .sclr(column_counter_next_0_sqmuxa_1_1_i),
 967         .sload(GND),
 968         .ena(VCC),
 969         .inverta(GND),
 970         .aload(GND),
 971         .regcascin(GND)
 972 );
 973 defparam column_counter_sig_0_.operation_mode="normal";
 974 defparam column_counter_sig_0_.output_mode="reg_only";
 975 defparam column_counter_sig_0_.lut_mask="7777";
 976 defparam column_counter_sig_0_.synch_mode="on";
 977 defparam column_counter_sig_0_.sum_lutc_input="datac";
 978 // @13:187
 979   stratix_lcell hsync_state_6_ (
 980         .regout(hsync_state_6),
 981         .clk(clk_pin_c),
 982         .dataa(VCC),
 983         .datab(VCC),
 984         .datac(VCC),
 985         .datad(un6_dly_counter_0_x),
 986         .aclr(GND),
 987         .sclr(GND),
 988         .sload(GND),
 989         .ena(VCC),
 990         .inverta(GND),
 991         .aload(GND),
 992         .regcascin(GND)
 993 );
 994 defparam hsync_state_6_.operation_mode="normal";
 995 defparam hsync_state_6_.output_mode="reg_only";
 996 defparam hsync_state_6_.lut_mask="ff00";
 997 defparam hsync_state_6_.synch_mode="off";
 998 defparam hsync_state_6_.sum_lutc_input="datac";
 999 // @13:300
1000   stratix_lcell vsync_state_0_ (
1001         .regout(vsync_state_0),
1002         .clk(clk_pin_c),
1003         .dataa(vsync_state_0),
1004         .datab(un6_dly_counter_0_x),
1005         .datac(vsync_state_3_iv_0_0__g0_0_a3_0),
1006         .datad(vsync_state_next_2_sqmuxa),
1007         .aclr(GND),
1008         .sclr(GND),
1009         .sload(GND),
1010         .ena(VCC),
1011         .inverta(GND),
1012         .aload(GND),
1013         .regcascin(GND)
1014 );
1015 defparam vsync_state_0_.operation_mode="normal";
1016 defparam vsync_state_0_.output_mode="reg_only";
1017 defparam vsync_state_0_.lut_mask="30ba";
1018 defparam vsync_state_0_.synch_mode="off";
1019 defparam vsync_state_0_.sum_lutc_input="datac";
1020 // @13:300
1021   stratix_lcell vsync_state_1_ (
1022         .regout(vsync_state_1),
1023         .clk(clk_pin_c),
1024         .dataa(vsync_state_4),
1025         .datab(un12_vsync_counter_7),
1026         .datac(un13_vsync_counter_4),
1027         .datad(un6_dly_counter_0_x),
1028         .aclr(GND),
1029         .sclr(GND),
1030         .sload(GND),
1031         .ena(VCC),
1032         .inverta(GND),
1033         .aload(GND),
1034         .regcascin(GND)
1035 );
1036 defparam vsync_state_1_.operation_mode="normal";
1037 defparam vsync_state_1_.output_mode="reg_only";
1038 defparam vsync_state_1_.lut_mask="0080";
1039 defparam vsync_state_1_.synch_mode="off";
1040 defparam vsync_state_1_.sum_lutc_input="datac";
1041 // @13:300
1042   stratix_lcell vsync_state_6_ (
1043         .combout(un6_dly_counter_0_x),
1044         .regout(vsync_state_6),
1045         .clk(clk_pin_c),
1046         .dataa(reset_pin_c),
1047         .datab(dly_counter_0),
1048         .datac(dly_counter_1),
1049         .datad(VCC),
1050         .aclr(GND),
1051         .sclr(GND),
1052         .sload(GND),
1053         .ena(VCC),
1054         .inverta(GND),
1055         .aload(GND),
1056         .regcascin(GND)
1057 );
1058 defparam vsync_state_6_.operation_mode="normal";
1059 defparam vsync_state_6_.output_mode="reg_and_comb";
1060 defparam vsync_state_6_.lut_mask="7f7f";
1061 defparam vsync_state_6_.synch_mode="off";
1062 defparam vsync_state_6_.sum_lutc_input="datac";
1063 // @13:125
1064   stratix_lcell line_counter_sig_8_ (
1065         .regout(line_counter_sig_8),
1066         .clk(clk_pin_c),
1067         .dataa(un10_line_counter_siglto8),
1068         .datab(un1_line_counter_sig_combout[9]),
1069         .datac(VCC),
1070         .datad(VCC),
1071         .aclr(GND),
1072         .sclr(line_counter_next_0_sqmuxa_1_1_i),
1073         .sload(GND),
1074         .ena(VCC),
1075         .inverta(GND),
1076         .aload(GND),
1077         .regcascin(GND)
1078 );
1079 defparam line_counter_sig_8_.operation_mode="normal";
1080 defparam line_counter_sig_8_.output_mode="reg_only";
1081 defparam line_counter_sig_8_.lut_mask="dddd";
1082 defparam line_counter_sig_8_.synch_mode="on";
1083 defparam line_counter_sig_8_.sum_lutc_input="datac";
1084 // @13:125
1085   stratix_lcell line_counter_sig_7_ (
1086         .regout(line_counter_sig_7),
1087         .clk(clk_pin_c),
1088         .dataa(un10_line_counter_siglto8),
1089         .datab(un1_line_counter_sig_combout[8]),
1090         .datac(VCC),
1091         .datad(VCC),
1092         .aclr(GND),
1093         .sclr(line_counter_next_0_sqmuxa_1_1_i),
1094         .sload(GND),
1095         .ena(VCC),
1096         .inverta(GND),
1097         .aload(GND),
1098         .regcascin(GND)
1099 );
1100 defparam line_counter_sig_7_.operation_mode="normal";
1101 defparam line_counter_sig_7_.output_mode="reg_only";
1102 defparam line_counter_sig_7_.lut_mask="dddd";
1103 defparam line_counter_sig_7_.synch_mode="on";
1104 defparam line_counter_sig_7_.sum_lutc_input="datac";
1105 // @13:125
1106   stratix_lcell line_counter_sig_6_ (
1107         .regout(line_counter_sig_6),
1108         .clk(clk_pin_c),
1109         .dataa(un10_line_counter_siglto8),
1110         .datab(un1_line_counter_sig_combout[7]),
1111         .datac(VCC),
1112         .datad(VCC),
1113         .aclr(GND),
1114         .sclr(line_counter_next_0_sqmuxa_1_1_i),
1115         .sload(GND),
1116         .ena(VCC),
1117         .inverta(GND),
1118         .aload(GND),
1119         .regcascin(GND)
1120 );
1121 defparam line_counter_sig_6_.operation_mode="normal";
1122 defparam line_counter_sig_6_.output_mode="reg_only";
1123 defparam line_counter_sig_6_.lut_mask="dddd";
1124 defparam line_counter_sig_6_.synch_mode="on";
1125 defparam line_counter_sig_6_.sum_lutc_input="datac";
1126 // @13:125
1127   stratix_lcell line_counter_sig_5_ (
1128         .regout(line_counter_sig_5),
1129         .clk(clk_pin_c),
1130         .dataa(un10_line_counter_siglto8),
1131         .datab(line_counter_next_0_sqmuxa_1_1),
1132         .datac(un1_line_counter_sig_combout[6]),
1133         .datad(VCC),
1134         .aclr(GND),
1135         .sclr(GND),
1136         .sload(GND),
1137         .ena(VCC),
1138         .inverta(GND),
1139         .aload(GND),
1140         .regcascin(GND)
1141 );
1142 defparam line_counter_sig_5_.operation_mode="normal";
1143 defparam line_counter_sig_5_.output_mode="reg_only";
1144 defparam line_counter_sig_5_.lut_mask="8080";
1145 defparam line_counter_sig_5_.synch_mode="off";
1146 defparam line_counter_sig_5_.sum_lutc_input="datac";
1147 // @13:125
1148   stratix_lcell line_counter_sig_4_ (
1149         .regout(line_counter_sig_4),
1150         .clk(clk_pin_c),
1151         .dataa(un10_line_counter_siglto8),
1152         .datab(un1_line_counter_sig_combout[5]),
1153         .datac(VCC),
1154         .datad(VCC),
1155         .aclr(GND),
1156         .sclr(line_counter_next_0_sqmuxa_1_1_i),
1157         .sload(GND),
1158         .ena(VCC),
1159         .inverta(GND),
1160         .aload(GND),
1161         .regcascin(GND)
1162 );
1163 defparam line_counter_sig_4_.operation_mode="normal";
1164 defparam line_counter_sig_4_.output_mode="reg_only";
1165 defparam line_counter_sig_4_.lut_mask="dddd";
1166 defparam line_counter_sig_4_.synch_mode="on";
1167 defparam line_counter_sig_4_.sum_lutc_input="datac";
1168 // @13:125
1169   stratix_lcell line_counter_sig_3_ (
1170         .regout(line_counter_sig_3),
1171         .clk(clk_pin_c),
1172         .dataa(un10_line_counter_siglto8),
1173         .datab(un1_line_counter_sig_combout[4]),
1174         .datac(VCC),
1175         .datad(VCC),
1176         .aclr(GND),
1177         .sclr(line_counter_next_0_sqmuxa_1_1_i),
1178         .sload(GND),
1179         .ena(VCC),
1180         .inverta(GND),
1181         .aload(GND),
1182         .regcascin(GND)
1183 );
1184 defparam line_counter_sig_3_.operation_mode="normal";
1185 defparam line_counter_sig_3_.output_mode="reg_only";
1186 defparam line_counter_sig_3_.lut_mask="dddd";
1187 defparam line_counter_sig_3_.synch_mode="on";
1188 defparam line_counter_sig_3_.sum_lutc_input="datac";
1189 // @13:125
1190   stratix_lcell line_counter_sig_2_ (
1191         .regout(line_counter_sig_2),
1192         .clk(clk_pin_c),
1193         .dataa(un10_line_counter_siglto8),
1194         .datab(un1_line_counter_sig_combout[3]),
1195         .datac(VCC),
1196         .datad(VCC),
1197         .aclr(GND),
1198         .sclr(line_counter_next_0_sqmuxa_1_1_i),
1199         .sload(GND),
1200         .ena(VCC),
1201         .inverta(GND),
1202         .aload(GND),
1203         .regcascin(GND)
1204 );
1205 defparam line_counter_sig_2_.operation_mode="normal";
1206 defparam line_counter_sig_2_.output_mode="reg_only";
1207 defparam line_counter_sig_2_.lut_mask="dddd";
1208 defparam line_counter_sig_2_.synch_mode="on";
1209 defparam line_counter_sig_2_.sum_lutc_input="datac";
1210 // @13:125
1211   stratix_lcell line_counter_sig_1_ (
1212         .regout(line_counter_sig_1),
1213         .clk(clk_pin_c),
1214         .dataa(un10_line_counter_siglto8),
1215         .datab(un1_line_counter_sig_combout[2]),
1216         .datac(VCC),
1217         .datad(VCC),
1218         .aclr(GND),
1219         .sclr(line_counter_next_0_sqmuxa_1_1_i),
1220         .sload(GND),
1221         .ena(VCC),
1222         .inverta(GND),
1223         .aload(GND),
1224         .regcascin(GND)
1225 );
1226 defparam line_counter_sig_1_.operation_mode="normal";
1227 defparam line_counter_sig_1_.output_mode="reg_only";
1228 defparam line_counter_sig_1_.lut_mask="dddd";
1229 defparam line_counter_sig_1_.synch_mode="on";
1230 defparam line_counter_sig_1_.sum_lutc_input="datac";
1231 // @13:125
1232   stratix_lcell line_counter_sig_0_ (
1233         .regout(line_counter_sig_0),
1234         .clk(clk_pin_c),
1235         .dataa(un1_line_counter_sig_combout[1]),
1236         .datab(un10_line_counter_siglto8),
1237         .datac(VCC),
1238         .datad(VCC),
1239         .aclr(GND),
1240         .sclr(line_counter_next_0_sqmuxa_1_1_i),
1241         .sload(GND),
1242         .ena(VCC),
1243         .inverta(GND),
1244         .aload(GND),
1245         .regcascin(GND)
1246 );
1247 defparam line_counter_sig_0_.operation_mode="normal";
1248 defparam line_counter_sig_0_.output_mode="reg_only";
1249 defparam line_counter_sig_0_.lut_mask="bbbb";
1250 defparam line_counter_sig_0_.synch_mode="on";
1251 defparam line_counter_sig_0_.sum_lutc_input="datac";
1252 // @13:187
1253   stratix_lcell v_enable_sig_Z (
1254         .regout(v_enable_sig),
1255         .clk(clk_pin_c),
1256         .dataa(hsync_state_3),
1257         .datab(hsync_state_1),
1258         .datac(VCC),
1259         .datad(VCC),
1260         .aclr(GND),
1261         .sclr(un6_dly_counter_0_x),
1262         .sload(GND),
1263         .ena(v_enable_sig_1_0_0_0_g0_i_o4),
1264         .inverta(GND),
1265         .aload(GND),
1266         .regcascin(GND)
1267 );
1268 defparam v_enable_sig_Z.operation_mode="normal";
1269 defparam v_enable_sig_Z.output_mode="reg_only";
1270 defparam v_enable_sig_Z.lut_mask="eeee";
1271 defparam v_enable_sig_Z.synch_mode="on";
1272 defparam v_enable_sig_Z.sum_lutc_input="datac";
1273 // @13:300
1274   stratix_lcell h_enable_sig_Z (
1275         .regout(h_enable_sig),
1276         .clk(clk_pin_c),
1277         .dataa(vsync_state_3),
1278         .datab(vsync_state_1),
1279         .datac(VCC),
1280         .datad(VCC),
1281         .aclr(GND),
1282         .sclr(un6_dly_counter_0_x),
1283         .sload(GND),
1284         .ena(h_enable_sig_1_0_0_0_g0_i_o4),
1285         .inverta(GND),
1286         .aload(GND),
1287         .regcascin(GND)
1288 );
1289 defparam h_enable_sig_Z.operation_mode="normal";
1290 defparam h_enable_sig_Z.output_mode="reg_only";
1291 defparam h_enable_sig_Z.lut_mask="eeee";
1292 defparam h_enable_sig_Z.synch_mode="on";
1293 defparam h_enable_sig_Z.sum_lutc_input="datac";
1294 // @13:187
1295   stratix_lcell h_sync_Z (
1296         .regout(h_sync),
1297         .clk(clk_pin_c),
1298         .dataa(reset_pin_c),
1299         .datab(dly_counter_0),
1300         .datac(dly_counter_1),
1301         .datad(h_sync_1_0_0_0_g1),
1302         .aclr(GND),
1303         .sclr(GND),
1304         .sload(GND),
1305         .ena(VCC),
1306         .inverta(GND),
1307         .aload(GND),
1308         .regcascin(GND)
1309 );
1310 defparam h_sync_Z.operation_mode="normal";
1311 defparam h_sync_Z.output_mode="reg_only";
1312 defparam h_sync_Z.lut_mask="ff7f";
1313 defparam h_sync_Z.synch_mode="off";
1314 defparam h_sync_Z.sum_lutc_input="datac";
1315 // @13:300
1316   stratix_lcell v_sync_Z (
1317         .regout(v_sync),
1318         .clk(clk_pin_c),
1319         .dataa(reset_pin_c),
1320         .datab(dly_counter_0),
1321         .datac(dly_counter_1),
1322         .datad(v_sync_1_0_0_0_g1),
1323         .aclr(GND),
1324         .sclr(GND),
1325         .sload(GND),
1326         .ena(VCC),
1327         .inverta(GND),
1328         .aload(GND),
1329         .regcascin(GND)
1330 );
1331 defparam v_sync_Z.operation_mode="normal";
1332 defparam v_sync_Z.output_mode="reg_only";
1333 defparam v_sync_Z.lut_mask="ff7f";
1334 defparam v_sync_Z.synch_mode="off";
1335 defparam v_sync_Z.sum_lutc_input="datac";
1336 // @13:300
1337   stratix_lcell vsync_state_5_ (
1338         .regout(vsync_state_5),
1339         .clk(clk_pin_c),
1340         .dataa(vsync_state_6),
1341         .datab(vsync_state_0),
1342         .datac(VCC),
1343         .datad(VCC),
1344         .aclr(GND),
1345         .sclr(un6_dly_counter_0_x),
1346         .sload(GND),
1347         .ena(vsync_state_next_2_sqmuxa),
1348         .inverta(GND),
1349         .aload(GND),
1350         .regcascin(GND)
1351 );
1352 defparam vsync_state_5_.operation_mode="normal";
1353 defparam vsync_state_5_.output_mode="reg_only";
1354 defparam vsync_state_5_.lut_mask="eeee";
1355 defparam vsync_state_5_.synch_mode="on";
1356 defparam vsync_state_5_.sum_lutc_input="datac";
1357 // @13:300
1358   stratix_lcell vsync_state_4_ (
1359         .regout(vsync_state_4),
1360         .clk(clk_pin_c),
1361         .dataa(vsync_counter_0),
1362         .datab(vsync_counter_9),
1363         .datac(vsync_state_5),
1364         .datad(un14_vsync_counter_8),
1365         .aclr(GND),
1366         .sclr(un6_dly_counter_0_x),
1367         .sload(GND),
1368         .ena(vsync_state_next_2_sqmuxa),
1369         .inverta(GND),
1370         .aload(GND),
1371         .regcascin(GND)
1372 );
1373 defparam vsync_state_4_.operation_mode="normal";
1374 defparam vsync_state_4_.output_mode="reg_only";
1375 defparam vsync_state_4_.lut_mask="2000";
1376 defparam vsync_state_4_.synch_mode="on";
1377 defparam vsync_state_4_.sum_lutc_input="datac";
1378 // @13:300
1379   stratix_lcell vsync_state_3_ (
1380         .regout(vsync_state_3),
1381         .clk(clk_pin_c),
1382         .dataa(vsync_state_1),
1383         .datab(VCC),
1384         .datac(VCC),
1385         .datad(VCC),
1386         .aclr(GND),
1387         .sclr(un6_dly_counter_0_x),
1388         .sload(GND),
1389         .ena(vsync_state_next_2_sqmuxa),
1390         .inverta(GND),
1391         .aload(GND),
1392         .regcascin(GND)
1393 );
1394 defparam vsync_state_3_.operation_mode="normal";
1395 defparam vsync_state_3_.output_mode="reg_only";
1396 defparam vsync_state_3_.lut_mask="aaaa";
1397 defparam vsync_state_3_.synch_mode="on";
1398 defparam vsync_state_3_.sum_lutc_input="datac";
1399 // @13:300
1400   stratix_lcell vsync_state_2_ (
1401         .regout(vsync_state_2),
1402         .clk(clk_pin_c),
1403         .dataa(vsync_counter_0),
1404         .datab(vsync_counter_9),
1405         .datac(vsync_state_3),
1406         .datad(un14_vsync_counter_8),
1407         .aclr(GND),
1408         .sclr(un6_dly_counter_0_x),
1409         .sload(GND),
1410         .ena(vsync_state_next_2_sqmuxa),
1411         .inverta(GND),
1412         .aload(GND),
1413         .regcascin(GND)
1414 );
1415 defparam vsync_state_2_.operation_mode="normal";
1416 defparam vsync_state_2_.output_mode="reg_only";
1417 defparam vsync_state_2_.lut_mask="8000";
1418 defparam vsync_state_2_.synch_mode="on";
1419 defparam vsync_state_2_.sum_lutc_input="datac";
1420 // @13:187
1421   stratix_lcell hsync_state_5_ (
1422         .regout(hsync_state_5),
1423         .clk(clk_pin_c),
1424         .dataa(hsync_state_6),
1425         .datab(hsync_state_0),
1426         .datac(VCC),
1427         .datad(VCC),
1428         .aclr(GND),
1429         .sclr(un6_dly_counter_0_x),
1430         .sload(GND),
1431         .ena(hsync_state_3_0_0_0__g0_0),
1432         .inverta(GND),
1433         .aload(GND),
1434         .regcascin(GND)
1435 );
1436 defparam hsync_state_5_.operation_mode="normal";
1437 defparam hsync_state_5_.output_mode="reg_only";
1438 defparam hsync_state_5_.lut_mask="eeee";
1439 defparam hsync_state_5_.synch_mode="on";
1440 defparam hsync_state_5_.sum_lutc_input="datac";
1441 // @13:187
1442   stratix_lcell hsync_state_4_ (
1443         .regout(hsync_state_4),
1444         .clk(clk_pin_c),
1445         .dataa(hsync_state_5),
1446         .datab(un10_hsync_counter_3),
1447         .datac(un10_hsync_counter_1),
1448         .datad(un10_hsync_counter_4),
1449         .aclr(GND),
1450         .sclr(un6_dly_counter_0_x),
1451         .sload(GND),
1452         .ena(hsync_state_3_0_0_0__g0_0),
1453         .inverta(GND),
1454         .aload(GND),
1455         .regcascin(GND)
1456 );
1457 defparam hsync_state_4_.operation_mode="normal";
1458 defparam hsync_state_4_.output_mode="reg_only";
1459 defparam hsync_state_4_.lut_mask="8000";
1460 defparam hsync_state_4_.synch_mode="on";
1461 defparam hsync_state_4_.sum_lutc_input="datac";
1462 // @13:187
1463   stratix_lcell hsync_state_3_ (
1464         .regout(hsync_state_3),
1465         .clk(clk_pin_c),
1466         .dataa(hsync_state_1),
1467         .datab(VCC),
1468         .datac(VCC),
1469         .datad(VCC),
1470         .aclr(GND),
1471         .sclr(un6_dly_counter_0_x),
1472         .sload(GND),
1473         .ena(hsync_state_3_0_0_0__g0_0),
1474         .inverta(GND),
1475         .aload(GND),
1476         .regcascin(GND)
1477 );
1478 defparam hsync_state_3_.operation_mode="normal";
1479 defparam hsync_state_3_.output_mode="reg_only";
1480 defparam hsync_state_3_.lut_mask="aaaa";
1481 defparam hsync_state_3_.synch_mode="on";
1482 defparam hsync_state_3_.sum_lutc_input="datac";
1483 // @13:187
1484   stratix_lcell hsync_state_2_ (
1485         .regout(hsync_state_2),
1486         .clk(clk_pin_c),
1487         .dataa(hsync_state_3),
1488         .datab(un12_hsync_counter),
1489         .datac(VCC),
1490         .datad(VCC),
1491         .aclr(GND),
1492         .sclr(un6_dly_counter_0_x),
1493         .sload(GND),
1494         .ena(hsync_state_3_0_0_0__g0_0),
1495         .inverta(GND),
1496         .aload(GND),
1497         .regcascin(GND)
1498 );
1499 defparam hsync_state_2_.operation_mode="normal";
1500 defparam hsync_state_2_.output_mode="reg_only";
1501 defparam hsync_state_2_.lut_mask="8888";
1502 defparam hsync_state_2_.synch_mode="on";
1503 defparam hsync_state_2_.sum_lutc_input="datac";
1504 // @13:187
1505   stratix_lcell hsync_state_1_ (
1506         .regout(hsync_state_1),
1507         .clk(clk_pin_c),
1508         .dataa(hsync_state_4),
1509         .datab(un11_hsync_counter_2),
1510         .datac(un10_hsync_counter_1),
1511         .datad(un11_hsync_counter_3),
1512         .aclr(GND),
1513         .sclr(un6_dly_counter_0_x),
1514         .sload(GND),
1515         .ena(hsync_state_3_0_0_0__g0_0),
1516         .inverta(GND),
1517         .aload(GND),
1518         .regcascin(GND)
1519 );
1520 defparam hsync_state_1_.operation_mode="normal";
1521 defparam hsync_state_1_.output_mode="reg_only";
1522 defparam hsync_state_1_.lut_mask="8000";
1523 defparam hsync_state_1_.synch_mode="on";
1524 defparam hsync_state_1_.sum_lutc_input="datac";
1525 // @13:187
1526   stratix_lcell hsync_state_0_ (
1527         .regout(hsync_state_0),
1528         .clk(clk_pin_c),
1529         .dataa(hsync_state_2),
1530         .datab(un13_hsync_counter),
1531         .datac(VCC),
1532         .datad(VCC),
1533         .aclr(GND),
1534         .sclr(un6_dly_counter_0_x),
1535         .sload(GND),
1536         .ena(hsync_state_3_0_0_0__g0_0),
1537         .inverta(GND),
1538         .aload(GND),
1539         .regcascin(GND)
1540 );
1541 defparam hsync_state_0_.operation_mode="normal";
1542 defparam hsync_state_0_.output_mode="reg_only";
1543 defparam hsync_state_0_.lut_mask="8888";
1544 defparam hsync_state_0_.synch_mode="on";
1545 defparam hsync_state_0_.sum_lutc_input="datac";
1546 // @13:97
1547   stratix_lcell vsync_state_next_2_sqmuxa_cZ (
1548         .combout(vsync_state_next_2_sqmuxa),
1549         .clk(GND),
1550         .dataa(un6_dly_counter_0_x),
1551         .datab(vsync_state_next_1_sqmuxa_1),
1552         .datac(vsync_state_next_1_sqmuxa_3),
1553         .datad(un1_vsync_state_next_1_sqmuxa_0),
1554         .aclr(GND),
1555         .sclr(GND),
1556         .sload(GND),
1557         .ena(VCC),
1558         .inverta(GND),
1559         .aload(GND),
1560         .regcascin(GND)
1561 );
1562 defparam vsync_state_next_2_sqmuxa_cZ.operation_mode="normal";
1563 defparam vsync_state_next_2_sqmuxa_cZ.output_mode="comb_only";
1564 defparam vsync_state_next_2_sqmuxa_cZ.lut_mask="aaab";
1565 defparam vsync_state_next_2_sqmuxa_cZ.synch_mode="off";
1566 defparam vsync_state_next_2_sqmuxa_cZ.sum_lutc_input="datac";
1567   stratix_lcell hsync_state_3_0_0_0__g0_0_cZ (
1568         .combout(hsync_state_3_0_0_0__g0_0),
1569         .clk(GND),
1570         .dataa(hsync_state_next_1_sqmuxa_1),
1571         .datab(hsync_state_next_1_sqmuxa_2),
1572         .datac(un6_dly_counter_0_x),
1573         .datad(un1_hsync_state_next_1_sqmuxa_0),
1574         .aclr(GND),
1575         .sclr(GND),
1576         .sload(GND),
1577         .ena(VCC),
1578         .inverta(GND),
1579         .aload(GND),
1580         .regcascin(GND)
1581 );
1582 defparam hsync_state_3_0_0_0__g0_0_cZ.operation_mode="normal";
1583 defparam hsync_state_3_0_0_0__g0_0_cZ.output_mode="comb_only";
1584 defparam hsync_state_3_0_0_0__g0_0_cZ.lut_mask="f0f1";
1585 defparam hsync_state_3_0_0_0__g0_0_cZ.synch_mode="off";
1586 defparam hsync_state_3_0_0_0__g0_0_cZ.sum_lutc_input="datac";
1587 // @13:206
1588   stratix_lcell un1_hsync_state_next_1_sqmuxa_0_cZ (
1589         .combout(un1_hsync_state_next_1_sqmuxa_0),
1590         .clk(GND),
1591         .dataa(hsync_state_2),
1592         .datab(hsync_state_3),
1593         .datac(un13_hsync_counter),
1594         .datad(un12_hsync_counter),
1595         .aclr(GND),
1596         .sclr(GND),
1597         .sload(GND),
1598         .ena(VCC),
1599         .inverta(GND),
1600         .aload(GND),
1601         .regcascin(GND)
1602 );
1603 defparam un1_hsync_state_next_1_sqmuxa_0_cZ.operation_mode="normal";
1604 defparam un1_hsync_state_next_1_sqmuxa_0_cZ.output_mode="comb_only";
1605 defparam un1_hsync_state_next_1_sqmuxa_0_cZ.lut_mask="0ace";
1606 defparam un1_hsync_state_next_1_sqmuxa_0_cZ.synch_mode="off";
1607 defparam un1_hsync_state_next_1_sqmuxa_0_cZ.sum_lutc_input="datac";
1608 // @13:319
1609   stratix_lcell un1_vsync_state_next_1_sqmuxa_0_cZ (
1610         .combout(un1_vsync_state_next_1_sqmuxa_0),
1611         .clk(GND),
1612         .dataa(vsync_state_2),
1613         .datab(un12_vsync_counter_6),
1614         .datac(un15_vsync_counter_4),
1615         .datad(vsync_state_next_1_sqmuxa_2),
1616         .aclr(GND),
1617         .sclr(GND),
1618         .sload(GND),
1619         .ena(VCC),
1620         .inverta(GND),
1621         .aload(GND),
1622         .regcascin(GND)
1623 );
1624 defparam un1_vsync_state_next_1_sqmuxa_0_cZ.operation_mode="normal";
1625 defparam un1_vsync_state_next_1_sqmuxa_0_cZ.output_mode="comb_only";
1626 defparam un1_vsync_state_next_1_sqmuxa_0_cZ.lut_mask="ff2a";
1627 defparam un1_vsync_state_next_1_sqmuxa_0_cZ.synch_mode="off";
1628 defparam un1_vsync_state_next_1_sqmuxa_0_cZ.sum_lutc_input="datac";
1629 // @13:111
1630   stratix_lcell COLUMN_COUNT_next_un10_column_counter_siglto9 (
1631         .combout(un10_column_counter_siglto9),
1632         .clk(GND),
1633         .dataa(column_counter_sig_7),
1634         .datab(column_counter_sig_8),
1635         .datac(column_counter_sig_9),
1636         .datad(un10_column_counter_siglt6),
1637         .aclr(GND),
1638         .sclr(GND),
1639         .sload(GND),
1640         .ena(VCC),
1641         .inverta(GND),
1642         .aload(GND),
1643         .regcascin(GND)
1644 );
1645 defparam COLUMN_COUNT_next_un10_column_counter_siglto9.operation_mode="normal";
1646 defparam COLUMN_COUNT_next_un10_column_counter_siglto9.output_mode="comb_only";
1647 defparam COLUMN_COUNT_next_un10_column_counter_siglto9.lut_mask="1f0f";
1648 defparam COLUMN_COUNT_next_un10_column_counter_siglto9.synch_mode="off";
1649 defparam COLUMN_COUNT_next_un10_column_counter_siglto9.sum_lutc_input="datac";
1650   stratix_lcell vsync_state_3_iv_0_0__g0_0_a3_0_cZ (
1651         .combout(vsync_state_3_iv_0_0__g0_0_a3_0),
1652         .clk(GND),
1653         .dataa(vsync_state_2),
1654         .datab(un12_vsync_counter_6),
1655         .datac(un15_vsync_counter_4),
1656         .datad(VCC),
1657         .aclr(GND),
1658         .sclr(GND),
1659         .sload(GND),
1660         .ena(VCC),
1661         .inverta(GND),
1662         .aload(GND),
1663         .regcascin(GND)
1664 );
1665 defparam vsync_state_3_iv_0_0__g0_0_a3_0_cZ.operation_mode="normal";
1666 defparam vsync_state_3_iv_0_0__g0_0_a3_0_cZ.output_mode="comb_only";
1667 defparam vsync_state_3_iv_0_0__g0_0_a3_0_cZ.lut_mask="8080";
1668 defparam vsync_state_3_iv_0_0__g0_0_a3_0_cZ.synch_mode="off";
1669 defparam vsync_state_3_iv_0_0__g0_0_a3_0_cZ.sum_lutc_input="datac";
1670 // @13:139
1671   stratix_lcell LINE_COUNT_next_un10_line_counter_siglto8 (
1672         .combout(un10_line_counter_siglto8),
1673         .clk(GND),
1674         .dataa(line_counter_sig_6),
1675         .datab(line_counter_sig_7),
1676         .datac(line_counter_sig_8),
1677         .datad(un10_line_counter_siglto5),
1678         .aclr(GND),
1679         .sclr(GND),
1680         .sload(GND),
1681         .ena(VCC),
1682         .inverta(GND),
1683         .aload(GND),
1684         .regcascin(GND)
1685 );
1686 defparam LINE_COUNT_next_un10_line_counter_siglto8.operation_mode="normal";
1687 defparam LINE_COUNT_next_un10_line_counter_siglto8.output_mode="comb_only";
1688 defparam LINE_COUNT_next_un10_line_counter_siglto8.lut_mask="ff7f";
1689 defparam LINE_COUNT_next_un10_line_counter_siglto8.synch_mode="off";
1690 defparam LINE_COUNT_next_un10_line_counter_siglto8.sum_lutc_input="datac";
1691 // @13:326
1692   stratix_lcell vsync_state_next_1_sqmuxa_1_cZ (
1693         .combout(vsync_state_next_1_sqmuxa_1),
1694         .clk(GND),
1695         .dataa(vsync_counter_0),
1696         .datab(vsync_counter_9),
1697         .datac(vsync_state_5),
1698         .datad(un14_vsync_counter_8),
1699         .aclr(GND),
1700         .sclr(GND),
1701         .sload(GND),
1702         .ena(VCC),
1703         .inverta(GND),
1704         .aload(GND),
1705         .regcascin(GND)
1706 );
1707 defparam vsync_state_next_1_sqmuxa_1_cZ.operation_mode="normal";
1708 defparam vsync_state_next_1_sqmuxa_1_cZ.output_mode="comb_only";
1709 defparam vsync_state_next_1_sqmuxa_1_cZ.lut_mask="d0f0";
1710 defparam vsync_state_next_1_sqmuxa_1_cZ.synch_mode="off";
1711 defparam vsync_state_next_1_sqmuxa_1_cZ.sum_lutc_input="datac";
1712 // @13:331
1713   stratix_lcell vsync_state_next_1_sqmuxa_2_cZ (
1714         .combout(vsync_state_next_1_sqmuxa_2),
1715         .clk(GND),
1716         .dataa(vsync_state_4),
1717         .datab(un12_vsync_counter_7),
1718         .datac(un13_vsync_counter_4),
1719         .datad(VCC),
1720         .aclr(GND),
1721         .sclr(GND),
1722         .sload(GND),
1723         .ena(VCC),
1724         .inverta(GND),
1725         .aload(GND),
1726         .regcascin(GND)
1727 );
1728 defparam vsync_state_next_1_sqmuxa_2_cZ.operation_mode="normal";
1729 defparam vsync_state_next_1_sqmuxa_2_cZ.output_mode="comb_only";
1730 defparam vsync_state_next_1_sqmuxa_2_cZ.lut_mask="2a2a";
1731 defparam vsync_state_next_1_sqmuxa_2_cZ.synch_mode="off";
1732 defparam vsync_state_next_1_sqmuxa_2_cZ.sum_lutc_input="datac";
1733 // @13:339
1734   stratix_lcell vsync_state_next_1_sqmuxa_3_cZ (
1735         .combout(vsync_state_next_1_sqmuxa_3),
1736         .clk(GND),
1737         .dataa(vsync_counter_0),
1738         .datab(vsync_counter_9),
1739         .datac(vsync_state_3),
1740         .datad(un14_vsync_counter_8),
1741         .aclr(GND),
1742         .sclr(GND),
1743         .sload(GND),
1744         .ena(VCC),
1745         .inverta(GND),
1746         .aload(GND),
1747         .regcascin(GND)
1748 );
1749 defparam vsync_state_next_1_sqmuxa_3_cZ.operation_mode="normal";
1750 defparam vsync_state_next_1_sqmuxa_3_cZ.output_mode="comb_only";
1751 defparam vsync_state_next_1_sqmuxa_3_cZ.lut_mask="70f0";
1752 defparam vsync_state_next_1_sqmuxa_3_cZ.synch_mode="off";
1753 defparam vsync_state_next_1_sqmuxa_3_cZ.sum_lutc_input="datac";
1754 // @10:159
1755   stratix_lcell G_16 (
1756         .combout(G_16_i),
1757         .clk(GND),
1758         .dataa(vsync_state_0),
1759         .datab(vsync_state_6),
1760         .datac(un9_vsync_counterlt9),
1761         .datad(un6_dly_counter_0_x),
1762         .aclr(GND),
1763         .sclr(GND),
1764         .sload(GND),
1765         .ena(VCC),
1766         .inverta(GND),
1767         .aload(GND),
1768         .regcascin(GND)
1769 );
1770 defparam G_16.operation_mode="normal";
1771 defparam G_16.output_mode="comb_only";
1772 defparam G_16.lut_mask="0f1f";
1773 defparam G_16.synch_mode="off";
1774 defparam G_16.sum_lutc_input="datac";
1775 // @10:159
1776   stratix_lcell G_2 (
1777         .combout(G_2_i),
1778         .clk(GND),
1779         .dataa(hsync_state_0),
1780         .datab(hsync_state_6),
1781         .datac(un9_hsync_counterlt9),
1782         .datad(un6_dly_counter_0_x),
1783         .aclr(GND),
1784         .sclr(GND),
1785         .sload(GND),
1786         .ena(VCC),
1787         .inverta(GND),
1788         .aload(GND),
1789         .regcascin(GND)
1790 );
1791 defparam G_2.operation_mode="normal";
1792 defparam G_2.output_mode="comb_only";
1793 defparam G_2.lut_mask="0f1f";
1794 defparam G_2.synch_mode="off";
1795 defparam G_2.sum_lutc_input="datac";
1796 // @13:218
1797   stratix_lcell hsync_state_next_1_sqmuxa_2_cZ (
1798         .combout(hsync_state_next_1_sqmuxa_2),
1799         .clk(GND),
1800         .dataa(hsync_state_4),
1801         .datab(un11_hsync_counter_2),
1802         .datac(un10_hsync_counter_1),
1803         .datad(un11_hsync_counter_3),
1804         .aclr(GND),
1805         .sclr(GND),
1806         .sload(GND),
1807         .ena(VCC),
1808         .inverta(GND),
1809         .aload(GND),
1810         .regcascin(GND)
1811 );
1812 defparam hsync_state_next_1_sqmuxa_2_cZ.operation_mode="normal";
1813 defparam hsync_state_next_1_sqmuxa_2_cZ.output_mode="comb_only";
1814 defparam hsync_state_next_1_sqmuxa_2_cZ.lut_mask="2aaa";
1815 defparam hsync_state_next_1_sqmuxa_2_cZ.synch_mode="off";
1816 defparam hsync_state_next_1_sqmuxa_2_cZ.sum_lutc_input="datac";
1817 // @13:213
1818   stratix_lcell hsync_state_next_1_sqmuxa_1_cZ (
1819         .combout(hsync_state_next_1_sqmuxa_1),
1820         .clk(GND),
1821         .dataa(hsync_state_5),
1822         .datab(un10_hsync_counter_3),
1823         .datac(un10_hsync_counter_1),
1824         .datad(un10_hsync_counter_4),
1825         .aclr(GND),
1826         .sclr(GND),
1827         .sload(GND),
1828         .ena(VCC),
1829         .inverta(GND),
1830         .aload(GND),
1831         .regcascin(GND)
1832 );
1833 defparam hsync_state_next_1_sqmuxa_1_cZ.operation_mode="normal";
1834 defparam hsync_state_next_1_sqmuxa_1_cZ.output_mode="comb_only";
1835 defparam hsync_state_next_1_sqmuxa_1_cZ.lut_mask="2aaa";
1836 defparam hsync_state_next_1_sqmuxa_1_cZ.synch_mode="off";
1837 defparam hsync_state_next_1_sqmuxa_1_cZ.sum_lutc_input="datac";
1838 // @13:281
1839   stratix_lcell VSYNC_COUNT_next_un9_vsync_counterlt9 (
1840         .combout(un9_vsync_counterlt9),
1841         .clk(GND),
1842         .dataa(vsync_counter_4),
1843         .datab(vsync_counter_5),
1844         .datac(un9_vsync_counterlt9_5),
1845         .datad(un9_vsync_counterlt9_6),
1846         .aclr(GND),
1847         .sclr(GND),
1848         .sload(GND),
1849         .ena(VCC),
1850         .inverta(GND),
1851         .aload(GND),
1852         .regcascin(GND)
1853 );
1854 defparam VSYNC_COUNT_next_un9_vsync_counterlt9.operation_mode="normal";
1855 defparam VSYNC_COUNT_next_un9_vsync_counterlt9.output_mode="comb_only";
1856 defparam VSYNC_COUNT_next_un9_vsync_counterlt9.lut_mask="fff7";
1857 defparam VSYNC_COUNT_next_un9_vsync_counterlt9.synch_mode="off";
1858 defparam VSYNC_COUNT_next_un9_vsync_counterlt9.sum_lutc_input="datac";
1859 // @13:111
1860   stratix_lcell COLUMN_COUNT_next_un10_column_counter_siglt6 (
1861         .combout(un10_column_counter_siglt6),
1862         .clk(GND),
1863         .dataa(column_counter_sig_3),
1864         .datab(column_counter_sig_4),
1865         .datac(un10_column_counter_siglt6_3),
1866         .datad(un10_column_counter_siglt6_1),
1867         .aclr(GND),
1868         .sclr(GND),
1869         .sload(GND),
1870         .ena(VCC),
1871         .inverta(GND),
1872         .aload(GND),
1873         .regcascin(GND)
1874 );
1875 defparam COLUMN_COUNT_next_un10_column_counter_siglt6.operation_mode="normal";
1876 defparam COLUMN_COUNT_next_un10_column_counter_siglt6.output_mode="comb_only";
1877 defparam COLUMN_COUNT_next_un10_column_counter_siglt6.lut_mask="fff7";
1878 defparam COLUMN_COUNT_next_un10_column_counter_siglt6.synch_mode="off";
1879 defparam COLUMN_COUNT_next_un10_column_counter_siglt6.sum_lutc_input="datac";
1880 // @13:226
1881   stratix_lcell HSYNC_FSM_next_un12_hsync_counter (
1882         .combout(un12_hsync_counter),
1883         .clk(GND),
1884         .dataa(hsync_counter_0),
1885         .datab(hsync_counter_1),
1886         .datac(un12_hsync_counter_3),
1887         .datad(un12_hsync_counter_4),
1888         .aclr(GND),
1889         .sclr(GND),
1890         .sload(GND),
1891         .ena(VCC),
1892         .inverta(GND),
1893         .aload(GND),
1894         .regcascin(GND)
1895 );
1896 defparam HSYNC_FSM_next_un12_hsync_counter.operation_mode="normal";
1897 defparam HSYNC_FSM_next_un12_hsync_counter.output_mode="comb_only";
1898 defparam HSYNC_FSM_next_un12_hsync_counter.lut_mask="8000";
1899 defparam HSYNC_FSM_next_un12_hsync_counter.synch_mode="off";
1900 defparam HSYNC_FSM_next_un12_hsync_counter.sum_lutc_input="datac";
1901 // @13:231
1902   stratix_lcell HSYNC_FSM_next_un13_hsync_counter (
1903         .combout(un13_hsync_counter),
1904         .clk(GND),
1905         .dataa(hsync_counter_6),
1906         .datab(hsync_counter_7),
1907         .datac(un13_hsync_counter_2),
1908         .datad(un13_hsync_counter_7),
1909         .aclr(GND),
1910         .sclr(GND),
1911         .sload(GND),
1912         .ena(VCC),
1913         .inverta(GND),
1914         .aload(GND),
1915         .regcascin(GND)
1916 );
1917 defparam HSYNC_FSM_next_un13_hsync_counter.operation_mode="normal";
1918 defparam HSYNC_FSM_next_un13_hsync_counter.output_mode="comb_only";
1919 defparam HSYNC_FSM_next_un13_hsync_counter.lut_mask="1000";
1920 defparam HSYNC_FSM_next_un13_hsync_counter.synch_mode="off";
1921 defparam HSYNC_FSM_next_un13_hsync_counter.sum_lutc_input="datac";
1922 // @13:172
1923   stratix_lcell HSYNC_COUNT_next_un9_hsync_counterlt9 (
1924         .combout(un9_hsync_counterlt9),
1925         .clk(GND),
1926         .dataa(hsync_counter_4),
1927         .datab(hsync_counter_5),
1928         .datac(un9_hsync_counterlt9_3),
1929         .datad(un13_hsync_counter_7),
1930         .aclr(GND),
1931         .sclr(GND),
1932         .sload(GND),
1933         .ena(VCC),
1934         .inverta(GND),
1935         .aload(GND),
1936         .regcascin(GND)
1937 );
1938 defparam HSYNC_COUNT_next_un9_hsync_counterlt9.operation_mode="normal";
1939 defparam HSYNC_COUNT_next_un9_hsync_counterlt9.output_mode="comb_only";
1940 defparam HSYNC_COUNT_next_un9_hsync_counterlt9.lut_mask="f7ff";
1941 defparam HSYNC_COUNT_next_un9_hsync_counterlt9.synch_mode="off";
1942 defparam HSYNC_COUNT_next_un9_hsync_counterlt9.sum_lutc_input="datac";
1943 // @13:139
1944   stratix_lcell LINE_COUNT_next_un10_line_counter_siglto5 (
1945         .combout(un10_line_counter_siglto5),
1946         .clk(GND),
1947         .dataa(line_counter_sig_1),
1948         .datab(line_counter_sig_2),
1949         .datac(line_counter_sig_5),
1950         .datad(un10_line_counter_siglt4_2),
1951         .aclr(GND),
1952         .sclr(GND),
1953         .sload(GND),
1954         .ena(VCC),
1955         .inverta(GND),
1956         .aload(GND),
1957         .regcascin(GND)
1958 );
1959 defparam LINE_COUNT_next_un10_line_counter_siglto5.operation_mode="normal";
1960 defparam LINE_COUNT_next_un10_line_counter_siglto5.output_mode="comb_only";
1961 defparam LINE_COUNT_next_un10_line_counter_siglto5.lut_mask="0f07";
1962 defparam LINE_COUNT_next_un10_line_counter_siglto5.synch_mode="off";
1963 defparam LINE_COUNT_next_un10_line_counter_siglto5.sum_lutc_input="datac";
1964 // @13:331
1965   stratix_lcell VSYNC_FSM_next_un13_vsync_counter_4 (
1966         .combout(un13_vsync_counter_4),
1967         .clk(GND),
1968         .dataa(vsync_counter_0),
1969         .datab(vsync_counter_5),
1970         .datac(un13_vsync_counter_3),
1971         .datad(VCC),
1972         .aclr(GND),
1973         .sclr(GND),
1974         .sload(GND),
1975         .ena(VCC),
1976         .inverta(GND),
1977         .aload(GND),
1978         .regcascin(GND)
1979 );
1980 defparam VSYNC_FSM_next_un13_vsync_counter_4.operation_mode="normal";
1981 defparam VSYNC_FSM_next_un13_vsync_counter_4.output_mode="comb_only";
1982 defparam VSYNC_FSM_next_un13_vsync_counter_4.lut_mask="8080";
1983 defparam VSYNC_FSM_next_un13_vsync_counter_4.synch_mode="off";
1984 defparam VSYNC_FSM_next_un13_vsync_counter_4.sum_lutc_input="datac";
1985 // @13:344
1986   stratix_lcell VSYNC_FSM_next_un15_vsync_counter_4 (
1987         .combout(un15_vsync_counter_4),
1988         .clk(GND),
1989         .dataa(vsync_counter_1),
1990         .datab(vsync_counter_4),
1991         .datac(un15_vsync_counter_3),
1992         .datad(VCC),
1993         .aclr(GND),
1994         .sclr(GND),
1995         .sload(GND),
1996         .ena(VCC),
1997         .inverta(GND),
1998         .aload(GND),
1999         .regcascin(GND)
2000 );
2001 defparam VSYNC_FSM_next_un15_vsync_counter_4.operation_mode="normal";
2002 defparam VSYNC_FSM_next_un15_vsync_counter_4.output_mode="comb_only";
2003 defparam VSYNC_FSM_next_un15_vsync_counter_4.lut_mask="1010";
2004 defparam VSYNC_FSM_next_un15_vsync_counter_4.synch_mode="off";
2005 defparam VSYNC_FSM_next_un15_vsync_counter_4.sum_lutc_input="datac";
2006 // @13:139
2007   stratix_lcell line_counter_next_0_sqmuxa_1_1_cZ (
2008         .combout(line_counter_next_0_sqmuxa_1_1),
2009         .clk(GND),
2010         .dataa(reset_pin_c),
2011         .datab(dly_counter_0),
2012         .datac(dly_counter_1),
2013         .datad(vsync_state_1),
2014         .aclr(GND),
2015         .sclr(GND),
2016         .sload(GND),
2017         .ena(VCC),
2018         .inverta(GND),
2019         .aload(GND),
2020         .regcascin(GND)
2021 );
2022 defparam line_counter_next_0_sqmuxa_1_1_cZ.operation_mode="normal";
2023 defparam line_counter_next_0_sqmuxa_1_1_cZ.output_mode="comb_only";
2024 defparam line_counter_next_0_sqmuxa_1_1_cZ.lut_mask="0080";
2025 defparam line_counter_next_0_sqmuxa_1_1_cZ.synch_mode="off";
2026 defparam line_counter_next_0_sqmuxa_1_1_cZ.sum_lutc_input="datac";
2027   stratix_lcell v_sync_1_0_0_0_g1_cZ (
2028         .combout(v_sync_1_0_0_0_g1),
2029         .clk(GND),
2030         .dataa(vsync_state_2),
2031         .datab(v_sync),
2032         .datac(vsync_state_4),
2033         .datad(un1_vsync_state_2_0),
2034         .aclr(GND),
2035         .sclr(GND),
2036         .sload(GND),
2037         .ena(VCC),
2038         .inverta(GND),
2039         .aload(GND),
2040         .regcascin(GND)
2041 );
2042 defparam v_sync_1_0_0_0_g1_cZ.operation_mode="normal";
2043 defparam v_sync_1_0_0_0_g1_cZ.output_mode="comb_only";
2044 defparam v_sync_1_0_0_0_g1_cZ.lut_mask="ccd8";
2045 defparam v_sync_1_0_0_0_g1_cZ.synch_mode="off";
2046 defparam v_sync_1_0_0_0_g1_cZ.sum_lutc_input="datac";
2047   stratix_lcell h_enable_sig_1_0_0_0_g0_i_o4_cZ (
2048         .combout(h_enable_sig_1_0_0_0_g0_i_o4),
2049         .clk(GND),
2050         .dataa(vsync_state_4),
2051         .datab(vsync_state_5),
2052         .datac(un6_dly_counter_0_x),
2053         .datad(VCC),
2054         .aclr(GND),
2055         .sclr(GND),
2056         .sload(GND),
2057         .ena(VCC),
2058         .inverta(GND),
2059         .aload(GND),
2060         .regcascin(GND)
2061 );
2062 defparam h_enable_sig_1_0_0_0_g0_i_o4_cZ.operation_mode="normal";
2063 defparam h_enable_sig_1_0_0_0_g0_i_o4_cZ.output_mode="comb_only";
2064 defparam h_enable_sig_1_0_0_0_g0_i_o4_cZ.lut_mask="f1f1";
2065 defparam h_enable_sig_1_0_0_0_g0_i_o4_cZ.synch_mode="off";
2066 defparam h_enable_sig_1_0_0_0_g0_i_o4_cZ.sum_lutc_input="datac";
2067 // @13:278
2068   stratix_lcell vsync_counter_next_1_sqmuxa_cZ (
2069         .combout(vsync_counter_next_1_sqmuxa),
2070         .clk(GND),
2071         .dataa(reset_pin_c),
2072         .datab(dly_counter_0),
2073         .datac(dly_counter_1),
2074         .datad(d_set_vsync_counter),
2075         .aclr(GND),
2076         .sclr(GND),
2077         .sload(GND),
2078         .ena(VCC),
2079         .inverta(GND),
2080         .aload(GND),
2081         .regcascin(GND)
2082 );
2083 defparam vsync_counter_next_1_sqmuxa_cZ.operation_mode="normal";
2084 defparam vsync_counter_next_1_sqmuxa_cZ.output_mode="comb_only";
2085 defparam vsync_counter_next_1_sqmuxa_cZ.lut_mask="0080";
2086 defparam vsync_counter_next_1_sqmuxa_cZ.synch_mode="off";
2087 defparam vsync_counter_next_1_sqmuxa_cZ.sum_lutc_input="datac";
2088 // @13:339
2089   stratix_lcell VSYNC_FSM_next_un14_vsync_counter_8 (
2090         .combout(un14_vsync_counter_8),
2091         .clk(GND),
2092         .dataa(un12_vsync_counter_6),
2093         .datab(un12_vsync_counter_7),
2094         .datac(VCC),
2095         .datad(VCC),
2096         .aclr(GND),
2097         .sclr(GND),
2098         .sload(GND),
2099         .ena(VCC),
2100         .inverta(GND),
2101         .aload(GND),
2102         .regcascin(GND)
2103 );
2104 defparam VSYNC_FSM_next_un14_vsync_counter_8.operation_mode="normal";
2105 defparam VSYNC_FSM_next_un14_vsync_counter_8.output_mode="comb_only";
2106 defparam VSYNC_FSM_next_un14_vsync_counter_8.lut_mask="8888";
2107 defparam VSYNC_FSM_next_un14_vsync_counter_8.synch_mode="off";
2108 defparam VSYNC_FSM_next_un14_vsync_counter_8.sum_lutc_input="datac";
2109 // @13:169
2110   stratix_lcell hsync_counter_next_1_sqmuxa_cZ (
2111         .combout(hsync_counter_next_1_sqmuxa),
2112         .clk(GND),
2113         .dataa(reset_pin_c),
2114         .datab(dly_counter_0),
2115         .datac(dly_counter_1),
2116         .datad(d_set_hsync_counter),
2117         .aclr(GND),
2118         .sclr(GND),
2119         .sload(GND),
2120         .ena(VCC),
2121         .inverta(GND),
2122         .aload(GND),
2123         .regcascin(GND)
2124 );
2125 defparam hsync_counter_next_1_sqmuxa_cZ.operation_mode="normal";
2126 defparam hsync_counter_next_1_sqmuxa_cZ.output_mode="comb_only";
2127 defparam hsync_counter_next_1_sqmuxa_cZ.lut_mask="0080";
2128 defparam hsync_counter_next_1_sqmuxa_cZ.synch_mode="off";
2129 defparam hsync_counter_next_1_sqmuxa_cZ.sum_lutc_input="datac";
2130 // @13:111
2131   stratix_lcell column_counter_next_0_sqmuxa_1_1_cZ (
2132         .combout(column_counter_next_0_sqmuxa_1_1),
2133         .clk(GND),
2134         .dataa(reset_pin_c),
2135         .datab(dly_counter_0),
2136         .datac(dly_counter_1),
2137         .datad(hsync_state_1),
2138         .aclr(GND),
2139         .sclr(GND),
2140         .sload(GND),
2141         .ena(VCC),
2142         .inverta(GND),
2143         .aload(GND),
2144         .regcascin(GND)
2145 );
2146 defparam column_counter_next_0_sqmuxa_1_1_cZ.operation_mode="normal";
2147 defparam column_counter_next_0_sqmuxa_1_1_cZ.output_mode="comb_only";
2148 defparam column_counter_next_0_sqmuxa_1_1_cZ.lut_mask="0080";
2149 defparam column_counter_next_0_sqmuxa_1_1_cZ.synch_mode="off";
2150 defparam column_counter_next_0_sqmuxa_1_1_cZ.sum_lutc_input="datac";
2151   stratix_lcell h_sync_1_0_0_0_g1_cZ (
2152         .combout(h_sync_1_0_0_0_g1),
2153         .clk(GND),
2154         .dataa(hsync_state_2),
2155         .datab(h_sync),
2156         .datac(hsync_state_4),
2157         .datad(un1_hsync_state_3_0),
2158         .aclr(GND),
2159         .sclr(GND),
2160         .sload(GND),
2161         .ena(VCC),
2162         .inverta(GND),
2163         .aload(GND),
2164         .regcascin(GND)
2165 );
2166 defparam h_sync_1_0_0_0_g1_cZ.operation_mode="normal";
2167 defparam h_sync_1_0_0_0_g1_cZ.output_mode="comb_only";
2168 defparam h_sync_1_0_0_0_g1_cZ.lut_mask="ccd8";
2169 defparam h_sync_1_0_0_0_g1_cZ.synch_mode="off";
2170 defparam h_sync_1_0_0_0_g1_cZ.sum_lutc_input="datac";
2171   stratix_lcell v_enable_sig_1_0_0_0_g0_i_o4_cZ (
2172         .combout(v_enable_sig_1_0_0_0_g0_i_o4),
2173         .clk(GND),
2174         .dataa(hsync_state_4),
2175         .datab(hsync_state_5),
2176         .datac(un6_dly_counter_0_x),
2177         .datad(VCC),
2178         .aclr(GND),
2179         .sclr(GND),
2180         .sload(GND),
2181         .ena(VCC),
2182         .inverta(GND),
2183         .aload(GND),
2184         .regcascin(GND)
2185 );
2186 defparam v_enable_sig_1_0_0_0_g0_i_o4_cZ.operation_mode="normal";
2187 defparam v_enable_sig_1_0_0_0_g0_i_o4_cZ.output_mode="comb_only";
2188 defparam v_enable_sig_1_0_0_0_g0_i_o4_cZ.lut_mask="f1f1";
2189 defparam v_enable_sig_1_0_0_0_g0_i_o4_cZ.synch_mode="off";
2190 defparam v_enable_sig_1_0_0_0_g0_i_o4_cZ.sum_lutc_input="datac";
2191 // @13:226
2192   stratix_lcell HSYNC_FSM_next_un12_hsync_counter_4 (
2193         .combout(un12_hsync_counter_4),
2194         .clk(GND),
2195         .dataa(hsync_counter_6),
2196         .datab(hsync_counter_7),
2197         .datac(hsync_counter_8),
2198         .datad(hsync_counter_4),
2199         .aclr(GND),
2200         .sclr(GND),
2201         .sload(GND),
2202         .ena(VCC),
2203         .inverta(GND),
2204         .aload(GND),
2205         .regcascin(GND)
2206 );
2207 defparam HSYNC_FSM_next_un12_hsync_counter_4.operation_mode="normal";
2208 defparam HSYNC_FSM_next_un12_hsync_counter_4.output_mode="comb_only";
2209 defparam HSYNC_FSM_next_un12_hsync_counter_4.lut_mask="0010";
2210 defparam HSYNC_FSM_next_un12_hsync_counter_4.synch_mode="off";
2211 defparam HSYNC_FSM_next_un12_hsync_counter_4.sum_lutc_input="datac";
2212 // @13:226
2213   stratix_lcell HSYNC_FSM_next_un12_hsync_counter_3 (
2214         .combout(un12_hsync_counter_3),
2215         .clk(GND),
2216         .dataa(hsync_counter_9),
2217         .datab(hsync_counter_5),
2218         .datac(hsync_counter_2),
2219         .datad(hsync_counter_3),
2220         .aclr(GND),
2221         .sclr(GND),
2222         .sload(GND),
2223         .ena(VCC),
2224         .inverta(GND),
2225         .aload(GND),
2226         .regcascin(GND)
2227 );
2228 defparam HSYNC_FSM_next_un12_hsync_counter_3.operation_mode="normal";
2229 defparam HSYNC_FSM_next_un12_hsync_counter_3.output_mode="comb_only";
2230 defparam HSYNC_FSM_next_un12_hsync_counter_3.lut_mask="0020";
2231 defparam HSYNC_FSM_next_un12_hsync_counter_3.synch_mode="off";
2232 defparam HSYNC_FSM_next_un12_hsync_counter_3.sum_lutc_input="datac";
2233 // @13:218
2234   stratix_lcell HSYNC_FSM_next_un11_hsync_counter_3 (
2235         .combout(un11_hsync_counter_3),
2236         .clk(GND),
2237         .dataa(hsync_counter_0),
2238         .datab(hsync_counter_1),
2239         .datac(hsync_counter_3),
2240         .datad(hsync_counter_4),
2241         .aclr(GND),
2242         .sclr(GND),
2243         .sload(GND),
2244         .ena(VCC),
2245         .inverta(GND),
2246         .aload(GND),
2247         .regcascin(GND)
2248 );
2249 defparam HSYNC_FSM_next_un11_hsync_counter_3.operation_mode="normal";
2250 defparam HSYNC_FSM_next_un11_hsync_counter_3.output_mode="comb_only";
2251 defparam HSYNC_FSM_next_un11_hsync_counter_3.lut_mask="0008";
2252 defparam HSYNC_FSM_next_un11_hsync_counter_3.synch_mode="off";
2253 defparam HSYNC_FSM_next_un11_hsync_counter_3.sum_lutc_input="datac";
2254 // @13:218
2255   stratix_lcell HSYNC_FSM_next_un11_hsync_counter_2 (
2256         .combout(un11_hsync_counter_2),
2257         .clk(GND),
2258         .dataa(hsync_counter_2),
2259         .datab(hsync_counter_7),
2260         .datac(hsync_counter_6),
2261         .datad(VCC),
2262         .aclr(GND),
2263         .sclr(GND),
2264         .sload(GND),
2265         .ena(VCC),
2266         .inverta(GND),
2267         .aload(GND),
2268         .regcascin(GND)
2269 );
2270 defparam HSYNC_FSM_next_un11_hsync_counter_2.operation_mode="normal";
2271 defparam HSYNC_FSM_next_un11_hsync_counter_2.output_mode="comb_only";
2272 defparam HSYNC_FSM_next_un11_hsync_counter_2.lut_mask="0808";
2273 defparam HSYNC_FSM_next_un11_hsync_counter_2.synch_mode="off";
2274 defparam HSYNC_FSM_next_un11_hsync_counter_2.sum_lutc_input="datac";
2275 // @13:172
2276   stratix_lcell HSYNC_COUNT_next_un9_hsync_counterlt9_3 (
2277         .combout(un9_hsync_counterlt9_3),
2278         .clk(GND),
2279         .dataa(hsync_counter_6),
2280         .datab(hsync_counter_7),
2281         .datac(hsync_counter_8),
2282         .datad(hsync_counter_9),
2283         .aclr(GND),
2284         .sclr(GND),
2285         .sload(GND),
2286         .ena(VCC),
2287         .inverta(GND),
2288         .aload(GND),
2289         .regcascin(GND)
2290 );
2291 defparam HSYNC_COUNT_next_un9_hsync_counterlt9_3.operation_mode="normal";
2292 defparam HSYNC_COUNT_next_un9_hsync_counterlt9_3.output_mode="comb_only";
2293 defparam HSYNC_COUNT_next_un9_hsync_counterlt9_3.lut_mask="7fff";
2294 defparam HSYNC_COUNT_next_un9_hsync_counterlt9_3.synch_mode="off";
2295 defparam HSYNC_COUNT_next_un9_hsync_counterlt9_3.sum_lutc_input="datac";
2296 // @13:231
2297   stratix_lcell HSYNC_FSM_next_un13_hsync_counter_2 (
2298         .combout(un13_hsync_counter_2),
2299         .clk(GND),
2300         .dataa(hsync_counter_8),
2301         .datab(hsync_counter_9),
2302         .datac(hsync_counter_4),
2303         .datad(hsync_counter_5),
2304         .aclr(GND),
2305         .sclr(GND),
2306         .sload(GND),
2307         .ena(VCC),
2308         .inverta(GND),
2309         .aload(GND),
2310         .regcascin(GND)
2311 );
2312 defparam HSYNC_FSM_next_un13_hsync_counter_2.operation_mode="normal";
2313 defparam HSYNC_FSM_next_un13_hsync_counter_2.output_mode="comb_only";
2314 defparam HSYNC_FSM_next_un13_hsync_counter_2.lut_mask="0080";
2315 defparam HSYNC_FSM_next_un13_hsync_counter_2.synch_mode="off";
2316 defparam HSYNC_FSM_next_un13_hsync_counter_2.sum_lutc_input="datac";
2317 // @13:281
2318   stratix_lcell VSYNC_COUNT_next_un9_vsync_counterlt9_6 (
2319         .combout(un9_vsync_counterlt9_6),
2320         .clk(GND),
2321         .dataa(vsync_counter_2),
2322         .datab(vsync_counter_3),
2323         .datac(vsync_counter_0),
2324         .datad(vsync_counter_1),
2325         .aclr(GND),
2326         .sclr(GND),
2327         .sload(GND),
2328         .ena(VCC),
2329         .inverta(GND),
2330         .aload(GND),
2331         .regcascin(GND)
2332 );
2333 defparam VSYNC_COUNT_next_un9_vsync_counterlt9_6.operation_mode="normal";
2334 defparam VSYNC_COUNT_next_un9_vsync_counterlt9_6.output_mode="comb_only";
2335 defparam VSYNC_COUNT_next_un9_vsync_counterlt9_6.lut_mask="7fff";
2336 defparam VSYNC_COUNT_next_un9_vsync_counterlt9_6.synch_mode="off";
2337 defparam VSYNC_COUNT_next_un9_vsync_counterlt9_6.sum_lutc_input="datac";
2338 // @13:281
2339   stratix_lcell VSYNC_COUNT_next_un9_vsync_counterlt9_5 (
2340         .combout(un9_vsync_counterlt9_5),
2341         .clk(GND),
2342         .dataa(vsync_counter_8),
2343         .datab(vsync_counter_9),
2344         .datac(vsync_counter_6),
2345         .datad(vsync_counter_7),
2346         .aclr(GND),
2347         .sclr(GND),
2348         .sload(GND),
2349         .ena(VCC),
2350         .inverta(GND),
2351         .aload(GND),
2352         .regcascin(GND)
2353 );
2354 defparam VSYNC_COUNT_next_un9_vsync_counterlt9_5.operation_mode="normal";
2355 defparam VSYNC_COUNT_next_un9_vsync_counterlt9_5.output_mode="comb_only";
2356 defparam VSYNC_COUNT_next_un9_vsync_counterlt9_5.lut_mask="7fff";
2357 defparam VSYNC_COUNT_next_un9_vsync_counterlt9_5.synch_mode="off";
2358 defparam VSYNC_COUNT_next_un9_vsync_counterlt9_5.sum_lutc_input="datac";
2359 // @13:331
2360   stratix_lcell VSYNC_FSM_next_un13_vsync_counter_3 (
2361         .combout(un13_vsync_counter_3),
2362         .clk(GND),
2363         .dataa(vsync_counter_6),
2364         .datab(vsync_counter_7),
2365         .datac(vsync_counter_8),
2366         .datad(vsync_counter_9),
2367         .aclr(GND),
2368         .sclr(GND),
2369         .sload(GND),
2370         .ena(VCC),
2371         .inverta(GND),
2372         .aload(GND),
2373         .regcascin(GND)
2374 );
2375 defparam VSYNC_FSM_next_un13_vsync_counter_3.operation_mode="normal";
2376 defparam VSYNC_FSM_next_un13_vsync_counter_3.output_mode="comb_only";
2377 defparam VSYNC_FSM_next_un13_vsync_counter_3.lut_mask="0001";
2378 defparam VSYNC_FSM_next_un13_vsync_counter_3.synch_mode="off";
2379 defparam VSYNC_FSM_next_un13_vsync_counter_3.sum_lutc_input="datac";
2380 // @13:344
2381   stratix_lcell VSYNC_FSM_next_un15_vsync_counter_3 (
2382         .combout(un15_vsync_counter_3),
2383         .clk(GND),
2384         .dataa(vsync_counter_3),
2385         .datab(vsync_counter_9),
2386         .datac(vsync_counter_0),
2387         .datad(vsync_counter_2),
2388         .aclr(GND),
2389         .sclr(GND),
2390         .sload(GND),
2391         .ena(VCC),
2392         .inverta(GND),
2393         .aload(GND),
2394         .regcascin(GND)
2395 );
2396 defparam VSYNC_FSM_next_un15_vsync_counter_3.operation_mode="normal";
2397 defparam VSYNC_FSM_next_un15_vsync_counter_3.output_mode="comb_only";
2398 defparam VSYNC_FSM_next_un15_vsync_counter_3.lut_mask="0008";
2399 defparam VSYNC_FSM_next_un15_vsync_counter_3.synch_mode="off";
2400 defparam VSYNC_FSM_next_un15_vsync_counter_3.sum_lutc_input="datac";
2401 // @13:213
2402   stratix_lcell HSYNC_FSM_next_un10_hsync_counter_4 (
2403         .combout(un10_hsync_counter_4),
2404         .clk(GND),
2405         .dataa(hsync_counter_4),
2406         .datab(hsync_counter_6),
2407         .datac(hsync_counter_1),
2408         .datad(hsync_counter_3),
2409         .aclr(GND),
2410         .sclr(GND),
2411         .sload(GND),
2412         .ena(VCC),
2413         .inverta(GND),
2414         .aload(GND),
2415         .regcascin(GND)
2416 );
2417 defparam HSYNC_FSM_next_un10_hsync_counter_4.operation_mode="normal";
2418 defparam HSYNC_FSM_next_un10_hsync_counter_4.output_mode="comb_only";
2419 defparam HSYNC_FSM_next_un10_hsync_counter_4.lut_mask="8000";
2420 defparam HSYNC_FSM_next_un10_hsync_counter_4.synch_mode="off";
2421 defparam HSYNC_FSM_next_un10_hsync_counter_4.sum_lutc_input="datac";
2422 // @13:213
2423   stratix_lcell HSYNC_FSM_next_un10_hsync_counter_3 (
2424         .combout(un10_hsync_counter_3),
2425         .clk(GND),
2426         .dataa(hsync_counter_0),
2427         .datab(hsync_counter_7),
2428         .datac(hsync_counter_2),
2429         .datad(VCC),
2430         .aclr(GND),
2431         .sclr(GND),
2432         .sload(GND),
2433         .ena(VCC),
2434         .inverta(GND),
2435         .aload(GND),
2436         .regcascin(GND)
2437 );
2438 defparam HSYNC_FSM_next_un10_hsync_counter_3.operation_mode="normal";
2439 defparam HSYNC_FSM_next_un10_hsync_counter_3.output_mode="comb_only";
2440 defparam HSYNC_FSM_next_un10_hsync_counter_3.lut_mask="0101";
2441 defparam HSYNC_FSM_next_un10_hsync_counter_3.synch_mode="off";
2442 defparam HSYNC_FSM_next_un10_hsync_counter_3.sum_lutc_input="datac";
2443 // @13:139
2444   stratix_lcell LINE_COUNT_next_un10_line_counter_siglt4_2 (
2445         .combout(un10_line_counter_siglt4_2),
2446         .clk(GND),
2447         .dataa(line_counter_sig_3),
2448         .datab(line_counter_sig_4),
2449         .datac(line_counter_sig_0),
2450         .datad(VCC),
2451         .aclr(GND),
2452         .sclr(GND),
2453         .sload(GND),
2454         .ena(VCC),
2455         .inverta(GND),
2456         .aload(GND),
2457         .regcascin(GND)
2458 );
2459 defparam LINE_COUNT_next_un10_line_counter_siglt4_2.operation_mode="normal";
2460 defparam LINE_COUNT_next_un10_line_counter_siglt4_2.output_mode="comb_only";
2461 defparam LINE_COUNT_next_un10_line_counter_siglt4_2.lut_mask="7f7f";
2462 defparam LINE_COUNT_next_un10_line_counter_siglt4_2.synch_mode="off";
2463 defparam LINE_COUNT_next_un10_line_counter_siglt4_2.sum_lutc_input="datac";
2464 // @13:326
2465   stratix_lcell VSYNC_FSM_next_un12_vsync_counter_6 (
2466         .combout(un12_vsync_counter_6),
2467         .clk(GND),
2468         .dataa(vsync_counter_7),
2469         .datab(vsync_counter_8),
2470         .datac(vsync_counter_5),
2471         .datad(vsync_counter_6),
2472         .aclr(GND),
2473         .sclr(GND),
2474         .sload(GND),
2475         .ena(VCC),
2476         .inverta(GND),
2477         .aload(GND),
2478         .regcascin(GND)
2479 );
2480 defparam VSYNC_FSM_next_un12_vsync_counter_6.operation_mode="normal";
2481 defparam VSYNC_FSM_next_un12_vsync_counter_6.output_mode="comb_only";
2482 defparam VSYNC_FSM_next_un12_vsync_counter_6.lut_mask="0001";
2483 defparam VSYNC_FSM_next_un12_vsync_counter_6.synch_mode="off";
2484 defparam VSYNC_FSM_next_un12_vsync_counter_6.sum_lutc_input="datac";
2485 // @13:326
2486   stratix_lcell VSYNC_FSM_next_un12_vsync_counter_7 (
2487         .combout(un12_vsync_counter_7),
2488         .clk(GND),
2489         .dataa(vsync_counter_3),
2490         .datab(vsync_counter_4),
2491         .datac(vsync_counter_1),
2492         .datad(vsync_counter_2),
2493         .aclr(GND),
2494         .sclr(GND),
2495         .sload(GND),
2496         .ena(VCC),
2497         .inverta(GND),
2498         .aload(GND),
2499         .regcascin(GND)
2500 );
2501 defparam VSYNC_FSM_next_un12_vsync_counter_7.operation_mode="normal";
2502 defparam VSYNC_FSM_next_un12_vsync_counter_7.output_mode="comb_only";
2503 defparam VSYNC_FSM_next_un12_vsync_counter_7.lut_mask="0001";
2504 defparam VSYNC_FSM_next_un12_vsync_counter_7.synch_mode="off";
2505 defparam VSYNC_FSM_next_un12_vsync_counter_7.sum_lutc_input="datac";
2506 // @13:111
2507   stratix_lcell COLUMN_COUNT_next_un10_column_counter_siglt6_1 (
2508         .combout(un10_column_counter_siglt6_1),
2509         .clk(GND),
2510         .dataa(column_counter_sig_0),
2511         .datab(column_counter_sig_2),
2512         .datac(column_counter_sig_1),
2513         .datad(VCC),
2514         .aclr(GND),
2515         .sclr(GND),
2516         .sload(GND),
2517         .ena(VCC),
2518         .inverta(GND),
2519         .aload(GND),
2520         .regcascin(GND)
2521 );
2522 defparam COLUMN_COUNT_next_un10_column_counter_siglt6_1.operation_mode="normal";
2523 defparam COLUMN_COUNT_next_un10_column_counter_siglt6_1.output_mode="comb_only";
2524 defparam COLUMN_COUNT_next_un10_column_counter_siglt6_1.lut_mask="7f7f";
2525 defparam COLUMN_COUNT_next_un10_column_counter_siglt6_1.synch_mode="off";
2526 defparam COLUMN_COUNT_next_un10_column_counter_siglt6_1.sum_lutc_input="datac";
2527 // @13:231
2528   stratix_lcell HSYNC_FSM_next_un13_hsync_counter_7 (
2529         .combout(un13_hsync_counter_7),
2530         .clk(GND),
2531         .dataa(hsync_counter_2),
2532         .datab(hsync_counter_3),
2533         .datac(hsync_counter_0),
2534         .datad(hsync_counter_1),
2535         .aclr(GND),
2536         .sclr(GND),
2537         .sload(GND),
2538         .ena(VCC),
2539         .inverta(GND),
2540         .aload(GND),
2541         .regcascin(GND)
2542 );
2543 defparam HSYNC_FSM_next_un13_hsync_counter_7.operation_mode="normal";
2544 defparam HSYNC_FSM_next_un13_hsync_counter_7.output_mode="comb_only";
2545 defparam HSYNC_FSM_next_un13_hsync_counter_7.lut_mask="8000";
2546 defparam HSYNC_FSM_next_un13_hsync_counter_7.synch_mode="off";
2547 defparam HSYNC_FSM_next_un13_hsync_counter_7.sum_lutc_input="datac";
2548 // @13:213
2549   stratix_lcell HSYNC_FSM_next_un10_hsync_counter_1 (
2550         .combout(un10_hsync_counter_1),
2551         .clk(GND),
2552         .dataa(hsync_counter_5),
2553         .datab(hsync_counter_8),
2554         .datac(hsync_counter_9),
2555         .datad(VCC),
2556         .aclr(GND),
2557         .sclr(GND),
2558         .sload(GND),
2559         .ena(VCC),
2560         .inverta(GND),
2561         .aload(GND),
2562         .regcascin(GND)
2563 );
2564 defparam HSYNC_FSM_next_un10_hsync_counter_1.operation_mode="normal";
2565 defparam HSYNC_FSM_next_un10_hsync_counter_1.output_mode="comb_only";
2566 defparam HSYNC_FSM_next_un10_hsync_counter_1.lut_mask="0101";
2567 defparam HSYNC_FSM_next_un10_hsync_counter_1.synch_mode="off";
2568 defparam HSYNC_FSM_next_un10_hsync_counter_1.sum_lutc_input="datac";
2569 // @13:206
2570   stratix_lcell un1_hsync_state_3_0_cZ (
2571         .combout(un1_hsync_state_3_0),
2572         .clk(GND),
2573         .dataa(hsync_state_3),
2574         .datab(hsync_state_1),
2575         .datac(VCC),
2576         .datad(VCC),
2577         .aclr(GND),
2578         .sclr(GND),
2579         .sload(GND),
2580         .ena(VCC),
2581         .inverta(GND),
2582         .aload(GND),
2583         .regcascin(GND)
2584 );
2585 defparam un1_hsync_state_3_0_cZ.operation_mode="normal";
2586 defparam un1_hsync_state_3_0_cZ.output_mode="comb_only";
2587 defparam un1_hsync_state_3_0_cZ.lut_mask="eeee";
2588 defparam un1_hsync_state_3_0_cZ.synch_mode="off";
2589 defparam un1_hsync_state_3_0_cZ.sum_lutc_input="datac";
2590 // @13:319
2591   stratix_lcell un1_vsync_state_2_0_cZ (
2592         .combout(un1_vsync_state_2_0),
2593         .clk(GND),
2594         .dataa(vsync_state_3),
2595         .datab(vsync_state_1),
2596         .datac(VCC),
2597         .datad(VCC),
2598         .aclr(GND),
2599         .sclr(GND),
2600         .sload(GND),
2601         .ena(VCC),
2602         .inverta(GND),
2603         .aload(GND),
2604         .regcascin(GND)
2605 );
2606 defparam un1_vsync_state_2_0_cZ.operation_mode="normal";
2607 defparam un1_vsync_state_2_0_cZ.output_mode="comb_only";
2608 defparam un1_vsync_state_2_0_cZ.lut_mask="eeee";
2609 defparam un1_vsync_state_2_0_cZ.synch_mode="off";
2610 defparam un1_vsync_state_2_0_cZ.sum_lutc_input="datac";
2611 // @13:361
2612   stratix_lcell d_set_vsync_counter_cZ (
2613         .combout(d_set_vsync_counter),
2614         .clk(GND),
2615         .dataa(vsync_state_6),
2616         .datab(vsync_state_0),
2617         .datac(VCC),
2618         .datad(VCC),
2619         .aclr(GND),
2620         .sclr(GND),
2621         .sload(GND),
2622         .ena(VCC),
2623         .inverta(GND),
2624         .aload(GND),
2625         .regcascin(GND)
2626 );
2627 defparam d_set_vsync_counter_cZ.operation_mode="normal";
2628 defparam d_set_vsync_counter_cZ.output_mode="comb_only";
2629 defparam d_set_vsync_counter_cZ.lut_mask="eeee";
2630 defparam d_set_vsync_counter_cZ.synch_mode="off";
2631 defparam d_set_vsync_counter_cZ.sum_lutc_input="datac";
2632 // @13:111
2633   stratix_lcell COLUMN_COUNT_next_un10_column_counter_siglt6_3 (
2634         .combout(un10_column_counter_siglt6_3),
2635         .clk(GND),
2636         .dataa(column_counter_sig_6),
2637         .datab(column_counter_sig_5),
2638         .datac(VCC),
2639         .datad(VCC),
2640         .aclr(GND),
2641         .sclr(GND),
2642         .sload(GND),
2643         .ena(VCC),
2644         .inverta(GND),
2645         .aload(GND),
2646         .regcascin(GND)
2647 );
2648 defparam COLUMN_COUNT_next_un10_column_counter_siglt6_3.operation_mode="normal";
2649 defparam COLUMN_COUNT_next_un10_column_counter_siglt6_3.output_mode="comb_only";
2650 defparam COLUMN_COUNT_next_un10_column_counter_siglt6_3.lut_mask="7777";
2651 defparam COLUMN_COUNT_next_un10_column_counter_siglt6_3.synch_mode="off";
2652 defparam COLUMN_COUNT_next_un10_column_counter_siglt6_3.sum_lutc_input="datac";
2653 // @13:248
2654   stratix_lcell d_set_hsync_counter_cZ (
2655         .combout(d_set_hsync_counter),
2656         .clk(GND),
2657         .dataa(hsync_state_6),
2658         .datab(hsync_state_0),
2659         .datac(VCC),
2660         .datad(VCC),
2661         .aclr(GND),
2662         .sclr(GND),
2663         .sload(GND),
2664         .ena(VCC),
2665         .inverta(GND),
2666         .aload(GND),
2667         .regcascin(GND)
2668 );
2669 defparam d_set_hsync_counter_cZ.operation_mode="normal";
2670 defparam d_set_hsync_counter_cZ.output_mode="comb_only";
2671 defparam d_set_hsync_counter_cZ.lut_mask="eeee";
2672 defparam d_set_hsync_counter_cZ.synch_mode="off";
2673 defparam d_set_hsync_counter_cZ.sum_lutc_input="datac";
2674 // @13:141
2675   stratix_lcell un1_line_counter_sig_9_ (
2676         .combout(un1_line_counter_sig_combout[9]),
2677         .clk(GND),
2678         .dataa(line_counter_sig_7),
2679         .datab(line_counter_sig_8),
2680         .datac(VCC),
2681         .datad(VCC),
2682         .aclr(GND),
2683         .sclr(GND),
2684         .sload(GND),
2685         .ena(VCC),
2686         .cin(un1_line_counter_sig_cout[7]),
2687         .inverta(GND),
2688         .aload(GND),
2689         .regcascin(GND)
2690 );
2691 defparam un1_line_counter_sig_9_.cin_used="true";
2692 defparam un1_line_counter_sig_9_.operation_mode="normal";
2693 defparam un1_line_counter_sig_9_.output_mode="comb_only";
2694 defparam un1_line_counter_sig_9_.lut_mask="6c6c";
2695 defparam un1_line_counter_sig_9_.synch_mode="off";
2696 defparam un1_line_counter_sig_9_.sum_lutc_input="cin";
2697 // @13:141
2698   stratix_lcell un1_line_counter_sig_8_ (
2699         .combout(un1_line_counter_sig_combout[8]),
2700         .clk(GND),
2701         .dataa(line_counter_sig_7),
2702         .datab(VCC),
2703         .datac(VCC),
2704         .datad(VCC),
2705         .aclr(GND),
2706         .sclr(GND),
2707         .sload(GND),
2708         .ena(VCC),
2709         .cin(un1_line_counter_sig_cout[6]),
2710         .inverta(GND),
2711         .aload(GND),
2712         .regcascin(GND)
2713 );
2714 defparam un1_line_counter_sig_8_.cin_used="true";
2715 defparam un1_line_counter_sig_8_.operation_mode="normal";
2716 defparam un1_line_counter_sig_8_.output_mode="comb_only";
2717 defparam un1_line_counter_sig_8_.lut_mask="5a5a";
2718 defparam un1_line_counter_sig_8_.synch_mode="off";
2719 defparam un1_line_counter_sig_8_.sum_lutc_input="cin";
2720 // @13:141
2721   stratix_lcell un1_line_counter_sig_7_ (
2722         .combout(un1_line_counter_sig_combout[7]),
2723         .cout(un1_line_counter_sig_cout[7]),
2724         .clk(GND),
2725         .dataa(line_counter_sig_5),
2726         .datab(line_counter_sig_6),
2727         .datac(VCC),
2728         .datad(VCC),
2729         .aclr(GND),
2730         .sclr(GND),
2731         .sload(GND),
2732         .ena(VCC),
2733         .cin(un1_line_counter_sig_cout[5]),
2734         .inverta(GND),
2735         .aload(GND),
2736         .regcascin(GND)
2737 );
2738 defparam un1_line_counter_sig_7_.cin_used="true";
2739 defparam un1_line_counter_sig_7_.operation_mode="arithmetic";
2740 defparam un1_line_counter_sig_7_.output_mode="comb_only";
2741 defparam un1_line_counter_sig_7_.lut_mask="6c80";
2742 defparam un1_line_counter_sig_7_.synch_mode="off";
2743 defparam un1_line_counter_sig_7_.sum_lutc_input="cin";
2744 // @13:141
2745   stratix_lcell un1_line_counter_sig_6_ (
2746         .combout(un1_line_counter_sig_combout[6]),
2747         .cout(un1_line_counter_sig_cout[6]),
2748         .clk(GND),
2749         .dataa(line_counter_sig_5),
2750         .datab(line_counter_sig_6),
2751         .datac(VCC),
2752         .datad(VCC),
2753         .aclr(GND),
2754         .sclr(GND),
2755         .sload(GND),
2756         .ena(VCC),
2757         .cin(un1_line_counter_sig_cout[4]),
2758         .inverta(GND),
2759         .aload(GND),
2760         .regcascin(GND)
2761 );
2762 defparam un1_line_counter_sig_6_.cin_used="true";
2763 defparam un1_line_counter_sig_6_.operation_mode="arithmetic";
2764 defparam un1_line_counter_sig_6_.output_mode="comb_only";
2765 defparam un1_line_counter_sig_6_.lut_mask="5a80";
2766 defparam un1_line_counter_sig_6_.synch_mode="off";
2767 defparam un1_line_counter_sig_6_.sum_lutc_input="cin";
2768 // @13:141
2769   stratix_lcell un1_line_counter_sig_5_ (
2770         .combout(un1_line_counter_sig_combout[5]),
2771         .cout(un1_line_counter_sig_cout[5]),
2772         .clk(GND),
2773         .dataa(line_counter_sig_3),
2774         .datab(line_counter_sig_4),
2775         .datac(VCC),
2776         .datad(VCC),
2777         .aclr(GND),
2778         .sclr(GND),
2779         .sload(GND),
2780         .ena(VCC),
2781         .cin(un1_line_counter_sig_cout[3]),
2782         .inverta(GND),
2783         .aload(GND),
2784         .regcascin(GND)
2785 );
2786 defparam un1_line_counter_sig_5_.cin_used="true";
2787 defparam un1_line_counter_sig_5_.operation_mode="arithmetic";
2788 defparam un1_line_counter_sig_5_.output_mode="comb_only";
2789 defparam un1_line_counter_sig_5_.lut_mask="6c80";
2790 defparam un1_line_counter_sig_5_.synch_mode="off";
2791 defparam un1_line_counter_sig_5_.sum_lutc_input="cin";
2792 // @13:141
2793   stratix_lcell un1_line_counter_sig_4_ (
2794         .combout(un1_line_counter_sig_combout[4]),
2795         .cout(un1_line_counter_sig_cout[4]),
2796         .clk(GND),
2797         .dataa(line_counter_sig_3),
2798         .datab(line_counter_sig_4),
2799         .datac(VCC),
2800         .datad(VCC),
2801         .aclr(GND),
2802         .sclr(GND),
2803         .sload(GND),
2804         .ena(VCC),
2805         .cin(un1_line_counter_sig_cout[2]),
2806         .inverta(GND),
2807         .aload(GND),
2808         .regcascin(GND)
2809 );
2810 defparam un1_line_counter_sig_4_.cin_used="true";
2811 defparam un1_line_counter_sig_4_.operation_mode="arithmetic";
2812 defparam un1_line_counter_sig_4_.output_mode="comb_only";
2813 defparam un1_line_counter_sig_4_.lut_mask="5a80";
2814 defparam un1_line_counter_sig_4_.synch_mode="off";
2815 defparam un1_line_counter_sig_4_.sum_lutc_input="cin";
2816 // @13:141
2817   stratix_lcell un1_line_counter_sig_3_ (
2818         .combout(un1_line_counter_sig_combout[3]),
2819         .cout(un1_line_counter_sig_cout[3]),
2820         .clk(GND),
2821         .dataa(line_counter_sig_1),
2822         .datab(line_counter_sig_2),
2823         .datac(VCC),
2824         .datad(VCC),
2825         .aclr(GND),
2826         .sclr(GND),
2827         .sload(GND),
2828         .ena(VCC),
2829         .cin(un1_line_counter_sig_cout[1]),
2830         .inverta(GND),
2831         .aload(GND),
2832         .regcascin(GND)
2833 );
2834 defparam un1_line_counter_sig_3_.cin_used="true";
2835 defparam un1_line_counter_sig_3_.operation_mode="arithmetic";
2836 defparam un1_line_counter_sig_3_.output_mode="comb_only";
2837 defparam un1_line_counter_sig_3_.lut_mask="6c80";
2838 defparam un1_line_counter_sig_3_.synch_mode="off";
2839 defparam un1_line_counter_sig_3_.sum_lutc_input="cin";
2840 // @13:141
2841   stratix_lcell un1_line_counter_sig_2_ (
2842         .combout(un1_line_counter_sig_combout[2]),
2843         .cout(un1_line_counter_sig_cout[2]),
2844         .clk(GND),
2845         .dataa(line_counter_sig_1),
2846         .datab(line_counter_sig_2),
2847         .datac(VCC),
2848         .datad(VCC),
2849         .aclr(GND),
2850         .sclr(GND),
2851         .sload(GND),
2852         .ena(VCC),
2853         .cin(un1_line_counter_sig_a_cout[1]),
2854         .inverta(GND),
2855         .aload(GND),
2856         .regcascin(GND)
2857 );
2858 defparam un1_line_counter_sig_2_.cin_used="true";
2859 defparam un1_line_counter_sig_2_.operation_mode="arithmetic";
2860 defparam un1_line_counter_sig_2_.output_mode="comb_only";
2861 defparam un1_line_counter_sig_2_.lut_mask="5a80";
2862 defparam un1_line_counter_sig_2_.synch_mode="off";
2863 defparam un1_line_counter_sig_2_.sum_lutc_input="cin";
2864 // @13:141
2865   stratix_lcell un1_line_counter_sig_a_1_ (
2866         .cout(un1_line_counter_sig_a_cout[1]),
2867         .clk(GND),
2868         .dataa(d_set_hsync_counter),
2869         .datab(line_counter_sig_0),
2870         .datac(VCC),
2871         .datad(VCC),
2872         .aclr(GND),
2873         .sclr(GND),
2874         .sload(GND),
2875         .ena(VCC),
2876         .inverta(GND),
2877         .aload(GND),
2878         .regcascin(GND)
2879 );
2880 defparam un1_line_counter_sig_a_1_.operation_mode="arithmetic";
2881 defparam un1_line_counter_sig_a_1_.output_mode="comb_only";
2882 defparam un1_line_counter_sig_a_1_.lut_mask="0088";
2883 defparam un1_line_counter_sig_a_1_.synch_mode="off";
2884 defparam un1_line_counter_sig_a_1_.sum_lutc_input="datac";
2885 // @13:141
2886   stratix_lcell un1_line_counter_sig_1_ (
2887         .combout(un1_line_counter_sig_combout[1]),
2888         .cout(un1_line_counter_sig_cout[1]),
2889         .clk(GND),
2890         .dataa(d_set_hsync_counter),
2891         .datab(line_counter_sig_0),
2892         .datac(VCC),
2893         .datad(VCC),
2894         .aclr(GND),
2895         .sclr(GND),
2896         .sload(GND),
2897         .ena(VCC),
2898         .inverta(GND),
2899         .aload(GND),
2900         .regcascin(GND)
2901 );
2902 defparam un1_line_counter_sig_1_.operation_mode="arithmetic";
2903 defparam un1_line_counter_sig_1_.output_mode="comb_only";
2904 defparam un1_line_counter_sig_1_.lut_mask="6688";
2905 defparam un1_line_counter_sig_1_.synch_mode="off";
2906 defparam un1_line_counter_sig_1_.sum_lutc_input="datac";
2907 // @13:112
2908   stratix_lcell un2_column_counter_next_9_ (
2909         .combout(un2_column_counter_next_combout[9]),
2910         .clk(GND),
2911         .dataa(column_counter_sig_8),
2912         .datab(column_counter_sig_9),
2913         .datac(VCC),
2914         .datad(VCC),
2915         .aclr(GND),
2916         .sclr(GND),
2917         .sload(GND),
2918         .ena(VCC),
2919         .cin(un2_column_counter_next_cout[7]),
2920         .inverta(GND),
2921         .aload(GND),
2922         .regcascin(GND)
2923 );
2924 defparam un2_column_counter_next_9_.cin_used="true";
2925 defparam un2_column_counter_next_9_.operation_mode="normal";
2926 defparam un2_column_counter_next_9_.output_mode="comb_only";
2927 defparam un2_column_counter_next_9_.lut_mask="6c6c";
2928 defparam un2_column_counter_next_9_.synch_mode="off";
2929 defparam un2_column_counter_next_9_.sum_lutc_input="cin";
2930 // @13:112
2931   stratix_lcell un2_column_counter_next_8_ (
2932         .combout(un2_column_counter_next_combout[8]),
2933         .clk(GND),
2934         .dataa(column_counter_sig_8),
2935         .datab(VCC),
2936         .datac(VCC),
2937         .datad(VCC),
2938         .aclr(GND),
2939         .sclr(GND),
2940         .sload(GND),
2941         .ena(VCC),
2942         .cin(un2_column_counter_next_cout[6]),
2943         .inverta(GND),
2944         .aload(GND),
2945         .regcascin(GND)
2946 );
2947 defparam un2_column_counter_next_8_.cin_used="true";
2948 defparam un2_column_counter_next_8_.operation_mode="normal";
2949 defparam un2_column_counter_next_8_.output_mode="comb_only";
2950 defparam un2_column_counter_next_8_.lut_mask="5a5a";
2951 defparam un2_column_counter_next_8_.synch_mode="off";
2952 defparam un2_column_counter_next_8_.sum_lutc_input="cin";
2953 // @13:112
2954   stratix_lcell un2_column_counter_next_7_ (
2955         .combout(un2_column_counter_next_combout[7]),
2956         .cout(un2_column_counter_next_cout[7]),
2957         .clk(GND),
2958         .dataa(column_counter_sig_6),
2959         .datab(column_counter_sig_7),
2960         .datac(VCC),
2961         .datad(VCC),
2962         .aclr(GND),
2963         .sclr(GND),
2964         .sload(GND),
2965         .ena(VCC),
2966         .cin(un2_column_counter_next_cout[5]),
2967         .inverta(GND),
2968         .aload(GND),
2969         .regcascin(GND)
2970 );
2971 defparam un2_column_counter_next_7_.cin_used="true";
2972 defparam un2_column_counter_next_7_.operation_mode="arithmetic";
2973 defparam un2_column_counter_next_7_.output_mode="comb_only";
2974 defparam un2_column_counter_next_7_.lut_mask="6c80";
2975 defparam un2_column_counter_next_7_.synch_mode="off";
2976 defparam un2_column_counter_next_7_.sum_lutc_input="cin";
2977 // @13:112
2978   stratix_lcell un2_column_counter_next_6_ (
2979         .combout(un2_column_counter_next_combout[6]),
2980         .cout(un2_column_counter_next_cout[6]),
2981         .clk(GND),
2982         .dataa(column_counter_sig_6),
2983         .datab(column_counter_sig_7),
2984         .datac(VCC),
2985         .datad(VCC),
2986         .aclr(GND),
2987         .sclr(GND),
2988         .sload(GND),
2989         .ena(VCC),
2990         .cin(un2_column_counter_next_cout[4]),
2991         .inverta(GND),
2992         .aload(GND),
2993         .regcascin(GND)
2994 );
2995 defparam un2_column_counter_next_6_.cin_used="true";
2996 defparam un2_column_counter_next_6_.operation_mode="arithmetic";
2997 defparam un2_column_counter_next_6_.output_mode="comb_only";
2998 defparam un2_column_counter_next_6_.lut_mask="5a80";
2999 defparam un2_column_counter_next_6_.synch_mode="off";
3000 defparam un2_column_counter_next_6_.sum_lutc_input="cin";
3001 // @13:112
3002   stratix_lcell un2_column_counter_next_5_ (
3003         .combout(un2_column_counter_next_combout[5]),
3004         .cout(un2_column_counter_next_cout[5]),
3005         .clk(GND),
3006         .dataa(column_counter_sig_4),
3007         .datab(column_counter_sig_5),
3008         .datac(VCC),
3009         .datad(VCC),
3010         .aclr(GND),
3011         .sclr(GND),
3012         .sload(GND),
3013         .ena(VCC),
3014         .cin(un2_column_counter_next_cout[3]),
3015         .inverta(GND),
3016         .aload(GND),
3017         .regcascin(GND)
3018 );
3019 defparam un2_column_counter_next_5_.cin_used="true";
3020 defparam un2_column_counter_next_5_.operation_mode="arithmetic";
3021 defparam un2_column_counter_next_5_.output_mode="comb_only";
3022 defparam un2_column_counter_next_5_.lut_mask="6c80";
3023 defparam un2_column_counter_next_5_.synch_mode="off";
3024 defparam un2_column_counter_next_5_.sum_lutc_input="cin";
3025 // @13:112
3026   stratix_lcell un2_column_counter_next_4_ (
3027         .combout(un2_column_counter_next_combout[4]),
3028         .cout(un2_column_counter_next_cout[4]),
3029         .clk(GND),
3030         .dataa(column_counter_sig_4),
3031         .datab(column_counter_sig_5),
3032         .datac(VCC),
3033         .datad(VCC),
3034         .aclr(GND),
3035         .sclr(GND),
3036         .sload(GND),
3037         .ena(VCC),
3038         .cin(un2_column_counter_next_cout[2]),
3039         .inverta(GND),
3040         .aload(GND),
3041         .regcascin(GND)
3042 );
3043 defparam un2_column_counter_next_4_.cin_used="true";
3044 defparam un2_column_counter_next_4_.operation_mode="arithmetic";
3045 defparam un2_column_counter_next_4_.output_mode="comb_only";
3046 defparam un2_column_counter_next_4_.lut_mask="5a80";
3047 defparam un2_column_counter_next_4_.synch_mode="off";
3048 defparam un2_column_counter_next_4_.sum_lutc_input="cin";
3049 // @13:112
3050   stratix_lcell un2_column_counter_next_3_ (
3051         .combout(un2_column_counter_next_combout[3]),
3052         .cout(un2_column_counter_next_cout[3]),
3053         .clk(GND),
3054         .dataa(column_counter_sig_2),
3055         .datab(column_counter_sig_3),
3056         .datac(VCC),
3057         .datad(VCC),
3058         .aclr(GND),
3059         .sclr(GND),
3060         .sload(GND),
3061         .ena(VCC),
3062         .cin(un2_column_counter_next_cout[1]),
3063         .inverta(GND),
3064         .aload(GND),
3065         .regcascin(GND)
3066 );
3067 defparam un2_column_counter_next_3_.cin_used="true";
3068 defparam un2_column_counter_next_3_.operation_mode="arithmetic";
3069 defparam un2_column_counter_next_3_.output_mode="comb_only";
3070 defparam un2_column_counter_next_3_.lut_mask="6c80";
3071 defparam un2_column_counter_next_3_.synch_mode="off";
3072 defparam un2_column_counter_next_3_.sum_lutc_input="cin";
3073 // @13:112
3074   stratix_lcell un2_column_counter_next_2_ (
3075         .combout(un2_column_counter_next_combout[2]),
3076         .cout(un2_column_counter_next_cout[2]),
3077         .clk(GND),
3078         .dataa(column_counter_sig_2),
3079         .datab(column_counter_sig_3),
3080         .datac(VCC),
3081         .datad(VCC),
3082         .aclr(GND),
3083         .sclr(GND),
3084         .sload(GND),
3085         .ena(VCC),
3086         .cin(un2_column_counter_next_cout[0]),
3087         .inverta(GND),
3088         .aload(GND),
3089         .regcascin(GND)
3090 );
3091 defparam un2_column_counter_next_2_.cin_used="true";
3092 defparam un2_column_counter_next_2_.operation_mode="arithmetic";
3093 defparam un2_column_counter_next_2_.output_mode="comb_only";
3094 defparam un2_column_counter_next_2_.lut_mask="5a80";
3095 defparam un2_column_counter_next_2_.synch_mode="off";
3096 defparam un2_column_counter_next_2_.sum_lutc_input="cin";
3097 // @13:112
3098   stratix_lcell un2_column_counter_next_1_ (
3099         .combout(un2_column_counter_next_combout[1]),
3100         .cout(un2_column_counter_next_cout[1]),
3101         .clk(GND),
3102         .dataa(column_counter_sig_0),
3103         .datab(column_counter_sig_1),
3104         .datac(VCC),
3105         .datad(VCC),
3106         .aclr(GND),
3107         .sclr(GND),
3108         .sload(GND),
3109         .ena(VCC),
3110         .inverta(GND),
3111         .aload(GND),
3112         .regcascin(GND)
3113 );
3114 defparam un2_column_counter_next_1_.operation_mode="arithmetic";
3115 defparam un2_column_counter_next_1_.output_mode="comb_only";
3116 defparam un2_column_counter_next_1_.lut_mask="6688";
3117 defparam un2_column_counter_next_1_.synch_mode="off";
3118 defparam un2_column_counter_next_1_.sum_lutc_input="datac";
3119 // @13:112
3120   stratix_lcell un2_column_counter_next_0_ (
3121         .cout(un2_column_counter_next_cout[0]),
3122         .clk(GND),
3123         .dataa(column_counter_sig_0),
3124         .datab(column_counter_sig_1),
3125         .datac(VCC),
3126         .datad(VCC),
3127         .aclr(GND),
3128         .sclr(GND),
3129         .sload(GND),
3130         .ena(VCC),
3131         .inverta(GND),
3132         .aload(GND),
3133         .regcascin(GND)
3134 );
3135 defparam un2_column_counter_next_0_.operation_mode="arithmetic";
3136 defparam un2_column_counter_next_0_.output_mode="comb_only";
3137 defparam un2_column_counter_next_0_.lut_mask="5588";
3138 defparam un2_column_counter_next_0_.synch_mode="off";
3139 defparam un2_column_counter_next_0_.sum_lutc_input="datac";
3140   assign  line_counter_next_0_sqmuxa_1_1_i = ~ line_counter_next_0_sqmuxa_1_1;
3141   assign  column_counter_next_0_sqmuxa_1_1_i = ~ column_counter_next_0_sqmuxa_1_1;
3142   assign  un9_vsync_counterlt9_i = ~ un9_vsync_counterlt9;
3143   assign  G_16_i_i = ~ G_16_i;
3144   assign  un9_hsync_counterlt9_i = ~ un9_hsync_counterlt9;
3145   assign  G_2_i_i = ~ G_2_i;
3146 endmodule /* vga_driver */
3147
3148 // VQM4.1+
3149 module vga_control (
3150   column_counter_sig_1,
3151   column_counter_sig_7,
3152   column_counter_sig_2,
3153   column_counter_sig_0,
3154   column_counter_sig_4,
3155   column_counter_sig_3,
3156   column_counter_sig_5,
3157   column_counter_sig_6,
3158   h_enable_sig,
3159   v_enable_sig,
3160   un10_column_counter_siglt6_1,
3161   g,
3162   un10_column_counter_siglt6_3,
3163   r,
3164   un6_dly_counter_0_x,
3165   clk_pin_c,
3166   b
3167 )
3168 ;
3169 input column_counter_sig_1 ;
3170 input column_counter_sig_7 ;
3171 input column_counter_sig_2 ;
3172 input column_counter_sig_0 ;
3173 input column_counter_sig_4 ;
3174 input column_counter_sig_3 ;
3175 input column_counter_sig_5 ;
3176 input column_counter_sig_6 ;
3177 input h_enable_sig ;
3178 input v_enable_sig ;
3179 input un10_column_counter_siglt6_1 ;
3180 output g ;
3181 input un10_column_counter_siglt6_3 ;
3182 output r ;
3183 input un6_dly_counter_0_x ;
3184 input clk_pin_c ;
3185 output b ;
3186 wire column_counter_sig_1 ;
3187 wire column_counter_sig_7 ;
3188 wire column_counter_sig_2 ;
3189 wire column_counter_sig_0 ;
3190 wire column_counter_sig_4 ;
3191 wire column_counter_sig_3 ;
3192 wire column_counter_sig_5 ;
3193 wire column_counter_sig_6 ;
3194 wire h_enable_sig ;
3195 wire v_enable_sig ;
3196 wire un10_column_counter_siglt6_1 ;
3197 wire g ;
3198 wire un10_column_counter_siglt6_3 ;
3199 wire r ;
3200 wire un6_dly_counter_0_x ;
3201 wire clk_pin_c ;
3202 wire b ;
3203 wire b_next_i_o3_0 ;
3204 wire b_next_i_a7_1 ;
3205 wire N_6_i_0_g0_0 ;
3206 wire N_4_i_0_g0_1 ;
3207 wire r_next_i_o7 ;
3208 wire N_23_i_0_g0_a ;
3209 wire g_next_i_o3 ;
3210 wire GND ;
3211 wire VCC ;
3212   assign VCC = 1'b1;
3213   assign GND = 1'b0;
3214 // @12:46
3215   stratix_lcell b_Z (
3216         .regout(b),
3217         .clk(clk_pin_c),
3218         .dataa(column_counter_sig_6),
3219         .datab(b_next_i_o3_0),
3220         .datac(b_next_i_a7_1),
3221         .datad(N_6_i_0_g0_0),
3222         .aclr(un6_dly_counter_0_x),
3223         .sclr(GND),
3224         .sload(GND),
3225         .ena(VCC),
3226         .inverta(GND),
3227         .aload(GND),
3228         .regcascin(GND)
3229 );
3230 defparam b_Z.operation_mode="normal";
3231 defparam b_Z.output_mode="reg_only";
3232 defparam b_Z.lut_mask="0700";
3233 defparam b_Z.synch_mode="off";
3234 defparam b_Z.sum_lutc_input="datac";
3235 // @12:46
3236   stratix_lcell r_Z (
3237         .regout(r),
3238         .clk(clk_pin_c),
3239         .dataa(column_counter_sig_6),
3240         .datab(un10_column_counter_siglt6_3),
3241         .datac(b_next_i_o3_0),
3242         .datad(N_4_i_0_g0_1),
3243         .aclr(un6_dly_counter_0_x),
3244         .sclr(GND),
3245         .sload(GND),
3246         .ena(VCC),
3247         .inverta(GND),
3248         .aload(GND),
3249         .regcascin(GND)
3250 );
3251 defparam r_Z.operation_mode="normal";
3252 defparam r_Z.output_mode="reg_only";
3253 defparam r_Z.lut_mask="1b00";
3254 defparam r_Z.synch_mode="off";
3255 defparam r_Z.sum_lutc_input="datac";
3256 // @12:46
3257   stratix_lcell g_Z (
3258         .regout(g),
3259         .clk(clk_pin_c),
3260         .dataa(column_counter_sig_6),
3261         .datab(column_counter_sig_5),
3262         .datac(r_next_i_o7),
3263         .datad(N_23_i_0_g0_a),
3264         .aclr(un6_dly_counter_0_x),
3265         .sclr(GND),
3266         .sload(GND),
3267         .ena(VCC),
3268         .inverta(GND),
3269         .aload(GND),
3270         .regcascin(GND)
3271 );
3272 defparam g_Z.operation_mode="normal";
3273 defparam g_Z.output_mode="reg_only";
3274 defparam g_Z.lut_mask="0400";
3275 defparam g_Z.synch_mode="off";
3276 defparam g_Z.sum_lutc_input="datac";
3277   stratix_lcell N_23_i_0_g0_a_cZ (
3278         .combout(N_23_i_0_g0_a),
3279         .clk(GND),
3280         .dataa(column_counter_sig_3),
3281         .datab(column_counter_sig_4),
3282         .datac(g_next_i_o3),
3283         .datad(un10_column_counter_siglt6_1),
3284         .aclr(GND),
3285         .sclr(GND),
3286         .sload(GND),
3287         .ena(VCC),
3288         .inverta(GND),
3289         .aload(GND),
3290         .regcascin(GND)
3291 );
3292 defparam N_23_i_0_g0_a_cZ.operation_mode="normal";
3293 defparam N_23_i_0_g0_a_cZ.output_mode="comb_only";
3294 defparam N_23_i_0_g0_a_cZ.lut_mask="6c6e";
3295 defparam N_23_i_0_g0_a_cZ.synch_mode="off";
3296 defparam N_23_i_0_g0_a_cZ.sum_lutc_input="datac";
3297   stratix_lcell N_4_i_0_g0_1_cZ (
3298         .combout(N_4_i_0_g0_1),
3299         .clk(GND),
3300         .dataa(column_counter_sig_5),
3301         .datab(column_counter_sig_6),
3302         .datac(g_next_i_o3),
3303         .datad(r_next_i_o7),
3304         .aclr(GND),
3305         .sclr(GND),
3306         .sload(GND),
3307         .ena(VCC),
3308         .inverta(GND),
3309         .aload(GND),
3310         .regcascin(GND)
3311 );
3312 defparam N_4_i_0_g0_1_cZ.operation_mode="normal";
3313 defparam N_4_i_0_g0_1_cZ.output_mode="comb_only";
3314 defparam N_4_i_0_g0_1_cZ.lut_mask="00ec";
3315 defparam N_4_i_0_g0_1_cZ.synch_mode="off";
3316 defparam N_4_i_0_g0_1_cZ.sum_lutc_input="datac";
3317   stratix_lcell N_6_i_0_g0_0_cZ (
3318         .combout(N_6_i_0_g0_0),
3319         .clk(GND),
3320         .dataa(column_counter_sig_5),
3321         .datab(column_counter_sig_6),
3322         .datac(un10_column_counter_siglt6_3),
3323         .datad(r_next_i_o7),
3324         .aclr(GND),
3325         .sclr(GND),
3326         .sload(GND),
3327         .ena(VCC),
3328         .inverta(GND),
3329         .aload(GND),
3330         .regcascin(GND)
3331 );
3332 defparam N_6_i_0_g0_0_cZ.operation_mode="normal";
3333 defparam N_6_i_0_g0_0_cZ.output_mode="comb_only";
3334 defparam N_6_i_0_g0_0_cZ.lut_mask="00ef";
3335 defparam N_6_i_0_g0_0_cZ.synch_mode="off";
3336 defparam N_6_i_0_g0_0_cZ.sum_lutc_input="datac";
3337 // @12:60
3338   stratix_lcell b_next_i_a7_1_cZ (
3339         .combout(b_next_i_a7_1),
3340         .clk(GND),
3341         .dataa(column_counter_sig_5),
3342         .datab(column_counter_sig_6),
3343         .datac(column_counter_sig_0),
3344         .datad(g_next_i_o3),
3345         .aclr(GND),
3346         .sclr(GND),
3347         .sload(GND),
3348         .ena(VCC),
3349         .inverta(GND),
3350         .aload(GND),
3351         .regcascin(GND)
3352 );
3353 defparam b_next_i_a7_1_cZ.operation_mode="normal";
3354 defparam b_next_i_a7_1_cZ.output_mode="comb_only";
3355 defparam b_next_i_a7_1_cZ.lut_mask="0001";
3356 defparam b_next_i_a7_1_cZ.synch_mode="off";
3357 defparam b_next_i_a7_1_cZ.sum_lutc_input="datac";
3358 // @12:60
3359   stratix_lcell b_next_i_o3_0_cZ (
3360         .combout(b_next_i_o3_0),
3361         .clk(GND),
3362         .dataa(column_counter_sig_3),
3363         .datab(column_counter_sig_4),
3364         .datac(column_counter_sig_2),
3365         .datad(column_counter_sig_5),
3366         .aclr(GND),
3367         .sclr(GND),
3368         .sload(GND),
3369         .ena(VCC),
3370         .inverta(GND),
3371         .aload(GND),
3372         .regcascin(GND)
3373 );
3374 defparam b_next_i_o3_0_cZ.operation_mode="normal";
3375 defparam b_next_i_o3_0_cZ.output_mode="comb_only";
3376 defparam b_next_i_o3_0_cZ.lut_mask="ff80";
3377 defparam b_next_i_o3_0_cZ.synch_mode="off";
3378 defparam b_next_i_o3_0_cZ.sum_lutc_input="datac";
3379 // @12:60
3380   stratix_lcell r_next_i_o7_cZ (
3381         .combout(r_next_i_o7),
3382         .clk(GND),
3383         .dataa(column_counter_sig_7),
3384         .datab(v_enable_sig),
3385         .datac(h_enable_sig),
3386         .datad(VCC),
3387         .aclr(GND),
3388         .sclr(GND),
3389         .sload(GND),
3390         .ena(VCC),
3391         .inverta(GND),
3392         .aload(GND),
3393         .regcascin(GND)
3394 );
3395 defparam r_next_i_o7_cZ.operation_mode="normal";
3396 defparam r_next_i_o7_cZ.output_mode="comb_only";
3397 defparam r_next_i_o7_cZ.lut_mask="bfbf";
3398 defparam r_next_i_o7_cZ.synch_mode="off";
3399 defparam r_next_i_o7_cZ.sum_lutc_input="datac";
3400 // @12:60
3401   stratix_lcell g_next_i_o3_cZ (
3402         .combout(g_next_i_o3),
3403         .clk(GND),
3404         .dataa(column_counter_sig_2),
3405         .datab(column_counter_sig_1),
3406         .datac(VCC),
3407         .datad(VCC),
3408         .aclr(GND),
3409         .sclr(GND),
3410         .sload(GND),
3411         .ena(VCC),
3412         .inverta(GND),
3413         .aload(GND),
3414         .regcascin(GND)
3415 );
3416 defparam g_next_i_o3_cZ.operation_mode="normal";
3417 defparam g_next_i_o3_cZ.output_mode="comb_only";
3418 defparam g_next_i_o3_cZ.lut_mask="eeee";
3419 defparam g_next_i_o3_cZ.synch_mode="off";
3420 defparam g_next_i_o3_cZ.sum_lutc_input="datac";
3421 endmodule /* vga_control */
3422
3423 // VQM4.1+
3424 module vga (
3425   clk_pin,
3426   reset_pin,
3427   r0_pin,
3428   r1_pin,
3429   r2_pin,
3430   g0_pin,
3431   g1_pin,
3432   g2_pin,
3433   b0_pin,
3434   b1_pin,
3435   hsync_pin,
3436   vsync_pin,
3437   seven_seg_pin,
3438   d_hsync,
3439   d_vsync,
3440   d_column_counter,
3441   d_line_counter,
3442   d_set_column_counter,
3443   d_set_line_counter,
3444   d_hsync_counter,
3445   d_vsync_counter,
3446   d_set_hsync_counter,
3447   d_set_vsync_counter,
3448   d_h_enable,
3449   d_v_enable,
3450   d_r,
3451   d_g,
3452   d_b,
3453   d_hsync_state,
3454   d_vsync_state,
3455   d_state_clk
3456 )
3457 ;
3458 input clk_pin ;
3459 input reset_pin ;
3460 output r0_pin ;
3461 output r1_pin ;
3462 output r2_pin ;
3463 output g0_pin ;
3464 output g1_pin ;
3465 output g2_pin ;
3466 output b0_pin ;
3467 output b1_pin ;
3468 output hsync_pin ;
3469 output vsync_pin ;
3470 output [13:0] seven_seg_pin ;
3471 output d_hsync ;
3472 output d_vsync ;
3473 output [9:0] d_column_counter ;
3474 output [8:0] d_line_counter ;
3475 output d_set_column_counter ;
3476 output d_set_line_counter ;
3477 output [9:0] d_hsync_counter ;
3478 output [9:0] d_vsync_counter ;
3479 output d_set_hsync_counter ;
3480 output d_set_vsync_counter ;
3481 output d_h_enable ;
3482 output d_v_enable ;
3483 output d_r ;
3484 output d_g ;
3485 output d_b ;
3486 output [0:6] d_hsync_state ;
3487 output [0:6] d_vsync_state ;
3488 output d_state_clk ;
3489 wire clk_pin ;
3490 wire reset_pin ;
3491 wire r0_pin ;
3492 wire r1_pin ;
3493 wire r2_pin ;
3494 wire g0_pin ;
3495 wire g1_pin ;
3496 wire g2_pin ;
3497 wire b0_pin ;
3498 wire b1_pin ;
3499 wire hsync_pin ;
3500 wire vsync_pin ;
3501 wire d_hsync ;
3502 wire d_vsync ;
3503 wire d_set_column_counter ;
3504 wire d_set_line_counter ;
3505 wire d_set_hsync_counter ;
3506 wire d_set_vsync_counter ;
3507 wire d_h_enable ;
3508 wire d_v_enable ;
3509 wire d_r ;
3510 wire d_g ;
3511 wire d_b ;
3512 wire d_state_clk ;
3513 wire [1:0] dly_counter;
3514 wire [9:0] vga_driver_unit_column_counter_sig;
3515 wire [8:0] vga_driver_unit_line_counter_sig;
3516 wire [9:0] vga_driver_unit_hsync_counter;
3517 wire [9:0] vga_driver_unit_vsync_counter;
3518 wire [6:0] vga_driver_unit_hsync_state;
3519 wire [6:0] vga_driver_unit_vsync_state;
3520 wire VCC ;
3521 wire GND ;
3522 wire vga_driver_unit_COLUMN_COUNT_next_un10_column_counter_siglt6_1 ;
3523 wire vga_driver_unit_COLUMN_COUNT_next_un10_column_counter_siglt6_3 ;
3524 wire DELAY_RESET_next_un6_dly_counter_0_x ;
3525 wire vga_driver_unit_h_sync ;
3526 wire vga_driver_unit_v_sync ;
3527 wire vga_driver_unit_d_set_hsync_counter ;
3528 wire vga_driver_unit_d_set_vsync_counter ;
3529 wire vga_driver_unit_h_enable_sig ;
3530 wire vga_driver_unit_v_enable_sig ;
3531 wire vga_control_unit_r ;
3532 wire vga_control_unit_g ;
3533 wire vga_control_unit_b ;
3534 wire G_49 ;
3535 wire reset_pin_c ;
3536 //@1:1
3537   assign VCC = 1'b1;
3538 //@1:1
3539   assign GND = 1'b0;
3540 // @10:111
3541   stratix_lcell dly_counter_1_ (
3542         .regout(dly_counter[1]),
3543         .clk(G_49),
3544         .dataa(reset_pin_c),
3545         .datab(dly_counter[0]),
3546         .datac(dly_counter[1]),
3547         .datad(VCC),
3548         .aclr(GND),
3549         .sclr(GND),
3550         .sload(GND),
3551         .ena(VCC),
3552         .inverta(GND),
3553         .aload(GND),
3554         .regcascin(GND)
3555 );
3556 defparam dly_counter_1_.operation_mode="normal";
3557 defparam dly_counter_1_.output_mode="reg_only";
3558 defparam dly_counter_1_.lut_mask="a8a8";
3559 defparam dly_counter_1_.synch_mode="off";
3560 defparam dly_counter_1_.sum_lutc_input="datac";
3561 // @10:111
3562   stratix_lcell dly_counter_0_ (
3563         .regout(dly_counter[0]),
3564         .clk(G_49),
3565         .dataa(reset_pin_c),
3566         .datab(dly_counter[0]),
3567         .datac(dly_counter[1]),
3568         .datad(VCC),
3569         .aclr(GND),
3570         .sclr(GND),
3571         .sload(GND),
3572         .ena(VCC),
3573         .inverta(GND),
3574         .aload(GND),
3575         .regcascin(GND)
3576 );
3577 defparam dly_counter_0_.operation_mode="normal";
3578 defparam dly_counter_0_.output_mode="reg_only";
3579 defparam dly_counter_0_.lut_mask="a2a2";
3580 defparam dly_counter_0_.synch_mode="off";
3581 defparam dly_counter_0_.sum_lutc_input="datac";
3582 // @6:42
3583   stratix_io reset_pin_in (
3584         .padio(reset_pin),
3585         .combout(reset_pin_c),
3586         .datain(GND),
3587         .oe(GND),
3588         .outclk(GND),
3589         .outclkena(VCC),
3590         .inclk(GND),
3591         .inclkena(VCC),
3592         .areset(GND),
3593         .sreset(GND)
3594 );
3595 defparam reset_pin_in.operation_mode = "input";
3596 // @6:41
3597   stratix_io clk_pin_in (
3598         .padio(clk_pin),
3599         .combout(G_49),
3600         .datain(GND),
3601         .oe(GND),
3602         .outclk(GND),
3603         .outclkena(VCC),
3604         .inclk(GND),
3605         .inclkena(VCC),
3606         .areset(GND),
3607         .sreset(GND)
3608 );
3609 defparam clk_pin_in.operation_mode = "input";
3610 // @6:64
3611   stratix_io d_state_clk_out (
3612         .padio(d_state_clk),
3613         .datain(G_49),
3614         .oe(VCC),
3615         .outclk(GND),
3616         .outclkena(VCC),
3617         .inclk(GND),
3618         .inclkena(VCC),
3619         .areset(GND),
3620         .sreset(GND)
3621 );
3622 defparam d_state_clk_out.operation_mode = "output";
3623 // @6:63
3624   stratix_io d_vsync_state_out_0_ (
3625         .padio(d_vsync_state[0]),
3626         .datain(vga_driver_unit_vsync_state[0]),
3627         .oe(VCC),
3628         .outclk(GND),
3629         .outclkena(VCC),
3630         .inclk(GND),
3631         .inclkena(VCC),
3632         .areset(GND),
3633         .sreset(GND)
3634 );
3635 defparam d_vsync_state_out_0_.operation_mode = "output";
3636 // @6:63
3637   stratix_io d_vsync_state_out_1_ (
3638         .padio(d_vsync_state[1]),
3639         .datain(vga_driver_unit_vsync_state[1]),
3640         .oe(VCC),
3641         .outclk(GND),
3642         .outclkena(VCC),
3643         .inclk(GND),
3644         .inclkena(VCC),
3645         .areset(GND),
3646         .sreset(GND)
3647 );
3648 defparam d_vsync_state_out_1_.operation_mode = "output";
3649 // @6:63
3650   stratix_io d_vsync_state_out_2_ (
3651         .padio(d_vsync_state[2]),
3652         .datain(vga_driver_unit_vsync_state[2]),
3653         .oe(VCC),
3654         .outclk(GND),
3655         .outclkena(VCC),
3656         .inclk(GND),
3657         .inclkena(VCC),
3658         .areset(GND),
3659         .sreset(GND)
3660 );
3661 defparam d_vsync_state_out_2_.operation_mode = "output";
3662 // @6:63
3663   stratix_io d_vsync_state_out_3_ (
3664         .padio(d_vsync_state[3]),
3665         .datain(vga_driver_unit_vsync_state[3]),
3666         .oe(VCC),
3667         .outclk(GND),
3668         .outclkena(VCC),
3669         .inclk(GND),
3670         .inclkena(VCC),
3671         .areset(GND),
3672         .sreset(GND)
3673 );
3674 defparam d_vsync_state_out_3_.operation_mode = "output";
3675 // @6:63
3676   stratix_io d_vsync_state_out_4_ (
3677         .padio(d_vsync_state[4]),
3678         .datain(vga_driver_unit_vsync_state[4]),
3679         .oe(VCC),
3680         .outclk(GND),
3681         .outclkena(VCC),
3682         .inclk(GND),
3683         .inclkena(VCC),
3684         .areset(GND),
3685         .sreset(GND)
3686 );
3687 defparam d_vsync_state_out_4_.operation_mode = "output";
3688 // @6:63
3689   stratix_io d_vsync_state_out_5_ (
3690         .padio(d_vsync_state[5]),
3691         .datain(vga_driver_unit_vsync_state[5]),
3692         .oe(VCC),
3693         .outclk(GND),
3694         .outclkena(VCC),
3695         .inclk(GND),
3696         .inclkena(VCC),
3697         .areset(GND),
3698         .sreset(GND)
3699 );
3700 defparam d_vsync_state_out_5_.operation_mode = "output";
3701 // @6:63
3702   stratix_io d_vsync_state_out_6_ (
3703         .padio(d_vsync_state[6]),
3704         .datain(vga_driver_unit_vsync_state[6]),
3705         .oe(VCC),
3706         .outclk(GND),
3707         .outclkena(VCC),
3708         .inclk(GND),
3709         .inclkena(VCC),
3710         .areset(GND),
3711         .sreset(GND)
3712 );
3713 defparam d_vsync_state_out_6_.operation_mode = "output";
3714 // @6:62
3715   stratix_io d_hsync_state_out_0_ (
3716         .padio(d_hsync_state[0]),
3717         .datain(vga_driver_unit_hsync_state[0]),
3718         .oe(VCC),
3719         .outclk(GND),
3720         .outclkena(VCC),
3721         .inclk(GND),
3722         .inclkena(VCC),
3723         .areset(GND),
3724         .sreset(GND)
3725 );
3726 defparam d_hsync_state_out_0_.operation_mode = "output";
3727 // @6:62
3728   stratix_io d_hsync_state_out_1_ (
3729         .padio(d_hsync_state[1]),
3730         .datain(vga_driver_unit_hsync_state[1]),
3731         .oe(VCC),
3732         .outclk(GND),
3733         .outclkena(VCC),
3734         .inclk(GND),
3735         .inclkena(VCC),
3736         .areset(GND),
3737         .sreset(GND)
3738 );
3739 defparam d_hsync_state_out_1_.operation_mode = "output";
3740 // @6:62
3741   stratix_io d_hsync_state_out_2_ (
3742         .padio(d_hsync_state[2]),
3743         .datain(vga_driver_unit_hsync_state[2]),
3744         .oe(VCC),
3745         .outclk(GND),
3746         .outclkena(VCC),
3747         .inclk(GND),
3748         .inclkena(VCC),
3749         .areset(GND),
3750         .sreset(GND)
3751 );
3752 defparam d_hsync_state_out_2_.operation_mode = "output";
3753 // @6:62
3754   stratix_io d_hsync_state_out_3_ (
3755         .padio(d_hsync_state[3]),
3756         .datain(vga_driver_unit_hsync_state[3]),
3757         .oe(VCC),
3758         .outclk(GND),
3759         .outclkena(VCC),
3760         .inclk(GND),
3761         .inclkena(VCC),
3762         .areset(GND),
3763         .sreset(GND)
3764 );
3765 defparam d_hsync_state_out_3_.operation_mode = "output";
3766 // @6:62
3767   stratix_io d_hsync_state_out_4_ (
3768         .padio(d_hsync_state[4]),
3769         .datain(vga_driver_unit_hsync_state[4]),
3770         .oe(VCC),
3771         .outclk(GND),
3772         .outclkena(VCC),
3773         .inclk(GND),
3774         .inclkena(VCC),
3775         .areset(GND),
3776         .sreset(GND)
3777 );
3778 defparam d_hsync_state_out_4_.operation_mode = "output";
3779 // @6:62
3780   stratix_io d_hsync_state_out_5_ (
3781         .padio(d_hsync_state[5]),
3782         .datain(vga_driver_unit_hsync_state[5]),
3783         .oe(VCC),
3784         .outclk(GND),
3785         .outclkena(VCC),
3786         .inclk(GND),
3787         .inclkena(VCC),
3788         .areset(GND),
3789         .sreset(GND)
3790 );
3791 defparam d_hsync_state_out_5_.operation_mode = "output";
3792 // @6:62
3793   stratix_io d_hsync_state_out_6_ (
3794         .padio(d_hsync_state[6]),
3795         .datain(vga_driver_unit_hsync_state[6]),
3796         .oe(VCC),
3797         .outclk(GND),
3798         .outclkena(VCC),
3799         .inclk(GND),
3800         .inclkena(VCC),
3801         .areset(GND),
3802         .sreset(GND)
3803 );
3804 defparam d_hsync_state_out_6_.operation_mode = "output";
3805 // @6:61
3806   stratix_io d_b_out (
3807         .padio(d_b),
3808         .datain(vga_control_unit_b),
3809         .oe(VCC),
3810         .outclk(GND),
3811         .outclkena(VCC),
3812         .inclk(GND),
3813         .inclkena(VCC),
3814         .areset(GND),
3815         .sreset(GND)
3816 );
3817 defparam d_b_out.operation_mode = "output";
3818 // @6:61
3819   stratix_io d_g_out (
3820         .padio(d_g),
3821         .datain(vga_control_unit_g),
3822         .oe(VCC),
3823         .outclk(GND),
3824         .outclkena(VCC),
3825         .inclk(GND),
3826         .inclkena(VCC),
3827         .areset(GND),
3828         .sreset(GND)
3829 );
3830 defparam d_g_out.operation_mode = "output";
3831 // @6:61
3832   stratix_io d_r_out (
3833         .padio(d_r),
3834         .datain(vga_control_unit_r),
3835         .oe(VCC),
3836         .outclk(GND),
3837         .outclkena(VCC),
3838         .inclk(GND),
3839         .inclkena(VCC),
3840         .areset(GND),
3841         .sreset(GND)
3842 );
3843 defparam d_r_out.operation_mode = "output";
3844 // @6:60
3845   stratix_io d_v_enable_out (
3846         .padio(d_v_enable),
3847         .datain(vga_driver_unit_v_enable_sig),
3848         .oe(VCC),
3849         .outclk(GND),
3850         .outclkena(VCC),
3851         .inclk(GND),
3852         .inclkena(VCC),
3853         .areset(GND),
3854         .sreset(GND)
3855 );
3856 defparam d_v_enable_out.operation_mode = "output";
3857 // @6:59
3858   stratix_io d_h_enable_out (
3859         .padio(d_h_enable),
3860         .datain(vga_driver_unit_h_enable_sig),
3861         .oe(VCC),
3862         .outclk(GND),
3863         .outclkena(VCC),
3864         .inclk(GND),
3865         .inclkena(VCC),
3866         .areset(GND),
3867         .sreset(GND)
3868 );
3869 defparam d_h_enable_out.operation_mode = "output";
3870 // @6:58
3871   stratix_io d_set_vsync_counter_out (
3872         .padio(d_set_vsync_counter),
3873         .datain(vga_driver_unit_d_set_vsync_counter),
3874         .oe(VCC),
3875         .outclk(GND),
3876         .outclkena(VCC),
3877         .inclk(GND),
3878         .inclkena(VCC),
3879         .areset(GND),
3880         .sreset(GND)
3881 );
3882 defparam d_set_vsync_counter_out.operation_mode = "output";
3883 // @6:58
3884   stratix_io d_set_hsync_counter_out (
3885         .padio(d_set_hsync_counter),
3886         .datain(vga_driver_unit_d_set_hsync_counter),
3887         .oe(VCC),
3888         .outclk(GND),
3889         .outclkena(VCC),
3890         .inclk(GND),
3891         .inclkena(VCC),
3892         .areset(GND),
3893         .sreset(GND)
3894 );
3895 defparam d_set_hsync_counter_out.operation_mode = "output";
3896 // @6:57
3897   stratix_io d_vsync_counter_out_9_ (
3898         .padio(d_vsync_counter[9]),
3899         .datain(vga_driver_unit_vsync_counter[9]),
3900         .oe(VCC),
3901         .outclk(GND),
3902         .outclkena(VCC),
3903         .inclk(GND),
3904         .inclkena(VCC),
3905         .areset(GND),
3906         .sreset(GND)
3907 );
3908 defparam d_vsync_counter_out_9_.operation_mode = "output";
3909 // @6:57
3910   stratix_io d_vsync_counter_out_8_ (
3911         .padio(d_vsync_counter[8]),
3912         .datain(vga_driver_unit_vsync_counter[8]),
3913         .oe(VCC),
3914         .outclk(GND),
3915         .outclkena(VCC),
3916         .inclk(GND),
3917         .inclkena(VCC),
3918         .areset(GND),
3919         .sreset(GND)
3920 );
3921 defparam d_vsync_counter_out_8_.operation_mode = "output";
3922 // @6:57
3923   stratix_io d_vsync_counter_out_7_ (
3924         .padio(d_vsync_counter[7]),
3925         .datain(vga_driver_unit_vsync_counter[7]),
3926         .oe(VCC),
3927         .outclk(GND),
3928         .outclkena(VCC),
3929         .inclk(GND),
3930         .inclkena(VCC),
3931         .areset(GND),
3932         .sreset(GND)
3933 );
3934 defparam d_vsync_counter_out_7_.operation_mode = "output";
3935 // @6:57
3936   stratix_io d_vsync_counter_out_6_ (
3937         .padio(d_vsync_counter[6]),
3938         .datain(vga_driver_unit_vsync_counter[6]),
3939         .oe(VCC),
3940         .outclk(GND),
3941         .outclkena(VCC),
3942         .inclk(GND),
3943         .inclkena(VCC),
3944         .areset(GND),
3945         .sreset(GND)
3946 );
3947 defparam d_vsync_counter_out_6_.operation_mode = "output";
3948 // @6:57
3949   stratix_io d_vsync_counter_out_5_ (
3950         .padio(d_vsync_counter[5]),
3951         .datain(vga_driver_unit_vsync_counter[5]),
3952         .oe(VCC),
3953         .outclk(GND),
3954         .outclkena(VCC),
3955         .inclk(GND),
3956         .inclkena(VCC),
3957         .areset(GND),
3958         .sreset(GND)
3959 );
3960 defparam d_vsync_counter_out_5_.operation_mode = "output";
3961 // @6:57
3962   stratix_io d_vsync_counter_out_4_ (
3963         .padio(d_vsync_counter[4]),
3964         .datain(vga_driver_unit_vsync_counter[4]),
3965         .oe(VCC),
3966         .outclk(GND),
3967         .outclkena(VCC),
3968         .inclk(GND),
3969         .inclkena(VCC),
3970         .areset(GND),
3971         .sreset(GND)
3972 );
3973 defparam d_vsync_counter_out_4_.operation_mode = "output";
3974 // @6:57
3975   stratix_io d_vsync_counter_out_3_ (
3976         .padio(d_vsync_counter[3]),
3977         .datain(vga_driver_unit_vsync_counter[3]),
3978         .oe(VCC),
3979         .outclk(GND),
3980         .outclkena(VCC),
3981         .inclk(GND),
3982         .inclkena(VCC),
3983         .areset(GND),
3984         .sreset(GND)
3985 );
3986 defparam d_vsync_counter_out_3_.operation_mode = "output";
3987 // @6:57
3988   stratix_io d_vsync_counter_out_2_ (
3989         .padio(d_vsync_counter[2]),
3990         .datain(vga_driver_unit_vsync_counter[2]),
3991         .oe(VCC),
3992         .outclk(GND),
3993         .outclkena(VCC),
3994         .inclk(GND),
3995         .inclkena(VCC),
3996         .areset(GND),
3997         .sreset(GND)
3998 );
3999 defparam d_vsync_counter_out_2_.operation_mode = "output";
4000 // @6:57
4001   stratix_io d_vsync_counter_out_1_ (
4002         .padio(d_vsync_counter[1]),
4003         .datain(vga_driver_unit_vsync_counter[1]),
4004         .oe(VCC),
4005         .outclk(GND),
4006         .outclkena(VCC),
4007         .inclk(GND),
4008         .inclkena(VCC),
4009         .areset(GND),
4010         .sreset(GND)
4011 );
4012 defparam d_vsync_counter_out_1_.operation_mode = "output";
4013 // @6:57
4014   stratix_io d_vsync_counter_out_0_ (
4015         .padio(d_vsync_counter[0]),
4016         .datain(vga_driver_unit_vsync_counter[0]),
4017         .oe(VCC),
4018         .outclk(GND),
4019         .outclkena(VCC),
4020         .inclk(GND),
4021         .inclkena(VCC),
4022         .areset(GND),
4023         .sreset(GND)
4024 );
4025 defparam d_vsync_counter_out_0_.operation_mode = "output";
4026 // @6:56
4027   stratix_io d_hsync_counter_out_9_ (
4028         .padio(d_hsync_counter[9]),
4029         .datain(vga_driver_unit_hsync_counter[9]),
4030         .oe(VCC),
4031         .outclk(GND),
4032         .outclkena(VCC),
4033         .inclk(GND),
4034         .inclkena(VCC),
4035         .areset(GND),
4036         .sreset(GND)
4037 );
4038 defparam d_hsync_counter_out_9_.operation_mode = "output";
4039 // @6:56
4040   stratix_io d_hsync_counter_out_8_ (
4041         .padio(d_hsync_counter[8]),
4042         .datain(vga_driver_unit_hsync_counter[8]),
4043         .oe(VCC),
4044         .outclk(GND),
4045         .outclkena(VCC),
4046         .inclk(GND),
4047         .inclkena(VCC),
4048         .areset(GND),
4049         .sreset(GND)
4050 );
4051 defparam d_hsync_counter_out_8_.operation_mode = "output";
4052 // @6:56
4053   stratix_io d_hsync_counter_out_7_ (
4054         .padio(d_hsync_counter[7]),
4055         .datain(vga_driver_unit_hsync_counter[7]),
4056         .oe(VCC),
4057         .outclk(GND),
4058         .outclkena(VCC),
4059         .inclk(GND),
4060         .inclkena(VCC),
4061         .areset(GND),
4062         .sreset(GND)
4063 );
4064 defparam d_hsync_counter_out_7_.operation_mode = "output";
4065 // @6:56
4066   stratix_io d_hsync_counter_out_6_ (
4067         .padio(d_hsync_counter[6]),
4068         .datain(vga_driver_unit_hsync_counter[6]),
4069         .oe(VCC),
4070         .outclk(GND),
4071         .outclkena(VCC),
4072         .inclk(GND),
4073         .inclkena(VCC),
4074         .areset(GND),
4075         .sreset(GND)
4076 );
4077 defparam d_hsync_counter_out_6_.operation_mode = "output";
4078 // @6:56
4079   stratix_io d_hsync_counter_out_5_ (
4080         .padio(d_hsync_counter[5]),
4081         .datain(vga_driver_unit_hsync_counter[5]),
4082         .oe(VCC),
4083         .outclk(GND),
4084         .outclkena(VCC),
4085         .inclk(GND),
4086         .inclkena(VCC),
4087         .areset(GND),
4088         .sreset(GND)
4089 );
4090 defparam d_hsync_counter_out_5_.operation_mode = "output";
4091 // @6:56
4092   stratix_io d_hsync_counter_out_4_ (
4093         .padio(d_hsync_counter[4]),
4094         .datain(vga_driver_unit_hsync_counter[4]),
4095         .oe(VCC),
4096         .outclk(GND),
4097         .outclkena(VCC),
4098         .inclk(GND),
4099         .inclkena(VCC),
4100         .areset(GND),
4101         .sreset(GND)
4102 );
4103 defparam d_hsync_counter_out_4_.operation_mode = "output";
4104 // @6:56
4105   stratix_io d_hsync_counter_out_3_ (
4106         .padio(d_hsync_counter[3]),
4107         .datain(vga_driver_unit_hsync_counter[3]),
4108         .oe(VCC),
4109         .outclk(GND),
4110         .outclkena(VCC),
4111         .inclk(GND),
4112         .inclkena(VCC),
4113         .areset(GND),
4114         .sreset(GND)
4115 );
4116 defparam d_hsync_counter_out_3_.operation_mode = "output";
4117 // @6:56
4118   stratix_io d_hsync_counter_out_2_ (
4119         .padio(d_hsync_counter[2]),
4120         .datain(vga_driver_unit_hsync_counter[2]),
4121         .oe(VCC),
4122         .outclk(GND),
4123         .outclkena(VCC),
4124         .inclk(GND),
4125         .inclkena(VCC),
4126         .areset(GND),
4127         .sreset(GND)
4128 );
4129 defparam d_hsync_counter_out_2_.operation_mode = "output";
4130 // @6:56
4131   stratix_io d_hsync_counter_out_1_ (
4132         .padio(d_hsync_counter[1]),
4133         .datain(vga_driver_unit_hsync_counter[1]),
4134         .oe(VCC),
4135         .outclk(GND),
4136         .outclkena(VCC),
4137         .inclk(GND),
4138         .inclkena(VCC),
4139         .areset(GND),
4140         .sreset(GND)
4141 );
4142 defparam d_hsync_counter_out_1_.operation_mode = "output";
4143 // @6:56
4144   stratix_io d_hsync_counter_out_0_ (
4145         .padio(d_hsync_counter[0]),
4146         .datain(vga_driver_unit_hsync_counter[0]),
4147         .oe(VCC),
4148         .outclk(GND),
4149         .outclkena(VCC),
4150         .inclk(GND),
4151         .inclkena(VCC),
4152         .areset(GND),
4153         .sreset(GND)
4154 );
4155 defparam d_hsync_counter_out_0_.operation_mode = "output";
4156 // @6:55
4157   stratix_io d_set_line_counter_out (
4158         .padio(d_set_line_counter),
4159         .datain(vga_driver_unit_vsync_state[1]),
4160         .oe(VCC),
4161         .outclk(GND),
4162         .outclkena(VCC),
4163         .inclk(GND),
4164         .inclkena(VCC),
4165         .areset(GND),
4166         .sreset(GND)
4167 );
4168 defparam d_set_line_counter_out.operation_mode = "output";
4169 // @6:55
4170   stratix_io d_set_column_counter_out (
4171         .padio(d_set_column_counter),
4172         .datain(vga_driver_unit_hsync_state[1]),
4173         .oe(VCC),
4174         .outclk(GND),
4175         .outclkena(VCC),
4176         .inclk(GND),
4177         .inclkena(VCC),
4178         .areset(GND),
4179         .sreset(GND)
4180 );
4181 defparam d_set_column_counter_out.operation_mode = "output";
4182 // @6:54
4183   stratix_io d_line_counter_out_8_ (
4184         .padio(d_line_counter[8]),
4185         .datain(vga_driver_unit_line_counter_sig[8]),
4186         .oe(VCC),
4187         .outclk(GND),
4188         .outclkena(VCC),
4189         .inclk(GND),
4190         .inclkena(VCC),
4191         .areset(GND),
4192         .sreset(GND)
4193 );
4194 defparam d_line_counter_out_8_.operation_mode = "output";
4195 // @6:54
4196   stratix_io d_line_counter_out_7_ (
4197         .padio(d_line_counter[7]),
4198         .datain(vga_driver_unit_line_counter_sig[7]),
4199         .oe(VCC),
4200         .outclk(GND),
4201         .outclkena(VCC),
4202         .inclk(GND),
4203         .inclkena(VCC),
4204         .areset(GND),
4205         .sreset(GND)
4206 );
4207 defparam d_line_counter_out_7_.operation_mode = "output";
4208 // @6:54
4209   stratix_io d_line_counter_out_6_ (
4210         .padio(d_line_counter[6]),
4211         .datain(vga_driver_unit_line_counter_sig[6]),
4212         .oe(VCC),
4213         .outclk(GND),
4214         .outclkena(VCC),
4215         .inclk(GND),
4216         .inclkena(VCC),
4217         .areset(GND),
4218         .sreset(GND)
4219 );
4220 defparam d_line_counter_out_6_.operation_mode = "output";
4221 // @6:54
4222   stratix_io d_line_counter_out_5_ (
4223         .padio(d_line_counter[5]),
4224         .datain(vga_driver_unit_line_counter_sig[5]),
4225         .oe(VCC),
4226         .outclk(GND),
4227         .outclkena(VCC),
4228         .inclk(GND),
4229         .inclkena(VCC),
4230         .areset(GND),
4231         .sreset(GND)
4232 );
4233 defparam d_line_counter_out_5_.operation_mode = "output";
4234 // @6:54
4235   stratix_io d_line_counter_out_4_ (
4236         .padio(d_line_counter[4]),
4237         .datain(vga_driver_unit_line_counter_sig[4]),
4238         .oe(VCC),
4239         .outclk(GND),
4240         .outclkena(VCC),
4241         .inclk(GND),
4242         .inclkena(VCC),
4243         .areset(GND),
4244         .sreset(GND)
4245 );
4246 defparam d_line_counter_out_4_.operation_mode = "output";
4247 // @6:54
4248   stratix_io d_line_counter_out_3_ (
4249         .padio(d_line_counter[3]),
4250         .datain(vga_driver_unit_line_counter_sig[3]),
4251         .oe(VCC),
4252         .outclk(GND),
4253         .outclkena(VCC),
4254         .inclk(GND),
4255         .inclkena(VCC),
4256         .areset(GND),
4257         .sreset(GND)
4258 );
4259 defparam d_line_counter_out_3_.operation_mode = "output";
4260 // @6:54
4261   stratix_io d_line_counter_out_2_ (
4262         .padio(d_line_counter[2]),
4263         .datain(vga_driver_unit_line_counter_sig[2]),
4264         .oe(VCC),
4265         .outclk(GND),
4266         .outclkena(VCC),
4267         .inclk(GND),
4268         .inclkena(VCC),
4269         .areset(GND),
4270         .sreset(GND)
4271 );
4272 defparam d_line_counter_out_2_.operation_mode = "output";
4273 // @6:54
4274   stratix_io d_line_counter_out_1_ (
4275         .padio(d_line_counter[1]),
4276         .datain(vga_driver_unit_line_counter_sig[1]),
4277         .oe(VCC),
4278         .outclk(GND),
4279         .outclkena(VCC),
4280         .inclk(GND),
4281         .inclkena(VCC),
4282         .areset(GND),
4283         .sreset(GND)
4284 );
4285 defparam d_line_counter_out_1_.operation_mode = "output";
4286 // @6:54
4287   stratix_io d_line_counter_out_0_ (
4288         .padio(d_line_counter[0]),
4289         .datain(vga_driver_unit_line_counter_sig[0]),
4290         .oe(VCC),
4291         .outclk(GND),
4292         .outclkena(VCC),
4293         .inclk(GND),
4294         .inclkena(VCC),
4295         .areset(GND),
4296         .sreset(GND)
4297 );
4298 defparam d_line_counter_out_0_.operation_mode = "output";
4299 // @6:53
4300   stratix_io d_column_counter_out_9_ (
4301         .padio(d_column_counter[9]),
4302         .datain(vga_driver_unit_column_counter_sig[9]),
4303         .oe(VCC),
4304         .outclk(GND),
4305         .outclkena(VCC),
4306         .inclk(GND),
4307         .inclkena(VCC),
4308         .areset(GND),
4309         .sreset(GND)
4310 );
4311 defparam d_column_counter_out_9_.operation_mode = "output";
4312 // @6:53
4313   stratix_io d_column_counter_out_8_ (
4314         .padio(d_column_counter[8]),
4315         .datain(vga_driver_unit_column_counter_sig[8]),
4316         .oe(VCC),
4317         .outclk(GND),
4318         .outclkena(VCC),
4319         .inclk(GND),
4320         .inclkena(VCC),
4321         .areset(GND),
4322         .sreset(GND)
4323 );
4324 defparam d_column_counter_out_8_.operation_mode = "output";
4325 // @6:53
4326   stratix_io d_column_counter_out_7_ (
4327         .padio(d_column_counter[7]),
4328         .datain(vga_driver_unit_column_counter_sig[7]),
4329         .oe(VCC),
4330         .outclk(GND),
4331         .outclkena(VCC),
4332         .inclk(GND),
4333         .inclkena(VCC),
4334         .areset(GND),
4335         .sreset(GND)
4336 );
4337 defparam d_column_counter_out_7_.operation_mode = "output";
4338 // @6:53
4339   stratix_io d_column_counter_out_6_ (
4340         .padio(d_column_counter[6]),
4341         .datain(vga_driver_unit_column_counter_sig[6]),
4342         .oe(VCC),
4343         .outclk(GND),
4344         .outclkena(VCC),
4345         .inclk(GND),
4346         .inclkena(VCC),
4347         .areset(GND),
4348         .sreset(GND)
4349 );
4350 defparam d_column_counter_out_6_.operation_mode = "output";
4351 // @6:53
4352   stratix_io d_column_counter_out_5_ (
4353         .padio(d_column_counter[5]),
4354         .datain(vga_driver_unit_column_counter_sig[5]),
4355         .oe(VCC),
4356         .outclk(GND),
4357         .outclkena(VCC),
4358         .inclk(GND),
4359         .inclkena(VCC),
4360         .areset(GND),
4361         .sreset(GND)
4362 );
4363 defparam d_column_counter_out_5_.operation_mode = "output";
4364 // @6:53
4365   stratix_io d_column_counter_out_4_ (
4366         .padio(d_column_counter[4]),
4367         .datain(vga_driver_unit_column_counter_sig[4]),
4368         .oe(VCC),
4369         .outclk(GND),
4370         .outclkena(VCC),
4371         .inclk(GND),
4372         .inclkena(VCC),
4373         .areset(GND),
4374         .sreset(GND)
4375 );
4376 defparam d_column_counter_out_4_.operation_mode = "output";
4377 // @6:53
4378   stratix_io d_column_counter_out_3_ (
4379         .padio(d_column_counter[3]),
4380         .datain(vga_driver_unit_column_counter_sig[3]),
4381         .oe(VCC),
4382         .outclk(GND),
4383         .outclkena(VCC),
4384         .inclk(GND),
4385         .inclkena(VCC),
4386         .areset(GND),
4387         .sreset(GND)
4388 );
4389 defparam d_column_counter_out_3_.operation_mode = "output";
4390 // @6:53
4391   stratix_io d_column_counter_out_2_ (
4392         .padio(d_column_counter[2]),
4393         .datain(vga_driver_unit_column_counter_sig[2]),
4394         .oe(VCC),
4395         .outclk(GND),
4396         .outclkena(VCC),
4397         .inclk(GND),
4398         .inclkena(VCC),
4399         .areset(GND),
4400         .sreset(GND)
4401 );
4402 defparam d_column_counter_out_2_.operation_mode = "output";
4403 // @6:53
4404   stratix_io d_column_counter_out_1_ (
4405         .padio(d_column_counter[1]),
4406         .datain(vga_driver_unit_column_counter_sig[1]),
4407         .oe(VCC),
4408         .outclk(GND),
4409         .outclkena(VCC),
4410         .inclk(GND),
4411         .inclkena(VCC),
4412         .areset(GND),
4413         .sreset(GND)
4414 );
4415 defparam d_column_counter_out_1_.operation_mode = "output";
4416 // @6:53
4417   stratix_io d_column_counter_out_0_ (
4418         .padio(d_column_counter[0]),
4419         .datain(vga_driver_unit_column_counter_sig[0]),
4420         .oe(VCC),
4421         .outclk(GND),
4422         .outclkena(VCC),
4423         .inclk(GND),
4424         .inclkena(VCC),
4425         .areset(GND),
4426         .sreset(GND)
4427 );
4428 defparam d_column_counter_out_0_.operation_mode = "output";
4429 // @6:52
4430   stratix_io d_vsync_out (
4431         .padio(d_vsync),
4432         .datain(vga_driver_unit_v_sync),
4433         .oe(VCC),
4434         .outclk(GND),
4435         .outclkena(VCC),
4436         .inclk(GND),
4437         .inclkena(VCC),
4438         .areset(GND),
4439         .sreset(GND)
4440 );
4441 defparam d_vsync_out.operation_mode = "output";
4442 // @6:52
4443   stratix_io d_hsync_out (
4444         .padio(d_hsync),
4445         .datain(vga_driver_unit_h_sync),
4446         .oe(VCC),
4447         .outclk(GND),
4448         .outclkena(VCC),
4449         .inclk(GND),
4450         .inclkena(VCC),
4451         .areset(GND),
4452         .sreset(GND)
4453 );
4454 defparam d_hsync_out.operation_mode = "output";
4455 // @6:50
4456   stratix_io seven_seg_pin_tri_13_ (
4457         .padio(seven_seg_pin[13]),
4458         .datain(VCC),
4459         .oe(VCC),
4460         .outclk(GND),
4461         .outclkena(VCC),
4462         .inclk(GND),
4463         .inclkena(VCC),
4464         .areset(GND),
4465         .sreset(GND)
4466 );
4467 defparam seven_seg_pin_tri_13_.operation_mode = "output";
4468 // @6:50
4469   stratix_io seven_seg_pin_out_12_ (
4470         .padio(seven_seg_pin[12]),
4471         .datain(DELAY_RESET_next_un6_dly_counter_0_x),
4472         .oe(VCC),
4473         .outclk(GND),
4474         .outclkena(VCC),
4475         .inclk(GND),
4476         .inclkena(VCC),
4477         .areset(GND),
4478         .sreset(GND)
4479 );
4480 defparam seven_seg_pin_out_12_.operation_mode = "output";
4481 // @6:50
4482   stratix_io seven_seg_pin_out_11_ (
4483         .padio(seven_seg_pin[11]),
4484         .datain(DELAY_RESET_next_un6_dly_counter_0_x),
4485         .oe(VCC),
4486         .outclk(GND),
4487         .outclkena(VCC),
4488         .inclk(GND),
4489         .inclkena(VCC),
4490         .areset(GND),
4491         .sreset(GND)
4492 );
4493 defparam seven_seg_pin_out_11_.operation_mode = "output";
4494 // @6:50
4495   stratix_io seven_seg_pin_out_10_ (
4496         .padio(seven_seg_pin[10]),
4497         .datain(DELAY_RESET_next_un6_dly_counter_0_x),
4498         .oe(VCC),
4499         .outclk(GND),
4500         .outclkena(VCC),
4501         .inclk(GND),
4502         .inclkena(VCC),
4503         .areset(GND),
4504         .sreset(GND)
4505 );
4506 defparam seven_seg_pin_out_10_.operation_mode = "output";
4507 // @6:50
4508   stratix_io seven_seg_pin_out_9_ (
4509         .padio(seven_seg_pin[9]),
4510         .datain(DELAY_RESET_next_un6_dly_counter_0_x),
4511         .oe(VCC),
4512         .outclk(GND),
4513         .outclkena(VCC),
4514         .inclk(GND),
4515         .inclkena(VCC),
4516         .areset(GND),
4517         .sreset(GND)
4518 );
4519 defparam seven_seg_pin_out_9_.operation_mode = "output";
4520 // @6:50
4521   stratix_io seven_seg_pin_out_8_ (
4522         .padio(seven_seg_pin[8]),
4523         .datain(DELAY_RESET_next_un6_dly_counter_0_x),
4524         .oe(VCC),
4525         .outclk(GND),
4526         .outclkena(VCC),
4527         .inclk(GND),
4528         .inclkena(VCC),
4529         .areset(GND),
4530         .sreset(GND)
4531 );
4532 defparam seven_seg_pin_out_8_.operation_mode = "output";
4533 // @6:50
4534   stratix_io seven_seg_pin_out_7_ (
4535         .padio(seven_seg_pin[7]),
4536         .datain(DELAY_RESET_next_un6_dly_counter_0_x),
4537         .oe(VCC),
4538         .outclk(GND),
4539         .outclkena(VCC),
4540         .inclk(GND),
4541         .inclkena(VCC),
4542         .areset(GND),
4543         .sreset(GND)
4544 );
4545 defparam seven_seg_pin_out_7_.operation_mode = "output";
4546 // @6:50
4547   stratix_io seven_seg_pin_tri_6_ (
4548         .padio(seven_seg_pin[6]),
4549         .datain(VCC),
4550         .oe(VCC),
4551         .outclk(GND),
4552         .outclkena(VCC),
4553         .inclk(GND),
4554         .inclkena(VCC),
4555         .areset(GND),
4556         .sreset(GND)
4557 );
4558 defparam seven_seg_pin_tri_6_.operation_mode = "output";
4559 // @6:50
4560   stratix_io seven_seg_pin_tri_5_ (
4561         .padio(seven_seg_pin[5]),
4562         .datain(VCC),
4563         .oe(VCC),
4564         .outclk(GND),
4565         .outclkena(VCC),
4566         .inclk(GND),
4567         .inclkena(VCC),
4568         .areset(GND),
4569         .sreset(GND)
4570 );
4571 defparam seven_seg_pin_tri_5_.operation_mode = "output";
4572 // @6:50
4573   stratix_io seven_seg_pin_tri_4_ (
4574         .padio(seven_seg_pin[4]),
4575         .datain(VCC),
4576         .oe(VCC),
4577         .outclk(GND),
4578         .outclkena(VCC),
4579         .inclk(GND),
4580         .inclkena(VCC),
4581         .areset(GND),
4582         .sreset(GND)
4583 );
4584 defparam seven_seg_pin_tri_4_.operation_mode = "output";
4585 // @6:50
4586   stratix_io seven_seg_pin_tri_3_ (
4587         .padio(seven_seg_pin[3]),
4588         .datain(VCC),
4589         .oe(VCC),
4590         .outclk(GND),
4591         .outclkena(VCC),
4592         .inclk(GND),
4593         .inclkena(VCC),
4594         .areset(GND),
4595         .sreset(GND)
4596 );
4597 defparam seven_seg_pin_tri_3_.operation_mode = "output";
4598 // @6:50
4599   stratix_io seven_seg_pin_out_2_ (
4600         .padio(seven_seg_pin[2]),
4601         .datain(DELAY_RESET_next_un6_dly_counter_0_x),
4602         .oe(VCC),
4603         .outclk(GND),
4604         .outclkena(VCC),
4605         .inclk(GND),
4606         .inclkena(VCC),
4607         .areset(GND),
4608         .sreset(GND)
4609 );
4610 defparam seven_seg_pin_out_2_.operation_mode = "output";
4611 // @6:50
4612   stratix_io seven_seg_pin_out_1_ (
4613         .padio(seven_seg_pin[1]),
4614         .datain(DELAY_RESET_next_un6_dly_counter_0_x),
4615         .oe(VCC),
4616         .outclk(GND),
4617         .outclkena(VCC),
4618         .inclk(GND),
4619         .inclkena(VCC),
4620         .areset(GND),
4621         .sreset(GND)
4622 );
4623 defparam seven_seg_pin_out_1_.operation_mode = "output";
4624 // @6:50
4625   stratix_io seven_seg_pin_tri_0_ (
4626         .padio(seven_seg_pin[0]),
4627         .datain(VCC),
4628         .oe(VCC),
4629         .outclk(GND),
4630         .outclkena(VCC),
4631         .inclk(GND),
4632         .inclkena(VCC),
4633         .areset(GND),
4634         .sreset(GND)
4635 );
4636 defparam seven_seg_pin_tri_0_.operation_mode = "output";
4637 // @6:48
4638   stratix_io vsync_pin_out (
4639         .padio(vsync_pin),
4640         .datain(vga_driver_unit_v_sync),
4641         .oe(VCC),
4642         .outclk(GND),
4643         .outclkena(VCC),
4644         .inclk(GND),
4645         .inclkena(VCC),
4646         .areset(GND),
4647         .sreset(GND)
4648 );
4649 defparam vsync_pin_out.operation_mode = "output";
4650 // @6:47
4651   stratix_io hsync_pin_out (
4652         .padio(hsync_pin),
4653         .datain(vga_driver_unit_h_sync),
4654         .oe(VCC),
4655         .outclk(GND),
4656         .outclkena(VCC),
4657         .inclk(GND),
4658         .inclkena(VCC),
4659         .areset(GND),
4660         .sreset(GND)
4661 );
4662 defparam hsync_pin_out.operation_mode = "output";
4663 // @6:46
4664   stratix_io b1_pin_out (
4665         .padio(b1_pin),
4666         .datain(vga_control_unit_b),
4667         .oe(VCC),
4668         .outclk(GND),
4669         .outclkena(VCC),
4670         .inclk(GND),
4671         .inclkena(VCC),
4672         .areset(GND),
4673         .sreset(GND)
4674 );
4675 defparam b1_pin_out.operation_mode = "output";
4676 // @6:46
4677   stratix_io b0_pin_out (
4678         .padio(b0_pin),
4679         .datain(vga_control_unit_b),
4680         .oe(VCC),
4681         .outclk(GND),
4682         .outclkena(VCC),
4683         .inclk(GND),
4684         .inclkena(VCC),
4685         .areset(GND),
4686         .sreset(GND)
4687 );
4688 defparam b0_pin_out.operation_mode = "output";
4689 // @6:45
4690   stratix_io g2_pin_out (
4691         .padio(g2_pin),
4692         .datain(vga_control_unit_g),
4693         .oe(VCC),
4694         .outclk(GND),
4695         .outclkena(VCC),
4696         .inclk(GND),
4697         .inclkena(VCC),
4698         .areset(GND),
4699         .sreset(GND)
4700 );
4701 defparam g2_pin_out.operation_mode = "output";
4702 // @6:45
4703   stratix_io g1_pin_out (
4704         .padio(g1_pin),
4705         .datain(vga_control_unit_g),
4706         .oe(VCC),
4707         .outclk(GND),
4708         .outclkena(VCC),
4709         .inclk(GND),
4710         .inclkena(VCC),
4711         .areset(GND),
4712         .sreset(GND)
4713 );
4714 defparam g1_pin_out.operation_mode = "output";
4715 // @6:45
4716   stratix_io g0_pin_out (
4717         .padio(g0_pin),
4718         .datain(vga_control_unit_g),
4719         .oe(VCC),
4720         .outclk(GND),
4721         .outclkena(VCC),
4722         .inclk(GND),
4723         .inclkena(VCC),
4724         .areset(GND),
4725         .sreset(GND)
4726 );
4727 defparam g0_pin_out.operation_mode = "output";
4728 // @6:44
4729   stratix_io r2_pin_out (
4730         .padio(r2_pin),
4731         .datain(vga_control_unit_r),
4732         .oe(VCC),
4733         .outclk(GND),
4734         .outclkena(VCC),
4735         .inclk(GND),
4736         .inclkena(VCC),
4737         .areset(GND),
4738         .sreset(GND)
4739 );
4740 defparam r2_pin_out.operation_mode = "output";
4741 // @6:44
4742   stratix_io r1_pin_out (
4743         .padio(r1_pin),
4744         .datain(vga_control_unit_r),
4745         .oe(VCC),
4746         .outclk(GND),
4747         .outclkena(VCC),
4748         .inclk(GND),
4749         .inclkena(VCC),
4750         .areset(GND),
4751         .sreset(GND)
4752 );
4753 defparam r1_pin_out.operation_mode = "output";
4754 // @6:44
4755   stratix_io r0_pin_out (
4756         .padio(r0_pin),
4757         .datain(vga_control_unit_r),
4758         .oe(VCC),
4759         .outclk(GND),
4760         .outclkena(VCC),
4761         .inclk(GND),
4762         .inclkena(VCC),
4763         .areset(GND),
4764         .sreset(GND)
4765 );
4766 defparam r0_pin_out.operation_mode = "output";
4767 //@6:41
4768 // @10:159
4769   vga_driver vga_driver_unit (
4770         .line_counter_sig_0(vga_driver_unit_line_counter_sig[0]),
4771         .line_counter_sig_1(vga_driver_unit_line_counter_sig[1]),
4772         .line_counter_sig_2(vga_driver_unit_line_counter_sig[2]),
4773         .line_counter_sig_3(vga_driver_unit_line_counter_sig[3]),
4774         .line_counter_sig_4(vga_driver_unit_line_counter_sig[4]),
4775         .line_counter_sig_5(vga_driver_unit_line_counter_sig[5]),
4776         .line_counter_sig_6(vga_driver_unit_line_counter_sig[6]),
4777         .line_counter_sig_7(vga_driver_unit_line_counter_sig[7]),
4778         .line_counter_sig_8(vga_driver_unit_line_counter_sig[8]),
4779         .dly_counter_1(dly_counter[1]),
4780         .dly_counter_0(dly_counter[0]),
4781         .vsync_state_2(vga_driver_unit_vsync_state[2]),
4782         .vsync_state_5(vga_driver_unit_vsync_state[5]),
4783         .vsync_state_3(vga_driver_unit_vsync_state[3]),
4784         .vsync_state_6(vga_driver_unit_vsync_state[6]),
4785         .vsync_state_4(vga_driver_unit_vsync_state[4]),
4786         .vsync_state_1(vga_driver_unit_vsync_state[1]),
4787         .vsync_state_0(vga_driver_unit_vsync_state[0]),
4788         .hsync_state_2(vga_driver_unit_hsync_state[2]),
4789         .hsync_state_4(vga_driver_unit_hsync_state[4]),
4790         .hsync_state_0(vga_driver_unit_hsync_state[0]),
4791         .hsync_state_5(vga_driver_unit_hsync_state[5]),
4792         .hsync_state_1(vga_driver_unit_hsync_state[1]),
4793         .hsync_state_3(vga_driver_unit_hsync_state[3]),
4794         .hsync_state_6(vga_driver_unit_hsync_state[6]),
4795         .column_counter_sig_0(vga_driver_unit_column_counter_sig[0]),
4796         .column_counter_sig_1(vga_driver_unit_column_counter_sig[1]),
4797         .column_counter_sig_2(vga_driver_unit_column_counter_sig[2]),
4798         .column_counter_sig_3(vga_driver_unit_column_counter_sig[3]),
4799         .column_counter_sig_4(vga_driver_unit_column_counter_sig[4]),
4800         .column_counter_sig_5(vga_driver_unit_column_counter_sig[5]),
4801         .column_counter_sig_6(vga_driver_unit_column_counter_sig[6]),
4802         .column_counter_sig_7(vga_driver_unit_column_counter_sig[7]),
4803         .column_counter_sig_8(vga_driver_unit_column_counter_sig[8]),
4804         .column_counter_sig_9(vga_driver_unit_column_counter_sig[9]),
4805         .vsync_counter_9(vga_driver_unit_vsync_counter[9]),
4806         .vsync_counter_8(vga_driver_unit_vsync_counter[8]),
4807         .vsync_counter_7(vga_driver_unit_vsync_counter[7]),
4808         .vsync_counter_6(vga_driver_unit_vsync_counter[6]),
4809         .vsync_counter_5(vga_driver_unit_vsync_counter[5]),
4810         .vsync_counter_4(vga_driver_unit_vsync_counter[4]),
4811         .vsync_counter_3(vga_driver_unit_vsync_counter[3]),
4812         .vsync_counter_2(vga_driver_unit_vsync_counter[2]),
4813         .vsync_counter_1(vga_driver_unit_vsync_counter[1]),
4814         .vsync_counter_0(vga_driver_unit_vsync_counter[0]),
4815         .hsync_counter_9(vga_driver_unit_hsync_counter[9]),
4816         .hsync_counter_8(vga_driver_unit_hsync_counter[8]),
4817         .hsync_counter_7(vga_driver_unit_hsync_counter[7]),
4818         .hsync_counter_6(vga_driver_unit_hsync_counter[6]),
4819         .hsync_counter_5(vga_driver_unit_hsync_counter[5]),
4820         .hsync_counter_4(vga_driver_unit_hsync_counter[4]),
4821         .hsync_counter_3(vga_driver_unit_hsync_counter[3]),
4822         .hsync_counter_2(vga_driver_unit_hsync_counter[2]),
4823         .hsync_counter_1(vga_driver_unit_hsync_counter[1]),
4824         .hsync_counter_0(vga_driver_unit_hsync_counter[0]),
4825         .d_set_vsync_counter(vga_driver_unit_d_set_vsync_counter),
4826         .un10_column_counter_siglt6_1(vga_driver_unit_COLUMN_COUNT_next_un10_column_counter_siglt6_1),
4827         .un10_column_counter_siglt6_3(vga_driver_unit_COLUMN_COUNT_next_un10_column_counter_siglt6_3),
4828         .v_sync(vga_driver_unit_v_sync),
4829         .h_sync(vga_driver_unit_h_sync),
4830         .h_enable_sig(vga_driver_unit_h_enable_sig),
4831         .v_enable_sig(vga_driver_unit_v_enable_sig),
4832         .reset_pin_c(reset_pin_c),
4833         .un6_dly_counter_0_x(DELAY_RESET_next_un6_dly_counter_0_x),
4834         .d_set_hsync_counter(vga_driver_unit_d_set_hsync_counter),
4835         .clk_pin_c(G_49)
4836 );
4837 // @10:184
4838   vga_control vga_control_unit (
4839         .column_counter_sig_1(vga_driver_unit_column_counter_sig[3]),
4840         .column_counter_sig_7(vga_driver_unit_column_counter_sig[9]),
4841         .column_counter_sig_2(vga_driver_unit_column_counter_sig[4]),
4842         .column_counter_sig_0(vga_driver_unit_column_counter_sig[2]),
4843         .column_counter_sig_4(vga_driver_unit_column_counter_sig[6]),
4844         .column_counter_sig_3(vga_driver_unit_column_counter_sig[5]),
4845         .column_counter_sig_5(vga_driver_unit_column_counter_sig[7]),
4846         .column_counter_sig_6(vga_driver_unit_column_counter_sig[8]),
4847         .h_enable_sig(vga_driver_unit_h_enable_sig),
4848         .v_enable_sig(vga_driver_unit_v_enable_sig),
4849         .un10_column_counter_siglt6_1(vga_driver_unit_COLUMN_COUNT_next_un10_column_counter_siglt6_1),
4850         .g(vga_control_unit_g),
4851         .un10_column_counter_siglt6_3(vga_driver_unit_COLUMN_COUNT_next_un10_column_counter_siglt6_3),
4852         .r(vga_control_unit_r),
4853         .un6_dly_counter_0_x(DELAY_RESET_next_un6_dly_counter_0_x),
4854         .clk_pin_c(G_49),
4855         .b(vga_control_unit_b)
4856 );
4857 endmodule /* vga */
4858