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4er slot (3. bsp fertig)
[dide_16.git] / bsp3 / Designflow / ppr / sim / db / vga.cbx.xml
1 <?xml version="1.0" ?>
2 <LOG_ROOT>
3         <PROJECT NAME="vga">
4         </PROJECT>
5 </LOG_ROOT>
dide laboruebung (ws09)