bsp3/Designflow/ppr/sim/simulation/modelsim/vga.vho

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   2 -- Your use of Altera Corporation's design tools, logic functions
   3 -- and other software and tools, and its AMPP partner logic
   4 -- functions, and any output files from any of the foregoing
   5 -- (including device programming or simulation files), and any
   6 -- associated documentation or information are expressly subject
   7 -- to the terms and conditions of the Altera Program License
   8 -- Subscription Agreement, Altera MegaCore Function License
   9 -- Agreement, or other applicable license agreement, including,
  10 -- without limitation, that your use is for the sole purpose of
  11 -- programming logic devices manufactured by Altera and sold by
  12 -- Altera or its authorized distributors.  Please refer to the
  13 -- applicable agreement for further details.
  14
  15 -- VENDOR "Altera"
  16 -- PROGRAM "Quartus II"
  17 -- VERSION "Version 9.0 Build 132 02/25/2009 SJ Full Version"
  18
  19 -- DATE "10/29/2009 17:00:56"
  20
  21 --
  22 -- Device: Altera EP1S25F672C6 Package FBGA672
  23 --
  24
  25 --
  26 -- This VHDL file should be used for ModelSim-Altera (VHDL) only
  27 --
  28
  29 LIBRARY IEEE, stratix;
  30 USE IEEE.std_logic_1164.all;
  31 USE stratix.stratix_components.all;
  32
  33 ENTITY  vga IS
  34     PORT (
  35         clk_pin : IN std_logic;
  36         reset_pin : IN std_logic;
  37         r0_pin : OUT std_logic;
  38         r1_pin : OUT std_logic;
  39         r2_pin : OUT std_logic;
  40         g0_pin : OUT std_logic;
  41         g1_pin : OUT std_logic;
  42         g2_pin : OUT std_logic;
  43         b0_pin : OUT std_logic;
  44         b1_pin : OUT std_logic;
  45         hsync_pin : OUT std_logic;
  46         vsync_pin : OUT std_logic;
  47         seven_seg_pin : OUT std_logic_vector(13 DOWNTO 0);
  48         d_hsync : OUT std_logic;
  49         d_vsync : OUT std_logic;
  50         d_column_counter : OUT std_logic_vector(9 DOWNTO 0);
  51         d_line_counter : OUT std_logic_vector(8 DOWNTO 0);
  52         d_set_column_counter : OUT std_logic;
  53         d_set_line_counter : OUT std_logic;
  54         d_hsync_counter : OUT std_logic_vector(9 DOWNTO 0);
  55         d_vsync_counter : OUT std_logic_vector(9 DOWNTO 0);
  56         d_set_hsync_counter : OUT std_logic;
  57         d_set_vsync_counter : OUT std_logic;
  58         d_h_enable : OUT std_logic;
  59         d_v_enable : OUT std_logic;
  60         d_r : OUT std_logic;
  61         d_g : OUT std_logic;
  62         d_b : OUT std_logic;
  63         d_hsync_state : OUT std_logic_vector(0 TO 6);
  64         d_vsync_state : OUT std_logic_vector(0 TO 6);
  65         d_state_clk : OUT std_logic
  66         );
  67 END vga;
  68
  69 ARCHITECTURE structure OF vga IS
  70 SIGNAL gnd : std_logic := '0';
  71 SIGNAL vcc : std_logic := '1';
  72 SIGNAL devoe : std_logic := '1';
  73 SIGNAL devclrn : std_logic := '1';
  74 SIGNAL devpor : std_logic := '1';
  75 SIGNAL ww_devoe : std_logic;
  76 SIGNAL ww_devclrn : std_logic;
  77 SIGNAL ww_devpor : std_logic;
  78 SIGNAL ww_clk_pin : std_logic;
  79 SIGNAL ww_reset_pin : std_logic;
  80 SIGNAL ww_r0_pin : std_logic;
  81 SIGNAL ww_r1_pin : std_logic;
  82 SIGNAL ww_r2_pin : std_logic;
  83 SIGNAL ww_g0_pin : std_logic;
  84 SIGNAL ww_g1_pin : std_logic;
  85 SIGNAL ww_g2_pin : std_logic;
  86 SIGNAL ww_b0_pin : std_logic;
  87 SIGNAL ww_b1_pin : std_logic;
  88 SIGNAL ww_hsync_pin : std_logic;
  89 SIGNAL ww_vsync_pin : std_logic;
  90 SIGNAL ww_seven_seg_pin : std_logic_vector(13 DOWNTO 0);
  91 SIGNAL ww_d_hsync : std_logic;
  92 SIGNAL ww_d_vsync : std_logic;
  93 SIGNAL ww_d_column_counter : std_logic_vector(9 DOWNTO 0);
  94 SIGNAL ww_d_line_counter : std_logic_vector(8 DOWNTO 0);
  95 SIGNAL ww_d_set_column_counter : std_logic;
  96 SIGNAL ww_d_set_line_counter : std_logic;
  97 SIGNAL ww_d_hsync_counter : std_logic_vector(9 DOWNTO 0);
  98 SIGNAL ww_d_vsync_counter : std_logic_vector(9 DOWNTO 0);
  99 SIGNAL ww_d_set_hsync_counter : std_logic;
 100 SIGNAL ww_d_set_vsync_counter : std_logic;
 101 SIGNAL ww_d_h_enable : std_logic;
 102 SIGNAL ww_d_v_enable : std_logic;
 103 SIGNAL ww_d_r : std_logic;
 104 SIGNAL ww_d_g : std_logic;
 105 SIGNAL ww_d_b : std_logic;
 106 SIGNAL ww_d_hsync_state : std_logic_vector(0 TO 6);
 107 SIGNAL ww_d_vsync_state : std_logic_vector(0 TO 6);
 108 SIGNAL ww_d_state_clk : std_logic;
 109 SIGNAL \vga_driver_unit|un2_column_counter_next_0_~COMBOUT\ : std_logic;
 110 SIGNAL \vga_driver_unit|un1_line_counter_sig_a_1_~COMBOUT\ : std_logic;
 111 SIGNAL \clk_pin~combout\ : std_logic;
 112 SIGNAL \reset_pin~combout\ : std_logic;
 113 SIGNAL \vga_driver_unit|un6_dly_counter_0_x\ : std_logic;
 114 SIGNAL \vga_driver_unit|hsync_state_6\ : std_logic;
 115 SIGNAL \vga_driver_unit|hsync_counter_0\ : std_logic;
 116 SIGNAL \vga_driver_unit|hsync_counter_cout[0]~COUT1_10\ : std_logic;
 117 SIGNAL \vga_driver_unit|hsync_counter_1\ : std_logic;
 118 SIGNAL \vga_driver_unit|hsync_counter_cout[1]~COUT1_12\ : std_logic;
 119 SIGNAL \vga_driver_unit|hsync_counter_cout[2]~COUT1_14\ : std_logic;
 120 SIGNAL \vga_driver_unit|hsync_counter_3\ : std_logic;
 121 SIGNAL \vga_driver_unit|hsync_counter_cout[3]~COUT1_16\ : std_logic;
 122 SIGNAL \vga_driver_unit|hsync_counter_4\ : std_logic;
 123 SIGNAL \vga_driver_unit|hsync_counter_5\ : std_logic;
 124 SIGNAL \vga_driver_unit|un13_hsync_counter_7\ : std_logic;
 125 SIGNAL \vga_driver_unit|hsync_counter_cout[5]~COUT1_18\ : std_logic;
 126 SIGNAL \vga_driver_unit|hsync_counter_6\ : std_logic;
 127 SIGNAL \vga_driver_unit|hsync_counter_cout[6]~COUT1_20\ : std_logic;
 128 SIGNAL \vga_driver_unit|hsync_counter_cout[7]~COUT1_22\ : std_logic;
 129 SIGNAL \vga_driver_unit|hsync_counter_8\ : std_logic;
 130 SIGNAL \vga_driver_unit|hsync_counter_cout[8]~COUT1_24\ : std_logic;
 131 SIGNAL \vga_driver_unit|hsync_counter_9\ : std_logic;
 132 SIGNAL \vga_driver_unit|un9_hsync_counterlt9_3\ : std_logic;
 133 SIGNAL \vga_driver_unit|un9_hsync_counterlt9\ : std_logic;
 134 SIGNAL \vga_driver_unit|G_2_i\ : std_logic;
 135 SIGNAL \vga_driver_unit|hsync_counter_7\ : std_logic;
 136 SIGNAL \vga_driver_unit|un13_hsync_counter_2\ : std_logic;
 137 SIGNAL \vga_driver_unit|un13_hsync_counter\ : std_logic;
 138 SIGNAL \vga_driver_unit|un12_hsync_counter_4\ : std_logic;
 139 SIGNAL \vga_driver_unit|un12_hsync_counter_3\ : std_logic;
 140 SIGNAL \vga_driver_unit|un12_hsync_counter\ : std_logic;
 141 SIGNAL \vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0\ : std_logic;
 142 SIGNAL \vga_driver_unit|un10_hsync_counter_4\ : std_logic;
 143 SIGNAL \vga_driver_unit|hsync_state_5\ : std_logic;
 144 SIGNAL \vga_driver_unit|un10_hsync_counter_1\ : std_logic;
 145 SIGNAL \vga_driver_unit|hsync_state_next_1_sqmuxa_1\ : std_logic;
 146 SIGNAL \vga_driver_unit|un11_hsync_counter_3\ : std_logic;
 147 SIGNAL \vga_driver_unit|un11_hsync_counter_2\ : std_logic;
 148 SIGNAL \vga_driver_unit|hsync_state_next_1_sqmuxa_2\ : std_logic;
 149 SIGNAL \vga_driver_unit|hsync_state_3_0_0_0__g0_0\ : std_logic;
 150 SIGNAL \vga_driver_unit|hsync_state_3\ : std_logic;
 151 SIGNAL \vga_driver_unit|hsync_state_2\ : std_logic;
 152 SIGNAL \vga_driver_unit|hsync_state_0\ : std_logic;
 153 SIGNAL \vga_driver_unit|d_set_hsync_counter\ : std_logic;
 154 SIGNAL \vga_driver_unit|hsync_counter_next_1_sqmuxa\ : std_logic;
 155 SIGNAL \vga_driver_unit|hsync_counter_2\ : std_logic;
 156 SIGNAL \vga_driver_unit|un10_hsync_counter_3\ : std_logic;
 157 SIGNAL \vga_driver_unit|hsync_state_4\ : std_logic;
 158 SIGNAL \vga_driver_unit|hsync_state_1\ : std_logic;
 159 SIGNAL \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\ : std_logic;
 160 SIGNAL \vga_driver_unit|column_counter_sig_0\ : std_logic;
 161 SIGNAL \vga_driver_unit|column_counter_sig_1\ : std_logic;
 162 SIGNAL \vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10\ : std_logic;
 163 SIGNAL \vga_driver_unit|column_counter_sig_3\ : std_logic;
 164 SIGNAL \vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18\ : std_logic;
 165 SIGNAL \vga_driver_unit|column_counter_sig_2\ : std_logic;
 166 SIGNAL \vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20\ : std_logic;
 167 SIGNAL \vga_driver_unit|column_counter_sig_4\ : std_logic;
 168 SIGNAL \vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12\ : std_logic;
 169 SIGNAL \vga_driver_unit|column_counter_sig_5\ : std_logic;
 170 SIGNAL \vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14\ : std_logic;
 171 SIGNAL \vga_driver_unit|column_counter_sig_7\ : std_logic;
 172 SIGNAL \vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22\ : std_logic;
 173 SIGNAL \vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24\ : std_logic;
 174 SIGNAL \vga_driver_unit|column_counter_sig_8\ : std_logic;
 175 SIGNAL \vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16\ : std_logic;
 176 SIGNAL \vga_driver_unit|column_counter_sig_9\ : std_logic;
 177 SIGNAL \vga_driver_unit|un10_column_counter_siglt6_1\ : std_logic;
 178 SIGNAL \vga_driver_unit|un10_column_counter_siglt6\ : std_logic;
 179 SIGNAL \vga_driver_unit|un10_column_counter_siglto9\ : std_logic;
 180 SIGNAL \vga_driver_unit|column_counter_sig_6\ : std_logic;
 181 SIGNAL \vga_driver_unit|un10_column_counter_siglt6_3\ : std_logic;
 182 SIGNAL \vga_control_unit|b_next_i_o3_0\ : std_logic;
 183 SIGNAL \vga_control_unit|g_next_i_o3\ : std_logic;
 184 SIGNAL \vga_driver_unit|vsync_state_6\ : std_logic;
 185 SIGNAL \vga_driver_unit|vsync_counter_0\ : std_logic;
 186 SIGNAL \vga_driver_unit|vsync_counter_cout[0]~COUT1_10\ : std_logic;
 187 SIGNAL \vga_driver_unit|vsync_counter_1\ : std_logic;
 188 SIGNAL \vga_driver_unit|vsync_counter_cout[1]~COUT1_12\ : std_logic;
 189 SIGNAL \vga_driver_unit|vsync_counter_2\ : std_logic;
 190 SIGNAL \vga_driver_unit|vsync_counter_cout[2]~COUT1_14\ : std_logic;
 191 SIGNAL \vga_driver_unit|vsync_counter_3\ : std_logic;
 192 SIGNAL \vga_driver_unit|vsync_counter_cout[3]~COUT1_16\ : std_logic;
 193 SIGNAL \vga_driver_unit|vsync_counter_5\ : std_logic;
 194 SIGNAL \vga_driver_unit|un9_vsync_counterlt9_6\ : std_logic;
 195 SIGNAL \vga_driver_unit|vsync_counter_cout[5]~COUT1_18\ : std_logic;
 196 SIGNAL \vga_driver_unit|vsync_counter_6\ : std_logic;
 197 SIGNAL \vga_driver_unit|vsync_counter_cout[6]~COUT1_20\ : std_logic;
 198 SIGNAL \vga_driver_unit|vsync_counter_cout[7]~COUT1_22\ : std_logic;
 199 SIGNAL \vga_driver_unit|vsync_counter_8\ : std_logic;
 200 SIGNAL \vga_driver_unit|vsync_counter_cout[8]~COUT1_24\ : std_logic;
 201 SIGNAL \vga_driver_unit|vsync_counter_9\ : std_logic;
 202 SIGNAL \vga_driver_unit|un9_vsync_counterlt9_5\ : std_logic;
 203 SIGNAL \vga_driver_unit|un9_vsync_counterlt9\ : std_logic;
 204 SIGNAL \vga_driver_unit|G_16_i\ : std_logic;
 205 SIGNAL \vga_driver_unit|vsync_counter_7\ : std_logic;
 206 SIGNAL \vga_driver_unit|un12_vsync_counter_6\ : std_logic;
 207 SIGNAL \vga_driver_unit|un15_vsync_counter_3\ : std_logic;
 208 SIGNAL \vga_driver_unit|un15_vsync_counter_4\ : std_logic;
 209 SIGNAL \vga_driver_unit|un14_vsync_counter_8\ : std_logic;
 210 SIGNAL \vga_driver_unit|vsync_state_5\ : std_logic;
 211 SIGNAL \vga_driver_unit|vsync_state_4\ : std_logic;
 212 SIGNAL \vga_driver_unit|un13_vsync_counter_3\ : std_logic;
 213 SIGNAL \vga_driver_unit|un13_vsync_counter_4\ : std_logic;
 214 SIGNAL \vga_driver_unit|vsync_state_next_1_sqmuxa_2\ : std_logic;
 215 SIGNAL \vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0\ : std_logic;
 216 SIGNAL \vga_driver_unit|vsync_state_next_1_sqmuxa_1\ : std_logic;
 217 SIGNAL \vga_driver_unit|vsync_state_next_1_sqmuxa_3\ : std_logic;
 218 SIGNAL \vga_driver_unit|vsync_state_next_2_sqmuxa\ : std_logic;
 219 SIGNAL \vga_driver_unit|vsync_state_3\ : std_logic;
 220 SIGNAL \vga_driver_unit|vsync_state_2\ : std_logic;
 221 SIGNAL \vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0\ : std_logic;
 222 SIGNAL \vga_driver_unit|vsync_state_0\ : std_logic;
 223 SIGNAL \vga_driver_unit|d_set_vsync_counter\ : std_logic;
 224 SIGNAL \vga_driver_unit|vsync_counter_next_1_sqmuxa\ : std_logic;
 225 SIGNAL \vga_driver_unit|vsync_counter_4\ : std_logic;
 226 SIGNAL \vga_driver_unit|un12_vsync_counter_7\ : std_logic;
 227 SIGNAL \vga_driver_unit|vsync_state_1\ : std_logic;
 228 SIGNAL \vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4\ : std_logic;
 229 SIGNAL \vga_driver_unit|h_enable_sig\ : std_logic;
 230 SIGNAL \vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4\ : std_logic;
 231 SIGNAL \vga_driver_unit|v_enable_sig\ : std_logic;
 232 SIGNAL \vga_control_unit|r_next_i_o7\ : std_logic;
 233 SIGNAL \vga_control_unit|N_4_i_0_g0_1\ : std_logic;
 234 SIGNAL \vga_control_unit|r\ : std_logic;
 235 SIGNAL \vga_control_unit|N_23_i_0_g0_a\ : std_logic;
 236 SIGNAL \vga_control_unit|g\ : std_logic;
 237 SIGNAL \vga_control_unit|b_next_i_a7_1\ : std_logic;
 238 SIGNAL \vga_control_unit|N_6_i_0_g0_0\ : std_logic;
 239 SIGNAL \vga_control_unit|b\ : std_logic;
 240 SIGNAL \vga_driver_unit|un1_hsync_state_3_0\ : std_logic;
 241 SIGNAL \vga_driver_unit|h_sync_1_0_0_0_g1\ : std_logic;
 242 SIGNAL \vga_driver_unit|h_sync\ : std_logic;
 243 SIGNAL \vga_driver_unit|un1_vsync_state_2_0\ : std_logic;
 244 SIGNAL \vga_driver_unit|v_sync_1_0_0_0_g1\ : std_logic;
 245 SIGNAL \vga_driver_unit|v_sync\ : std_logic;
 246 SIGNAL \~STRATIX_FITTER_CREATED_GND~I_combout\ : std_logic;
 247 SIGNAL \vga_driver_unit|line_counter_next_0_sqmuxa_1_1\ : std_logic;
 248 SIGNAL \vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3\ : std_logic;
 249 SIGNAL \vga_driver_unit|line_counter_sig_1\ : std_logic;
 250 SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9\ : std_logic;
 251 SIGNAL \vga_driver_unit|line_counter_sig_2\ : std_logic;
 252 SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17\ : std_logic;
 253 SIGNAL \vga_driver_unit|line_counter_sig_3\ : std_logic;
 254 SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11\ : std_logic;
 255 SIGNAL \vga_driver_unit|line_counter_sig_4\ : std_logic;
 256 SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19\ : std_logic;
 257 SIGNAL \vga_driver_unit|line_counter_sig_5\ : std_logic;
 258 SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13\ : std_logic;
 259 SIGNAL \vga_driver_unit|line_counter_sig_6\ : std_logic;
 260 SIGNAL \vga_driver_unit|un10_line_counter_siglt4_2\ : std_logic;
 261 SIGNAL \vga_driver_unit|un10_line_counter_siglto5\ : std_logic;
 262 SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21\ : std_logic;
 263 SIGNAL \vga_driver_unit|line_counter_sig_7\ : std_logic;
 264 SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15\ : std_logic;
 265 SIGNAL \vga_driver_unit|line_counter_sig_8\ : std_logic;
 266 SIGNAL \vga_driver_unit|un10_line_counter_siglto8\ : std_logic;
 267 SIGNAL \vga_driver_unit|line_counter_sig_0\ : std_logic;
 268 SIGNAL \vga_driver_unit|hsync_counter_cout\ : std_logic_vector(8 DOWNTO 0);
 269 SIGNAL \vga_driver_unit|un1_line_counter_sig_a_cout\ : std_logic_vector(1 DOWNTO 1);
 270 SIGNAL \vga_driver_unit|un1_line_counter_sig_combout\ : std_logic_vector(9 DOWNTO 1);
 271 SIGNAL \vga_driver_unit|un1_line_counter_sig_cout\ : std_logic_vector(7 DOWNTO 1);
 272 SIGNAL \vga_driver_unit|un2_column_counter_next_combout\ : std_logic_vector(9 DOWNTO 1);
 273 SIGNAL \vga_driver_unit|un2_column_counter_next_cout\ : std_logic_vector(7 DOWNTO 0);
 274 SIGNAL \vga_driver_unit|vsync_counter_cout\ : std_logic_vector(8 DOWNTO 0);
 275 SIGNAL dly_counter : std_logic_vector(1 DOWNTO 0);
 276 SIGNAL \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\ : std_logic;
 277 SIGNAL \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\ : std_logic;
 278 SIGNAL \vga_driver_unit|ALT_INV_G_2_i\ : std_logic;
 279 SIGNAL \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\ : std_logic;
 280 SIGNAL \vga_driver_unit|ALT_INV_G_16_i\ : std_logic;
 281 SIGNAL \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\ : std_logic;
 282 SIGNAL \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\ : std_logic;
 283
 284 BEGIN
 285
 286 ww_clk_pin <= clk_pin;
 287 ww_reset_pin <= reset_pin;
 288 r0_pin <= ww_r0_pin;
 289 r1_pin <= ww_r1_pin;
 290 r2_pin <= ww_r2_pin;
 291 g0_pin <= ww_g0_pin;
 292 g1_pin <= ww_g1_pin;
 293 g2_pin <= ww_g2_pin;
 294 b0_pin <= ww_b0_pin;
 295 b1_pin <= ww_b1_pin;
 296 hsync_pin <= ww_hsync_pin;
 297 vsync_pin <= ww_vsync_pin;
 298 seven_seg_pin <= ww_seven_seg_pin;
 299 d_hsync <= ww_d_hsync;
 300 d_vsync <= ww_d_vsync;
 301 d_column_counter <= ww_d_column_counter;
 302 d_line_counter <= ww_d_line_counter;
 303 d_set_column_counter <= ww_d_set_column_counter;
 304 d_set_line_counter <= ww_d_set_line_counter;
 305 d_hsync_counter <= ww_d_hsync_counter;
 306 d_vsync_counter <= ww_d_vsync_counter;
 307 d_set_hsync_counter <= ww_d_set_hsync_counter;
 308 d_set_vsync_counter <= ww_d_set_vsync_counter;
 309 d_h_enable <= ww_d_h_enable;
 310 d_v_enable <= ww_d_v_enable;
 311 d_r <= ww_d_r;
 312 d_g <= ww_d_g;
 313 d_b <= ww_d_b;
 314 d_hsync_state <= ww_d_hsync_state;
 315 d_vsync_state <= ww_d_vsync_state;
 316 d_state_clk <= ww_d_state_clk;
 317 ww_devoe <= devoe;
 318 ww_devclrn <= devclrn;
 319 ww_devpor <= devpor;
 320 \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\ <= NOT \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\;
 321 \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\ <= NOT \vga_driver_unit|line_counter_next_0_sqmuxa_1_1\;
 322 \vga_driver_unit|ALT_INV_G_2_i\ <= NOT \vga_driver_unit|G_2_i\;
 323 \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\ <= NOT \vga_driver_unit|un9_hsync_counterlt9\;
 324 \vga_driver_unit|ALT_INV_G_16_i\ <= NOT \vga_driver_unit|G_16_i\;
 325 \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\ <= NOT \vga_driver_unit|un9_vsync_counterlt9\;
 326 \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\ <= NOT \~STRATIX_FITTER_CREATED_GND~I_combout\;
 327
 328 clk_pin_in : stratix_io
 329 -- pragma translate_off
 330 GENERIC MAP (
 331         ddio_mode => "none",
 332         input_async_reset => "none",
 333         input_power_up => "low",
 334         input_register_mode => "none",
 335         input_sync_reset => "none",
 336         oe_async_reset => "none",
 337         oe_power_up => "low",
 338         oe_register_mode => "none",
 339         oe_sync_reset => "none",
 340         operation_mode => "input",
 341         output_async_reset => "none",
 342         output_power_up => "low",
 343         output_register_mode => "none",
 344         output_sync_reset => "none")
 345 -- pragma translate_on
 346 PORT MAP (
 347         devclrn => ww_devclrn,
 348         devpor => ww_devpor,
 349         devoe => ww_devoe,
 350         oe => GND,
 351         padio => ww_clk_pin,
 352         combout => \clk_pin~combout\);
 353
 354 reset_pin_in : stratix_io
 355 -- pragma translate_off
 356 GENERIC MAP (
 357         ddio_mode => "none",
 358         input_async_reset => "none",
 359         input_power_up => "low",
 360         input_register_mode => "none",
 361         input_sync_reset => "none",
 362         oe_async_reset => "none",
 363         oe_power_up => "low",
 364         oe_register_mode => "none",
 365         oe_sync_reset => "none",
 366         operation_mode => "input",
 367         output_async_reset => "none",
 368         output_power_up => "low",
 369         output_register_mode => "none",
 370         output_sync_reset => "none")
 371 -- pragma translate_on
 372 PORT MAP (
 373         devclrn => ww_devclrn,
 374         devpor => ww_devpor,
 375         devoe => ww_devoe,
 376         oe => GND,
 377         padio => ww_reset_pin,
 378         combout => \reset_pin~combout\);
 379
 380 \dly_counter_1_\ : stratix_lcell
 381 -- Equation(s):
 382 -- dly_counter(1) = DFFEAS(\reset_pin~combout\ & (dly_counter(0) # dly_counter(1)), GLOBAL(\clk_pin~combout\), VCC, , , , , , )
 383
 384 -- pragma translate_off
 385 GENERIC MAP (
 386         lut_mask => "a8a8",
 387         operation_mode => "normal",
 388         output_mode => "reg_only",
 389         register_cascade_mode => "off",
 390         sum_lutc_input => "datac",
 391         synch_mode => "off")
 392 -- pragma translate_on
 393 PORT MAP (
 394         clk => \clk_pin~combout\,
 395         dataa => \reset_pin~combout\,
 396         datab => dly_counter(0),
 397         datac => dly_counter(1),
 398         aclr => GND,
 399         devclrn => ww_devclrn,
 400         devpor => ww_devpor,
 401         regout => dly_counter(1));
 402
 403 \dly_counter_0_\ : stratix_lcell
 404 -- Equation(s):
 405 -- dly_counter(0) = DFFEAS(\reset_pin~combout\ & (dly_counter(1) # !dly_counter(0)), GLOBAL(\clk_pin~combout\), VCC, , , , , , )
 406
 407 -- pragma translate_off
 408 GENERIC MAP (
 409         lut_mask => "a2a2",
 410         operation_mode => "normal",
 411         output_mode => "reg_only",
 412         register_cascade_mode => "off",
 413         sum_lutc_input => "datac",
 414         synch_mode => "off")
 415 -- pragma translate_on
 416 PORT MAP (
 417         clk => \clk_pin~combout\,
 418         dataa => \reset_pin~combout\,
 419         datab => dly_counter(0),
 420         datac => dly_counter(1),
 421         aclr => GND,
 422         devclrn => ww_devclrn,
 423         devpor => ww_devpor,
 424         regout => dly_counter(0));
 425
 426 \vga_driver_unit|vsync_state_6_\ : stratix_lcell
 427 -- Equation(s):
 428 -- \vga_driver_unit|un6_dly_counter_0_x\ = !dly_counter(1) # !dly_counter(0) # !\reset_pin~combout\
 429 -- \vga_driver_unit|vsync_state_6\ = DFFEAS(\vga_driver_unit|un6_dly_counter_0_x\, GLOBAL(\clk_pin~combout\), VCC, , , , , , )
 430
 431 -- pragma translate_off
 432 GENERIC MAP (
 433         lut_mask => "7f7f",
 434         operation_mode => "normal",
 435         output_mode => "reg_and_comb",
 436         register_cascade_mode => "off",
 437         sum_lutc_input => "datac",
 438         synch_mode => "off")
 439 -- pragma translate_on
 440 PORT MAP (
 441         clk => \clk_pin~combout\,
 442         dataa => \reset_pin~combout\,
 443         datab => dly_counter(0),
 444         datac => dly_counter(1),
 445         aclr => GND,
 446         devclrn => ww_devclrn,
 447         devpor => ww_devpor,
 448         combout => \vga_driver_unit|un6_dly_counter_0_x\,
 449         regout => \vga_driver_unit|vsync_state_6\);
 450
 451 \vga_driver_unit|hsync_state_6_\ : stratix_lcell
 452 -- Equation(s):
 453 -- \vga_driver_unit|d_set_hsync_counter\ = C1_hsync_state_6 # \vga_driver_unit|hsync_state_0\
 454 -- \vga_driver_unit|hsync_state_6\ = DFFEAS(\vga_driver_unit|d_set_hsync_counter\, GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|un6_dly_counter_0_x\, , , VCC)
 455
 456 -- pragma translate_off
 457 GENERIC MAP (
 458         lut_mask => "fff0",
 459         operation_mode => "normal",
 460         output_mode => "reg_and_comb",
 461         register_cascade_mode => "off",
 462         sum_lutc_input => "qfbk",
 463         synch_mode => "on")
 464 -- pragma translate_on
 465 PORT MAP (
 466         clk => \clk_pin~combout\,
 467         datac => \vga_driver_unit|un6_dly_counter_0_x\,
 468         datad => \vga_driver_unit|hsync_state_0\,
 469         aclr => GND,
 470         sload => VCC,
 471         devclrn => ww_devclrn,
 472         devpor => ww_devpor,
 473         combout => \vga_driver_unit|d_set_hsync_counter\,
 474         regout => \vga_driver_unit|hsync_state_6\);
 475
 476 \vga_driver_unit|hsync_counter_0_\ : stratix_lcell
 477 -- Equation(s):
 478 -- \vga_driver_unit|hsync_counter_0\ = DFFEAS(!\vga_driver_unit|hsync_counter_0\, GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, !\vga_driver_unit|un9_hsync_counterlt9\)
 479 -- \vga_driver_unit|hsync_counter_cout\(0) = CARRY(\vga_driver_unit|hsync_counter_0\)
 480 -- \vga_driver_unit|hsync_counter_cout[0]~COUT1_10\ = CARRY(\vga_driver_unit|hsync_counter_0\)
 481
 482 -- pragma translate_off
 483 GENERIC MAP (
 484         lut_mask => "33cc",
 485         operation_mode => "arithmetic",
 486         output_mode => "reg_only",
 487         register_cascade_mode => "off",
 488         sum_lutc_input => "datac",
 489         synch_mode => "on")
 490 -- pragma translate_on
 491 PORT MAP (
 492         clk => \clk_pin~combout\,
 493         datab => \vga_driver_unit|hsync_counter_0\,
 494         datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
 495         aclr => GND,
 496         sclr => \vga_driver_unit|ALT_INV_G_2_i\,
 497         sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
 498         devclrn => ww_devclrn,
 499         devpor => ww_devpor,
 500         regout => \vga_driver_unit|hsync_counter_0\,
 501         cout0 => \vga_driver_unit|hsync_counter_cout\(0),
 502         cout1 => \vga_driver_unit|hsync_counter_cout[0]~COUT1_10\);
 503
 504 \vga_driver_unit|hsync_counter_1_\ : stratix_lcell
 505 -- Equation(s):
 506 -- \vga_driver_unit|hsync_counter_1\ = DFFEAS(\vga_driver_unit|hsync_counter_1\ $ \vga_driver_unit|hsync_counter_cout\(0), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\,
 507 -- !\vga_driver_unit|un9_hsync_counterlt9\)
 508 -- \vga_driver_unit|hsync_counter_cout\(1) = CARRY(!\vga_driver_unit|hsync_counter_cout\(0) # !\vga_driver_unit|hsync_counter_1\)
 509 -- \vga_driver_unit|hsync_counter_cout[1]~COUT1_12\ = CARRY(!\vga_driver_unit|hsync_counter_cout[0]~COUT1_10\ # !\vga_driver_unit|hsync_counter_1\)
 510
 511 -- pragma translate_off
 512 GENERIC MAP (
 513         cin0_used => "true",
 514         cin1_used => "true",
 515         lut_mask => "3c3f",
 516         operation_mode => "arithmetic",
 517         output_mode => "reg_only",
 518         register_cascade_mode => "off",
 519         sum_lutc_input => "cin",
 520         synch_mode => "on")
 521 -- pragma translate_on
 522 PORT MAP (
 523         clk => \clk_pin~combout\,
 524         datab => \vga_driver_unit|hsync_counter_1\,
 525         datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
 526         aclr => GND,
 527         sclr => \vga_driver_unit|ALT_INV_G_2_i\,
 528         sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
 529         cin0 => \vga_driver_unit|hsync_counter_cout\(0),
 530         cin1 => \vga_driver_unit|hsync_counter_cout[0]~COUT1_10\,
 531         devclrn => ww_devclrn,
 532         devpor => ww_devpor,
 533         regout => \vga_driver_unit|hsync_counter_1\,
 534         cout0 => \vga_driver_unit|hsync_counter_cout\(1),
 535         cout1 => \vga_driver_unit|hsync_counter_cout[1]~COUT1_12\);
 536
 537 \vga_driver_unit|hsync_counter_2_\ : stratix_lcell
 538 -- Equation(s):
 539 -- \vga_driver_unit|hsync_counter_2\ = DFFEAS(\vga_driver_unit|hsync_counter_2\ $ (!\vga_driver_unit|hsync_counter_cout\(1)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\,
 540 -- !\vga_driver_unit|un9_hsync_counterlt9\)
 541 -- \vga_driver_unit|hsync_counter_cout\(2) = CARRY(\vga_driver_unit|hsync_counter_2\ & (!\vga_driver_unit|hsync_counter_cout\(1)))
 542 -- \vga_driver_unit|hsync_counter_cout[2]~COUT1_14\ = CARRY(\vga_driver_unit|hsync_counter_2\ & (!\vga_driver_unit|hsync_counter_cout[1]~COUT1_12\))
 543
 544 -- pragma translate_off
 545 GENERIC MAP (
 546         cin0_used => "true",
 547         cin1_used => "true",
 548         lut_mask => "a50a",
 549         operation_mode => "arithmetic",
 550         output_mode => "reg_only",
 551         register_cascade_mode => "off",
 552         sum_lutc_input => "cin",
 553         synch_mode => "on")
 554 -- pragma translate_on
 555 PORT MAP (
 556         clk => \clk_pin~combout\,
 557         dataa => \vga_driver_unit|hsync_counter_2\,
 558         datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
 559         aclr => GND,
 560         sclr => \vga_driver_unit|ALT_INV_G_2_i\,
 561         sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
 562         cin0 => \vga_driver_unit|hsync_counter_cout\(1),
 563         cin1 => \vga_driver_unit|hsync_counter_cout[1]~COUT1_12\,
 564         devclrn => ww_devclrn,
 565         devpor => ww_devpor,
 566         regout => \vga_driver_unit|hsync_counter_2\,
 567         cout0 => \vga_driver_unit|hsync_counter_cout\(2),
 568         cout1 => \vga_driver_unit|hsync_counter_cout[2]~COUT1_14\);
 569
 570 \vga_driver_unit|hsync_counter_3_\ : stratix_lcell
 571 -- Equation(s):
 572 -- \vga_driver_unit|hsync_counter_3\ = DFFEAS(\vga_driver_unit|hsync_counter_3\ $ (\vga_driver_unit|hsync_counter_cout\(2)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\,
 573 -- !\vga_driver_unit|un9_hsync_counterlt9\)
 574 -- \vga_driver_unit|hsync_counter_cout\(3) = CARRY(!\vga_driver_unit|hsync_counter_cout\(2) # !\vga_driver_unit|hsync_counter_3\)
 575 -- \vga_driver_unit|hsync_counter_cout[3]~COUT1_16\ = CARRY(!\vga_driver_unit|hsync_counter_cout[2]~COUT1_14\ # !\vga_driver_unit|hsync_counter_3\)
 576
 577 -- pragma translate_off
 578 GENERIC MAP (
 579         cin0_used => "true",
 580         cin1_used => "true",
 581         lut_mask => "5a5f",
 582         operation_mode => "arithmetic",
 583         output_mode => "reg_only",
 584         register_cascade_mode => "off",
 585         sum_lutc_input => "cin",
 586         synch_mode => "on")
 587 -- pragma translate_on
 588 PORT MAP (
 589         clk => \clk_pin~combout\,
 590         dataa => \vga_driver_unit|hsync_counter_3\,
 591         datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
 592         aclr => GND,
 593         sclr => \vga_driver_unit|ALT_INV_G_2_i\,
 594         sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
 595         cin0 => \vga_driver_unit|hsync_counter_cout\(2),
 596         cin1 => \vga_driver_unit|hsync_counter_cout[2]~COUT1_14\,
 597         devclrn => ww_devclrn,
 598         devpor => ww_devpor,
 599         regout => \vga_driver_unit|hsync_counter_3\,
 600         cout0 => \vga_driver_unit|hsync_counter_cout\(3),
 601         cout1 => \vga_driver_unit|hsync_counter_cout[3]~COUT1_16\);
 602
 603 \vga_driver_unit|hsync_counter_4_\ : stratix_lcell
 604 -- Equation(s):
 605 -- \vga_driver_unit|hsync_counter_4\ = DFFEAS(\vga_driver_unit|hsync_counter_4\ $ (!\vga_driver_unit|hsync_counter_cout\(3)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\,
 606 -- !\vga_driver_unit|un9_hsync_counterlt9\)
 607 -- \vga_driver_unit|hsync_counter_cout\(4) = CARRY(\vga_driver_unit|hsync_counter_4\ & (!\vga_driver_unit|hsync_counter_cout[3]~COUT1_16\))
 608
 609 -- pragma translate_off
 610 GENERIC MAP (
 611         cin0_used => "true",
 612         cin1_used => "true",
 613         lut_mask => "a50a",
 614         operation_mode => "arithmetic",
 615         output_mode => "reg_only",
 616         register_cascade_mode => "off",
 617         sum_lutc_input => "cin",
 618         synch_mode => "on")
 619 -- pragma translate_on
 620 PORT MAP (
 621         clk => \clk_pin~combout\,
 622         dataa => \vga_driver_unit|hsync_counter_4\,
 623         datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
 624         aclr => GND,
 625         sclr => \vga_driver_unit|ALT_INV_G_2_i\,
 626         sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
 627         cin0 => \vga_driver_unit|hsync_counter_cout\(3),
 628         cin1 => \vga_driver_unit|hsync_counter_cout[3]~COUT1_16\,
 629         devclrn => ww_devclrn,
 630         devpor => ww_devpor,
 631         regout => \vga_driver_unit|hsync_counter_4\,
 632         cout => \vga_driver_unit|hsync_counter_cout\(4));
 633
 634 \vga_driver_unit|hsync_counter_5_\ : stratix_lcell
 635 -- Equation(s):
 636 -- \vga_driver_unit|hsync_counter_5\ = DFFEAS(\vga_driver_unit|hsync_counter_5\ $ \vga_driver_unit|hsync_counter_cout\(4), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\,
 637 -- !\vga_driver_unit|un9_hsync_counterlt9\)
 638 -- \vga_driver_unit|hsync_counter_cout\(5) = CARRY(!\vga_driver_unit|hsync_counter_cout\(4) # !\vga_driver_unit|hsync_counter_5\)
 639 -- \vga_driver_unit|hsync_counter_cout[5]~COUT1_18\ = CARRY(!\vga_driver_unit|hsync_counter_cout\(4) # !\vga_driver_unit|hsync_counter_5\)
 640
 641 -- pragma translate_off
 642 GENERIC MAP (
 643         cin_used => "true",
 644         lut_mask => "3c3f",
 645         operation_mode => "arithmetic",
 646         output_mode => "reg_only",
 647         register_cascade_mode => "off",
 648         sum_lutc_input => "cin",
 649         synch_mode => "on")
 650 -- pragma translate_on
 651 PORT MAP (
 652         clk => \clk_pin~combout\,
 653         datab => \vga_driver_unit|hsync_counter_5\,
 654         datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
 655         aclr => GND,
 656         sclr => \vga_driver_unit|ALT_INV_G_2_i\,
 657         sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
 658         cin => \vga_driver_unit|hsync_counter_cout\(4),
 659         devclrn => ww_devclrn,
 660         devpor => ww_devpor,
 661         regout => \vga_driver_unit|hsync_counter_5\,
 662         cout0 => \vga_driver_unit|hsync_counter_cout\(5),
 663         cout1 => \vga_driver_unit|hsync_counter_cout[5]~COUT1_18\);
 664
 665 \vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7\ : stratix_lcell
 666 -- Equation(s):
 667 -- \vga_driver_unit|un13_hsync_counter_7\ = \vga_driver_unit|hsync_counter_1\ & \vga_driver_unit|hsync_counter_2\ & \vga_driver_unit|hsync_counter_3\ & \vga_driver_unit|hsync_counter_0\
 668
 669 -- pragma translate_off
 670 GENERIC MAP (
 671         lut_mask => "8000",
 672         operation_mode => "normal",
 673         output_mode => "comb_only",
 674         register_cascade_mode => "off",
 675         sum_lutc_input => "datac",
 676         synch_mode => "off")
 677 -- pragma translate_on
 678 PORT MAP (
 679         dataa => \vga_driver_unit|hsync_counter_1\,
 680         datab => \vga_driver_unit|hsync_counter_2\,
 681         datac => \vga_driver_unit|hsync_counter_3\,
 682         datad => \vga_driver_unit|hsync_counter_0\,
 683         devclrn => ww_devclrn,
 684         devpor => ww_devpor,
 685         combout => \vga_driver_unit|un13_hsync_counter_7\);
 686
 687 \vga_driver_unit|hsync_counter_6_\ : stratix_lcell
 688 -- Equation(s):
 689 -- \vga_driver_unit|hsync_counter_6\ = DFFEAS(\vga_driver_unit|hsync_counter_6\ $ !(!\vga_driver_unit|hsync_counter_cout\(4) & \vga_driver_unit|hsync_counter_cout\(5)) # (\vga_driver_unit|hsync_counter_cout\(4) &
 690 -- \vga_driver_unit|hsync_counter_cout[5]~COUT1_18\), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, !\vga_driver_unit|un9_hsync_counterlt9\)
 691 -- \vga_driver_unit|hsync_counter_cout\(6) = CARRY(\vga_driver_unit|hsync_counter_6\ & !\vga_driver_unit|hsync_counter_cout\(5))
 692 -- \vga_driver_unit|hsync_counter_cout[6]~COUT1_20\ = CARRY(\vga_driver_unit|hsync_counter_6\ & !\vga_driver_unit|hsync_counter_cout[5]~COUT1_18\)
 693
 694 -- pragma translate_off
 695 GENERIC MAP (
 696         cin0_used => "true",
 697         cin1_used => "true",
 698         cin_used => "true",
 699         lut_mask => "c30c",
 700         operation_mode => "arithmetic",
 701         output_mode => "reg_only",
 702         register_cascade_mode => "off",
 703         sum_lutc_input => "cin",
 704         synch_mode => "on")
 705 -- pragma translate_on
 706 PORT MAP (
 707         clk => \clk_pin~combout\,
 708         datab => \vga_driver_unit|hsync_counter_6\,
 709         datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
 710         aclr => GND,
 711         sclr => \vga_driver_unit|ALT_INV_G_2_i\,
 712         sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
 713         cin => \vga_driver_unit|hsync_counter_cout\(4),
 714         cin0 => \vga_driver_unit|hsync_counter_cout\(5),
 715         cin1 => \vga_driver_unit|hsync_counter_cout[5]~COUT1_18\,
 716         devclrn => ww_devclrn,
 717         devpor => ww_devpor,
 718         regout => \vga_driver_unit|hsync_counter_6\,
 719         cout0 => \vga_driver_unit|hsync_counter_cout\(6),
 720         cout1 => \vga_driver_unit|hsync_counter_cout[6]~COUT1_20\);
 721
 722 \vga_driver_unit|hsync_counter_7_\ : stratix_lcell
 723 -- Equation(s):
 724 -- \vga_driver_unit|hsync_counter_7\ = DFFEAS(\vga_driver_unit|hsync_counter_7\ $ ((!\vga_driver_unit|hsync_counter_cout\(4) & \vga_driver_unit|hsync_counter_cout\(6)) # (\vga_driver_unit|hsync_counter_cout\(4) &
 725 -- \vga_driver_unit|hsync_counter_cout[6]~COUT1_20\)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, !\vga_driver_unit|un9_hsync_counterlt9\)
 726 -- \vga_driver_unit|hsync_counter_cout\(7) = CARRY(!\vga_driver_unit|hsync_counter_cout\(6) # !\vga_driver_unit|hsync_counter_7\)
 727 -- \vga_driver_unit|hsync_counter_cout[7]~COUT1_22\ = CARRY(!\vga_driver_unit|hsync_counter_cout[6]~COUT1_20\ # !\vga_driver_unit|hsync_counter_7\)
 728
 729 -- pragma translate_off
 730 GENERIC MAP (
 731         cin0_used => "true",
 732         cin1_used => "true",
 733         cin_used => "true",
 734         lut_mask => "5a5f",
 735         operation_mode => "arithmetic",
 736         output_mode => "reg_only",
 737         register_cascade_mode => "off",
 738         sum_lutc_input => "cin",
 739         synch_mode => "on")
 740 -- pragma translate_on
 741 PORT MAP (
 742         clk => \clk_pin~combout\,
 743         dataa => \vga_driver_unit|hsync_counter_7\,
 744         datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
 745         aclr => GND,
 746         sclr => \vga_driver_unit|ALT_INV_G_2_i\,
 747         sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
 748         cin => \vga_driver_unit|hsync_counter_cout\(4),
 749         cin0 => \vga_driver_unit|hsync_counter_cout\(6),
 750         cin1 => \vga_driver_unit|hsync_counter_cout[6]~COUT1_20\,
 751         devclrn => ww_devclrn,
 752         devpor => ww_devpor,
 753         regout => \vga_driver_unit|hsync_counter_7\,
 754         cout0 => \vga_driver_unit|hsync_counter_cout\(7),
 755         cout1 => \vga_driver_unit|hsync_counter_cout[7]~COUT1_22\);
 756
 757 \vga_driver_unit|hsync_counter_8_\ : stratix_lcell
 758 -- Equation(s):
 759 -- \vga_driver_unit|hsync_counter_8\ = DFFEAS(\vga_driver_unit|hsync_counter_8\ $ (!(!\vga_driver_unit|hsync_counter_cout\(4) & \vga_driver_unit|hsync_counter_cout\(7)) # (\vga_driver_unit|hsync_counter_cout\(4) &
 760 -- \vga_driver_unit|hsync_counter_cout[7]~COUT1_22\)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, !\vga_driver_unit|un9_hsync_counterlt9\)
 761 -- \vga_driver_unit|hsync_counter_cout\(8) = CARRY(\vga_driver_unit|hsync_counter_8\ & (!\vga_driver_unit|hsync_counter_cout\(7)))
 762 -- \vga_driver_unit|hsync_counter_cout[8]~COUT1_24\ = CARRY(\vga_driver_unit|hsync_counter_8\ & (!\vga_driver_unit|hsync_counter_cout[7]~COUT1_22\))
 763
 764 -- pragma translate_off
 765 GENERIC MAP (
 766         cin0_used => "true",
 767         cin1_used => "true",
 768         cin_used => "true",
 769         lut_mask => "a50a",
 770         operation_mode => "arithmetic",
 771         output_mode => "reg_only",
 772         register_cascade_mode => "off",
 773         sum_lutc_input => "cin",
 774         synch_mode => "on")
 775 -- pragma translate_on
 776 PORT MAP (
 777         clk => \clk_pin~combout\,
 778         dataa => \vga_driver_unit|hsync_counter_8\,
 779         datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
 780         aclr => GND,
 781         sclr => \vga_driver_unit|ALT_INV_G_2_i\,
 782         sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
 783         cin => \vga_driver_unit|hsync_counter_cout\(4),
 784         cin0 => \vga_driver_unit|hsync_counter_cout\(7),
 785         cin1 => \vga_driver_unit|hsync_counter_cout[7]~COUT1_22\,
 786         devclrn => ww_devclrn,
 787         devpor => ww_devpor,
 788         regout => \vga_driver_unit|hsync_counter_8\,
 789         cout0 => \vga_driver_unit|hsync_counter_cout\(8),
 790         cout1 => \vga_driver_unit|hsync_counter_cout[8]~COUT1_24\);
 791
 792 \vga_driver_unit|hsync_counter_9_\ : stratix_lcell
 793 -- Equation(s):
 794 -- \vga_driver_unit|hsync_counter_9\ = DFFEAS((!\vga_driver_unit|hsync_counter_cout\(4) & \vga_driver_unit|hsync_counter_cout\(8)) # (\vga_driver_unit|hsync_counter_cout\(4) & \vga_driver_unit|hsync_counter_cout[8]~COUT1_24\) $
 795 -- \vga_driver_unit|hsync_counter_9\, GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, !\vga_driver_unit|un9_hsync_counterlt9\)
 796
 797 -- pragma translate_off
 798 GENERIC MAP (
 799         cin0_used => "true",
 800         cin1_used => "true",
 801         cin_used => "true",
 802         lut_mask => "0ff0",
 803         operation_mode => "normal",
 804         output_mode => "reg_only",
 805         register_cascade_mode => "off",
 806         sum_lutc_input => "cin",
 807         synch_mode => "on")
 808 -- pragma translate_on
 809 PORT MAP (
 810         clk => \clk_pin~combout\,
 811         datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
 812         datad => \vga_driver_unit|hsync_counter_9\,
 813         aclr => GND,
 814         sclr => \vga_driver_unit|ALT_INV_G_2_i\,
 815         sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
 816         cin => \vga_driver_unit|hsync_counter_cout\(4),
 817         cin0 => \vga_driver_unit|hsync_counter_cout\(8),
 818         cin1 => \vga_driver_unit|hsync_counter_cout[8]~COUT1_24\,
 819         devclrn => ww_devclrn,
 820         devpor => ww_devpor,
 821         regout => \vga_driver_unit|hsync_counter_9\);
 822
 823 \vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3\ : stratix_lcell
 824 -- Equation(s):
 825 -- \vga_driver_unit|un9_hsync_counterlt9_3\ = !\vga_driver_unit|hsync_counter_6\ # !\vga_driver_unit|hsync_counter_8\ # !\vga_driver_unit|hsync_counter_9\ # !\vga_driver_unit|hsync_counter_7\
 826
 827 -- pragma translate_off
 828 GENERIC MAP (
 829         lut_mask => "7fff",
 830         operation_mode => "normal",
 831         output_mode => "comb_only",
 832         register_cascade_mode => "off",
 833         sum_lutc_input => "datac",
 834         synch_mode => "off")
 835 -- pragma translate_on
 836 PORT MAP (
 837         dataa => \vga_driver_unit|hsync_counter_7\,
 838         datab => \vga_driver_unit|hsync_counter_9\,
 839         datac => \vga_driver_unit|hsync_counter_8\,
 840         datad => \vga_driver_unit|hsync_counter_6\,
 841         devclrn => ww_devclrn,
 842         devpor => ww_devpor,
 843         combout => \vga_driver_unit|un9_hsync_counterlt9_3\);
 844
 845 \vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9\ : stratix_lcell
 846 -- Equation(s):
 847 -- \vga_driver_unit|un9_hsync_counterlt9\ = \vga_driver_unit|un9_hsync_counterlt9_3\ # !\vga_driver_unit|un13_hsync_counter_7\ # !\vga_driver_unit|hsync_counter_4\ # !\vga_driver_unit|hsync_counter_5\
 848
 849 -- pragma translate_off
 850 GENERIC MAP (
 851         lut_mask => "ff7f",
 852         operation_mode => "normal",
 853         output_mode => "comb_only",
 854         register_cascade_mode => "off",
 855         sum_lutc_input => "datac",
 856         synch_mode => "off")
 857 -- pragma translate_on
 858 PORT MAP (
 859         dataa => \vga_driver_unit|hsync_counter_5\,
 860         datab => \vga_driver_unit|hsync_counter_4\,
 861         datac => \vga_driver_unit|un13_hsync_counter_7\,
 862         datad => \vga_driver_unit|un9_hsync_counterlt9_3\,
 863         devclrn => ww_devclrn,
 864         devpor => ww_devpor,
 865         combout => \vga_driver_unit|un9_hsync_counterlt9\);
 866
 867 \vga_driver_unit|G_2\ : stratix_lcell
 868 -- Equation(s):
 869 -- \vga_driver_unit|G_2_i\ = !\vga_driver_unit|hsync_state_6\ & !\vga_driver_unit|hsync_state_0\ & !\vga_driver_unit|un6_dly_counter_0_x\ # !\vga_driver_unit|un9_hsync_counterlt9\
 870
 871 -- pragma translate_off
 872 GENERIC MAP (
 873         lut_mask => "3337",
 874         operation_mode => "normal",
 875         output_mode => "comb_only",
 876         register_cascade_mode => "off",
 877         sum_lutc_input => "datac",
 878         synch_mode => "off")
 879 -- pragma translate_on
 880 PORT MAP (
 881         dataa => \vga_driver_unit|hsync_state_6\,
 882         datab => \vga_driver_unit|un9_hsync_counterlt9\,
 883         datac => \vga_driver_unit|hsync_state_0\,
 884         datad => \vga_driver_unit|un6_dly_counter_0_x\,
 885         devclrn => ww_devclrn,
 886         devpor => ww_devpor,
 887         combout => \vga_driver_unit|G_2_i\);
 888
 889 \vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2\ : stratix_lcell
 890 -- Equation(s):
 891 -- \vga_driver_unit|un13_hsync_counter_2\ = !\vga_driver_unit|hsync_counter_5\ & \vga_driver_unit|hsync_counter_9\ & \vga_driver_unit|hsync_counter_8\ & \vga_driver_unit|hsync_counter_4\
 892
 893 -- pragma translate_off
 894 GENERIC MAP (
 895         lut_mask => "4000",
 896         operation_mode => "normal",
 897         output_mode => "comb_only",
 898         register_cascade_mode => "off",
 899         sum_lutc_input => "datac",
 900         synch_mode => "off")
 901 -- pragma translate_on
 902 PORT MAP (
 903         dataa => \vga_driver_unit|hsync_counter_5\,
 904         datab => \vga_driver_unit|hsync_counter_9\,
 905         datac => \vga_driver_unit|hsync_counter_8\,
 906         datad => \vga_driver_unit|hsync_counter_4\,
 907         devclrn => ww_devclrn,
 908         devpor => ww_devpor,
 909         combout => \vga_driver_unit|un13_hsync_counter_2\);
 910
 911 \vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter\ : stratix_lcell
 912 -- Equation(s):
 913 -- \vga_driver_unit|un13_hsync_counter\ = !\vga_driver_unit|hsync_counter_7\ & !\vga_driver_unit|hsync_counter_6\ & \vga_driver_unit|un13_hsync_counter_7\ & \vga_driver_unit|un13_hsync_counter_2\
 914
 915 -- pragma translate_off
 916 GENERIC MAP (
 917         lut_mask => "1000",
 918         operation_mode => "normal",
 919         output_mode => "comb_only",
 920         register_cascade_mode => "off",
 921         sum_lutc_input => "datac",
 922         synch_mode => "off")
 923 -- pragma translate_on
 924 PORT MAP (
 925         dataa => \vga_driver_unit|hsync_counter_7\,
 926         datab => \vga_driver_unit|hsync_counter_6\,
 927         datac => \vga_driver_unit|un13_hsync_counter_7\,
 928         datad => \vga_driver_unit|un13_hsync_counter_2\,
 929         devclrn => ww_devclrn,
 930         devpor => ww_devpor,
 931         combout => \vga_driver_unit|un13_hsync_counter\);
 932
 933 \vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4\ : stratix_lcell
 934 -- Equation(s):
 935 -- \vga_driver_unit|un12_hsync_counter_4\ = !\vga_driver_unit|hsync_counter_7\ & !\vga_driver_unit|hsync_counter_4\ & \vga_driver_unit|hsync_counter_8\ & !\vga_driver_unit|hsync_counter_6\
 936
 937 -- pragma translate_off
 938 GENERIC MAP (
 939         lut_mask => "0010",
 940         operation_mode => "normal",
 941         output_mode => "comb_only",
 942         register_cascade_mode => "off",
 943         sum_lutc_input => "datac",
 944         synch_mode => "off")
 945 -- pragma translate_on
 946 PORT MAP (
 947         dataa => \vga_driver_unit|hsync_counter_7\,
 948         datab => \vga_driver_unit|hsync_counter_4\,
 949         datac => \vga_driver_unit|hsync_counter_8\,
 950         datad => \vga_driver_unit|hsync_counter_6\,
 951         devclrn => ww_devclrn,
 952         devpor => ww_devpor,
 953         combout => \vga_driver_unit|un12_hsync_counter_4\);
 954
 955 \vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3\ : stratix_lcell
 956 -- Equation(s):
 957 -- \vga_driver_unit|un12_hsync_counter_3\ = !\vga_driver_unit|hsync_counter_5\ & \vga_driver_unit|hsync_counter_9\ & !\vga_driver_unit|hsync_counter_3\ & \vga_driver_unit|hsync_counter_2\
 958
 959 -- pragma translate_off
 960 GENERIC MAP (
 961         lut_mask => "0400",
 962         operation_mode => "normal",
 963         output_mode => "comb_only",
 964         register_cascade_mode => "off",
 965         sum_lutc_input => "datac",
 966         synch_mode => "off")
 967 -- pragma translate_on
 968 PORT MAP (
 969         dataa => \vga_driver_unit|hsync_counter_5\,
 970         datab => \vga_driver_unit|hsync_counter_9\,
 971         datac => \vga_driver_unit|hsync_counter_3\,
 972         datad => \vga_driver_unit|hsync_counter_2\,
 973         devclrn => ww_devclrn,
 974         devpor => ww_devpor,
 975         combout => \vga_driver_unit|un12_hsync_counter_3\);
 976
 977 \vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter\ : stratix_lcell
 978 -- Equation(s):
 979 -- \vga_driver_unit|un12_hsync_counter\ = \vga_driver_unit|hsync_counter_0\ & \vga_driver_unit|hsync_counter_1\ & \vga_driver_unit|un12_hsync_counter_4\ & \vga_driver_unit|un12_hsync_counter_3\
 980
 981 -- pragma translate_off
 982 GENERIC MAP (
 983         lut_mask => "8000",
 984         operation_mode => "normal",
 985         output_mode => "comb_only",
 986         register_cascade_mode => "off",
 987         sum_lutc_input => "datac",
 988         synch_mode => "off")
 989 -- pragma translate_on
 990 PORT MAP (
 991         dataa => \vga_driver_unit|hsync_counter_0\,
 992         datab => \vga_driver_unit|hsync_counter_1\,
 993         datac => \vga_driver_unit|un12_hsync_counter_4\,
 994         datad => \vga_driver_unit|un12_hsync_counter_3\,
 995         devclrn => ww_devclrn,
 996         devpor => ww_devpor,
 997         combout => \vga_driver_unit|un12_hsync_counter\);
 998
 999 \vga_driver_unit|hsync_state_3_\ : stratix_lcell
1000 -- Equation(s):
1001 -- \vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0\ = \vga_driver_unit|hsync_state_2\ & (C1_hsync_state_3 & !\vga_driver_unit|un12_hsync_counter\ # !\vga_driver_unit|un13_hsync_counter\) # !\vga_driver_unit|hsync_state_2\ & (C1_hsync_state_3 &
1002 -- !\vga_driver_unit|un12_hsync_counter\)
1003 -- \vga_driver_unit|hsync_state_3\ = DFFEAS(\vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, \vga_driver_unit|hsync_state_1\, , \vga_driver_unit|un6_dly_counter_0_x\, VCC)
1004
1005 -- pragma translate_off
1006 GENERIC MAP (
1007         lut_mask => "22f2",
1008         operation_mode => "normal",
1009         output_mode => "reg_and_comb",
1010         register_cascade_mode => "off",
1011         sum_lutc_input => "qfbk",
1012         synch_mode => "on")
1013 -- pragma translate_on
1014 PORT MAP (
1015         clk => \clk_pin~combout\,
1016         dataa => \vga_driver_unit|hsync_state_2\,
1017         datab => \vga_driver_unit|un13_hsync_counter\,
1018         datac => \vga_driver_unit|hsync_state_1\,
1019         datad => \vga_driver_unit|un12_hsync_counter\,
1020         aclr => GND,
1021         sclr => \vga_driver_unit|un6_dly_counter_0_x\,
1022         sload => VCC,
1023         ena => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\,
1024         devclrn => ww_devclrn,
1025         devpor => ww_devpor,
1026         combout => \vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0\,
1027         regout => \vga_driver_unit|hsync_state_3\);
1028
1029 \vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4\ : stratix_lcell
1030 -- Equation(s):
1031 -- \vga_driver_unit|un10_hsync_counter_4\ = \vga_driver_unit|hsync_counter_1\ & \vga_driver_unit|hsync_counter_6\ & \vga_driver_unit|hsync_counter_4\ & \vga_driver_unit|hsync_counter_3\
1032
1033 -- pragma translate_off
1034 GENERIC MAP (
1035         lut_mask => "8000",
1036         operation_mode => "normal",
1037         output_mode => "comb_only",
1038         register_cascade_mode => "off",
1039         sum_lutc_input => "datac",
1040         synch_mode => "off")
1041 -- pragma translate_on
1042 PORT MAP (
1043         dataa => \vga_driver_unit|hsync_counter_1\,
1044         datab => \vga_driver_unit|hsync_counter_6\,
1045         datac => \vga_driver_unit|hsync_counter_4\,
1046         datad => \vga_driver_unit|hsync_counter_3\,
1047         devclrn => ww_devclrn,
1048         devpor => ww_devpor,
1049         combout => \vga_driver_unit|un10_hsync_counter_4\);
1050
1051 \vga_driver_unit|hsync_state_5_\ : stratix_lcell
1052 -- Equation(s):
1053 -- \vga_driver_unit|hsync_state_5\ = DFFEAS(\vga_driver_unit|hsync_state_0\ # \vga_driver_unit|hsync_state_6\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
1054
1055 -- pragma translate_off
1056 GENERIC MAP (
1057         lut_mask => "fcfc",
1058         operation_mode => "normal",
1059         output_mode => "reg_only",
1060         register_cascade_mode => "off",
1061         sum_lutc_input => "datac",
1062         synch_mode => "on")
1063 -- pragma translate_on
1064 PORT MAP (
1065         clk => \clk_pin~combout\,
1066         datab => \vga_driver_unit|hsync_state_0\,
1067         datac => \vga_driver_unit|hsync_state_6\,
1068         aclr => GND,
1069         sclr => \vga_driver_unit|un6_dly_counter_0_x\,
1070         ena => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\,
1071         devclrn => ww_devclrn,
1072         devpor => ww_devpor,
1073         regout => \vga_driver_unit|hsync_state_5\);
1074
1075 \vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1\ : stratix_lcell
1076 -- Equation(s):
1077 -- \vga_driver_unit|un10_hsync_counter_1\ = !\vga_driver_unit|hsync_counter_9\ & !\vga_driver_unit|hsync_counter_5\ & (!\vga_driver_unit|hsync_counter_8\)
1078
1079 -- pragma translate_off
1080 GENERIC MAP (
1081         lut_mask => "0011",
1082         operation_mode => "normal",
1083         output_mode => "comb_only",
1084         register_cascade_mode => "off",
1085         sum_lutc_input => "datac",
1086         synch_mode => "off")
1087 -- pragma translate_on
1088 PORT MAP (
1089         dataa => \vga_driver_unit|hsync_counter_9\,
1090         datab => \vga_driver_unit|hsync_counter_5\,
1091         datad => \vga_driver_unit|hsync_counter_8\,
1092         devclrn => ww_devclrn,
1093         devpor => ww_devpor,
1094         combout => \vga_driver_unit|un10_hsync_counter_1\);
1095
1096 \vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ\ : stratix_lcell
1097 -- Equation(s):
1098 -- \vga_driver_unit|hsync_state_next_1_sqmuxa_1\ = \vga_driver_unit|hsync_state_5\ & (!\vga_driver_unit|un10_hsync_counter_1\ # !\vga_driver_unit|un10_hsync_counter_4\ # !\vga_driver_unit|un10_hsync_counter_3\)
1099
1100 -- pragma translate_off
1101 GENERIC MAP (
1102         lut_mask => "70f0",
1103         operation_mode => "normal",
1104         output_mode => "comb_only",
1105         register_cascade_mode => "off",
1106         sum_lutc_input => "datac",
1107         synch_mode => "off")
1108 -- pragma translate_on
1109 PORT MAP (
1110         dataa => \vga_driver_unit|un10_hsync_counter_3\,
1111         datab => \vga_driver_unit|un10_hsync_counter_4\,
1112         datac => \vga_driver_unit|hsync_state_5\,
1113         datad => \vga_driver_unit|un10_hsync_counter_1\,
1114         devclrn => ww_devclrn,
1115         devpor => ww_devpor,
1116         combout => \vga_driver_unit|hsync_state_next_1_sqmuxa_1\);
1117
1118 \vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3\ : stratix_lcell
1119 -- Equation(s):
1120 -- \vga_driver_unit|un11_hsync_counter_3\ = \vga_driver_unit|hsync_counter_1\ & !\vga_driver_unit|hsync_counter_4\ & !\vga_driver_unit|hsync_counter_3\ & \vga_driver_unit|hsync_counter_0\
1121
1122 -- pragma translate_off
1123 GENERIC MAP (
1124         lut_mask => "0200",
1125         operation_mode => "normal",
1126         output_mode => "comb_only",
1127         register_cascade_mode => "off",
1128         sum_lutc_input => "datac",
1129         synch_mode => "off")
1130 -- pragma translate_on
1131 PORT MAP (
1132         dataa => \vga_driver_unit|hsync_counter_1\,
1133         datab => \vga_driver_unit|hsync_counter_4\,
1134         datac => \vga_driver_unit|hsync_counter_3\,
1135         datad => \vga_driver_unit|hsync_counter_0\,
1136         devclrn => ww_devclrn,
1137         devpor => ww_devpor,
1138         combout => \vga_driver_unit|un11_hsync_counter_3\);
1139
1140 \vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2\ : stratix_lcell
1141 -- Equation(s):
1142 -- \vga_driver_unit|un11_hsync_counter_2\ = !\vga_driver_unit|hsync_counter_6\ & \vga_driver_unit|hsync_counter_7\ & \vga_driver_unit|hsync_counter_2\
1143
1144 -- pragma translate_off
1145 GENERIC MAP (
1146         lut_mask => "3000",
1147         operation_mode => "normal",
1148         output_mode => "comb_only",
1149         register_cascade_mode => "off",
1150         sum_lutc_input => "datac",
1151         synch_mode => "off")
1152 -- pragma translate_on
1153 PORT MAP (
1154         datab => \vga_driver_unit|hsync_counter_6\,
1155         datac => \vga_driver_unit|hsync_counter_7\,
1156         datad => \vga_driver_unit|hsync_counter_2\,
1157         devclrn => ww_devclrn,
1158         devpor => ww_devpor,
1159         combout => \vga_driver_unit|un11_hsync_counter_2\);
1160
1161 \vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ\ : stratix_lcell
1162 -- Equation(s):
1163 -- \vga_driver_unit|hsync_state_next_1_sqmuxa_2\ = \vga_driver_unit|hsync_state_4\ & (!\vga_driver_unit|un11_hsync_counter_2\ # !\vga_driver_unit|un11_hsync_counter_3\ # !\vga_driver_unit|un10_hsync_counter_1\)
1164
1165 -- pragma translate_off
1166 GENERIC MAP (
1167         lut_mask => "2aaa",
1168         operation_mode => "normal",
1169         output_mode => "comb_only",
1170         register_cascade_mode => "off",
1171         sum_lutc_input => "datac",
1172         synch_mode => "off")
1173 -- pragma translate_on
1174 PORT MAP (
1175         dataa => \vga_driver_unit|hsync_state_4\,
1176         datab => \vga_driver_unit|un10_hsync_counter_1\,
1177         datac => \vga_driver_unit|un11_hsync_counter_3\,
1178         datad => \vga_driver_unit|un11_hsync_counter_2\,
1179         devclrn => ww_devclrn,
1180         devpor => ww_devpor,
1181         combout => \vga_driver_unit|hsync_state_next_1_sqmuxa_2\);
1182
1183 \vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ\ : stratix_lcell
1184 -- Equation(s):
1185 -- \vga_driver_unit|hsync_state_3_0_0_0__g0_0\ = \vga_driver_unit|un6_dly_counter_0_x\ # !\vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0\ & !\vga_driver_unit|hsync_state_next_1_sqmuxa_1\ & !\vga_driver_unit|hsync_state_next_1_sqmuxa_2\
1186
1187 -- pragma translate_off
1188 GENERIC MAP (
1189         lut_mask => "aaab",
1190         operation_mode => "normal",
1191         output_mode => "comb_only",
1192         register_cascade_mode => "off",
1193         sum_lutc_input => "datac",
1194         synch_mode => "off")
1195 -- pragma translate_on
1196 PORT MAP (
1197         dataa => \vga_driver_unit|un6_dly_counter_0_x\,
1198         datab => \vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0\,
1199         datac => \vga_driver_unit|hsync_state_next_1_sqmuxa_1\,
1200         datad => \vga_driver_unit|hsync_state_next_1_sqmuxa_2\,
1201         devclrn => ww_devclrn,
1202         devpor => ww_devpor,
1203         combout => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\);
1204
1205 \vga_driver_unit|hsync_state_2_\ : stratix_lcell
1206 -- Equation(s):
1207 -- \vga_driver_unit|hsync_state_2\ = DFFEAS(\vga_driver_unit|hsync_state_3\ & (\vga_driver_unit|un12_hsync_counter\), GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
1208
1209 -- pragma translate_off
1210 GENERIC MAP (
1211         lut_mask => "cc00",
1212         operation_mode => "normal",
1213         output_mode => "reg_only",
1214         register_cascade_mode => "off",
1215         sum_lutc_input => "datac",
1216         synch_mode => "on")
1217 -- pragma translate_on
1218 PORT MAP (
1219         clk => \clk_pin~combout\,
1220         datab => \vga_driver_unit|hsync_state_3\,
1221         datad => \vga_driver_unit|un12_hsync_counter\,
1222         aclr => GND,
1223         sclr => \vga_driver_unit|un6_dly_counter_0_x\,
1224         ena => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\,
1225         devclrn => ww_devclrn,
1226         devpor => ww_devpor,
1227         regout => \vga_driver_unit|hsync_state_2\);
1228
1229 \vga_driver_unit|hsync_state_0_\ : stratix_lcell
1230 -- Equation(s):
1231 -- \vga_driver_unit|hsync_state_0\ = DFFEAS(\vga_driver_unit|hsync_state_2\ & (\vga_driver_unit|un13_hsync_counter\), GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
1232
1233 -- pragma translate_off
1234 GENERIC MAP (
1235         lut_mask => "a0a0",
1236         operation_mode => "normal",
1237         output_mode => "reg_only",
1238         register_cascade_mode => "off",
1239         sum_lutc_input => "datac",
1240         synch_mode => "on")
1241 -- pragma translate_on
1242 PORT MAP (
1243         clk => \clk_pin~combout\,
1244         dataa => \vga_driver_unit|hsync_state_2\,
1245         datac => \vga_driver_unit|un13_hsync_counter\,
1246         aclr => GND,
1247         sclr => \vga_driver_unit|un6_dly_counter_0_x\,
1248         ena => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\,
1249         devclrn => ww_devclrn,
1250         devpor => ww_devpor,
1251         regout => \vga_driver_unit|hsync_state_0\);
1252
1253 \vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ\ : stratix_lcell
1254 -- Equation(s):
1255 -- \vga_driver_unit|hsync_counter_next_1_sqmuxa\ = \reset_pin~combout\ & dly_counter(0) & !\vga_driver_unit|d_set_hsync_counter\ & dly_counter(1)
1256
1257 -- pragma translate_off
1258 GENERIC MAP (
1259         lut_mask => "0800",
1260         operation_mode => "normal",
1261         output_mode => "comb_only",
1262         register_cascade_mode => "off",
1263         sum_lutc_input => "datac",
1264         synch_mode => "off")
1265 -- pragma translate_on
1266 PORT MAP (
1267         dataa => \reset_pin~combout\,
1268         datab => dly_counter(0),
1269         datac => \vga_driver_unit|d_set_hsync_counter\,
1270         datad => dly_counter(1),
1271         devclrn => ww_devclrn,
1272         devpor => ww_devpor,
1273         combout => \vga_driver_unit|hsync_counter_next_1_sqmuxa\);
1274
1275 \vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3\ : stratix_lcell
1276 -- Equation(s):
1277 -- \vga_driver_unit|un10_hsync_counter_3\ = !\vga_driver_unit|hsync_counter_2\ & !\vga_driver_unit|hsync_counter_7\ & !\vga_driver_unit|hsync_counter_0\
1278
1279 -- pragma translate_off
1280 GENERIC MAP (
1281         lut_mask => "0003",
1282         operation_mode => "normal",
1283         output_mode => "comb_only",
1284         register_cascade_mode => "off",
1285         sum_lutc_input => "datac",
1286         synch_mode => "off")
1287 -- pragma translate_on
1288 PORT MAP (
1289         datab => \vga_driver_unit|hsync_counter_2\,
1290         datac => \vga_driver_unit|hsync_counter_7\,
1291         datad => \vga_driver_unit|hsync_counter_0\,
1292         devclrn => ww_devclrn,
1293         devpor => ww_devpor,
1294         combout => \vga_driver_unit|un10_hsync_counter_3\);
1295
1296 \vga_driver_unit|hsync_state_4_\ : stratix_lcell
1297 -- Equation(s):
1298 -- \vga_driver_unit|hsync_state_4\ = DFFEAS(\vga_driver_unit|un10_hsync_counter_3\ & \vga_driver_unit|un10_hsync_counter_4\ & \vga_driver_unit|hsync_state_5\ & \vga_driver_unit|un10_hsync_counter_1\, GLOBAL(\clk_pin~combout\), VCC, ,
1299 -- \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
1300
1301 -- pragma translate_off
1302 GENERIC MAP (
1303         lut_mask => "8000",
1304         operation_mode => "normal",
1305         output_mode => "reg_only",
1306         register_cascade_mode => "off",
1307         sum_lutc_input => "datac",
1308         synch_mode => "on")
1309 -- pragma translate_on
1310 PORT MAP (
1311         clk => \clk_pin~combout\,
1312         dataa => \vga_driver_unit|un10_hsync_counter_3\,
1313         datab => \vga_driver_unit|un10_hsync_counter_4\,
1314         datac => \vga_driver_unit|hsync_state_5\,
1315         datad => \vga_driver_unit|un10_hsync_counter_1\,
1316         aclr => GND,
1317         sclr => \vga_driver_unit|un6_dly_counter_0_x\,
1318         ena => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\,
1319         devclrn => ww_devclrn,
1320         devpor => ww_devpor,
1321         regout => \vga_driver_unit|hsync_state_4\);
1322
1323 \vga_driver_unit|hsync_state_1_\ : stratix_lcell
1324 -- Equation(s):
1325 -- \vga_driver_unit|hsync_state_1\ = DFFEAS(\vga_driver_unit|hsync_state_4\ & \vga_driver_unit|un10_hsync_counter_1\ & \vga_driver_unit|un11_hsync_counter_3\ & \vga_driver_unit|un11_hsync_counter_2\, GLOBAL(\clk_pin~combout\), VCC, ,
1326 -- \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
1327
1328 -- pragma translate_off
1329 GENERIC MAP (
1330         lut_mask => "8000",
1331         operation_mode => "normal",
1332         output_mode => "reg_only",
1333         register_cascade_mode => "off",
1334         sum_lutc_input => "datac",
1335         synch_mode => "on")
1336 -- pragma translate_on
1337 PORT MAP (
1338         clk => \clk_pin~combout\,
1339         dataa => \vga_driver_unit|hsync_state_4\,
1340         datab => \vga_driver_unit|un10_hsync_counter_1\,
1341         datac => \vga_driver_unit|un11_hsync_counter_3\,
1342         datad => \vga_driver_unit|un11_hsync_counter_2\,
1343         aclr => GND,
1344         sclr => \vga_driver_unit|un6_dly_counter_0_x\,
1345         ena => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\,
1346         devclrn => ww_devclrn,
1347         devpor => ww_devpor,
1348         regout => \vga_driver_unit|hsync_state_1\);
1349
1350 \vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ\ : stratix_lcell
1351 -- Equation(s):
1352 -- \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\ = \reset_pin~combout\ & dly_counter(0) & dly_counter(1) & !\vga_driver_unit|hsync_state_1\
1353
1354 -- pragma translate_off
1355 GENERIC MAP (
1356         lut_mask => "0080",
1357         operation_mode => "normal",
1358         output_mode => "comb_only",
1359         register_cascade_mode => "off",
1360         sum_lutc_input => "datac",
1361         synch_mode => "off")
1362 -- pragma translate_on
1363 PORT MAP (
1364         dataa => \reset_pin~combout\,
1365         datab => dly_counter(0),
1366         datac => dly_counter(1),
1367         datad => \vga_driver_unit|hsync_state_1\,
1368         devclrn => ww_devclrn,
1369         devpor => ww_devpor,
1370         combout => \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\);
1371
1372 \vga_driver_unit|column_counter_sig_0_\ : stratix_lcell
1373 -- Equation(s):
1374 -- \vga_driver_unit|column_counter_sig_0\ = DFFEAS(!\vga_driver_unit|un10_column_counter_siglto9\ # !\vga_driver_unit|column_counter_sig_0\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, )
1375
1376 -- pragma translate_off
1377 GENERIC MAP (
1378         lut_mask => "3f3f",
1379         operation_mode => "normal",
1380         output_mode => "reg_only",
1381         register_cascade_mode => "off",
1382         sum_lutc_input => "datac",
1383         synch_mode => "on")
1384 -- pragma translate_on
1385 PORT MAP (
1386         clk => \clk_pin~combout\,
1387         datab => \vga_driver_unit|column_counter_sig_0\,
1388         datac => \vga_driver_unit|un10_column_counter_siglto9\,
1389         aclr => GND,
1390         sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\,
1391         devclrn => ww_devclrn,
1392         devpor => ww_devpor,
1393         regout => \vga_driver_unit|column_counter_sig_0\);
1394
1395 \vga_driver_unit|un2_column_counter_next_1_\ : stratix_lcell
1396 -- Equation(s):
1397 -- \vga_driver_unit|un2_column_counter_next_combout\(1) = \vga_driver_unit|column_counter_sig_0\ $ \vga_driver_unit|column_counter_sig_1\
1398 -- \vga_driver_unit|un2_column_counter_next_cout\(1) = CARRY(\vga_driver_unit|column_counter_sig_0\ & \vga_driver_unit|column_counter_sig_1\)
1399 -- \vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10\ = CARRY(\vga_driver_unit|column_counter_sig_0\ & \vga_driver_unit|column_counter_sig_1\)
1400
1401 -- pragma translate_off
1402 GENERIC MAP (
1403         lut_mask => "6688",
1404         operation_mode => "arithmetic",
1405         output_mode => "comb_only",
1406         register_cascade_mode => "off",
1407         sum_lutc_input => "datac",
1408         synch_mode => "off")
1409 -- pragma translate_on
1410 PORT MAP (
1411         dataa => \vga_driver_unit|column_counter_sig_0\,
1412         datab => \vga_driver_unit|column_counter_sig_1\,
1413         devclrn => ww_devclrn,
1414         devpor => ww_devpor,
1415         combout => \vga_driver_unit|un2_column_counter_next_combout\(1),
1416         cout0 => \vga_driver_unit|un2_column_counter_next_cout\(1),
1417         cout1 => \vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10\);
1418
1419 \vga_driver_unit|column_counter_sig_1_\ : stratix_lcell
1420 -- Equation(s):
1421 -- \vga_driver_unit|column_counter_sig_1\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(1) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, )
1422
1423 -- pragma translate_off
1424 GENERIC MAP (
1425         lut_mask => "cfcf",
1426         operation_mode => "normal",
1427         output_mode => "reg_only",
1428         register_cascade_mode => "off",
1429         sum_lutc_input => "datac",
1430         synch_mode => "on")
1431 -- pragma translate_on
1432 PORT MAP (
1433         clk => \clk_pin~combout\,
1434         datab => \vga_driver_unit|un2_column_counter_next_combout\(1),
1435         datac => \vga_driver_unit|un10_column_counter_siglto9\,
1436         aclr => GND,
1437         sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\,
1438         devclrn => ww_devclrn,
1439         devpor => ww_devpor,
1440         regout => \vga_driver_unit|column_counter_sig_1\);
1441
1442 \vga_driver_unit|un2_column_counter_next_3_\ : stratix_lcell
1443 -- Equation(s):
1444 -- \vga_driver_unit|un2_column_counter_next_combout\(3) = \vga_driver_unit|column_counter_sig_3\ $ (\vga_driver_unit|column_counter_sig_2\ & \vga_driver_unit|un2_column_counter_next_cout\(1))
1445 -- \vga_driver_unit|un2_column_counter_next_cout\(3) = CARRY(!\vga_driver_unit|un2_column_counter_next_cout\(1) # !\vga_driver_unit|column_counter_sig_3\ # !\vga_driver_unit|column_counter_sig_2\)
1446 -- \vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12\ = CARRY(!\vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10\ # !\vga_driver_unit|column_counter_sig_3\ # !\vga_driver_unit|column_counter_sig_2\)
1447
1448 -- pragma translate_off
1449 GENERIC MAP (
1450         cin0_used => "true",
1451         cin1_used => "true",
1452         lut_mask => "6c7f",
1453         operation_mode => "arithmetic",
1454         output_mode => "comb_only",
1455         register_cascade_mode => "off",
1456         sum_lutc_input => "cin",
1457         synch_mode => "off")
1458 -- pragma translate_on
1459 PORT MAP (
1460         dataa => \vga_driver_unit|column_counter_sig_2\,
1461         datab => \vga_driver_unit|column_counter_sig_3\,
1462         cin0 => \vga_driver_unit|un2_column_counter_next_cout\(1),
1463         cin1 => \vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10\,
1464         devclrn => ww_devclrn,
1465         devpor => ww_devpor,
1466         combout => \vga_driver_unit|un2_column_counter_next_combout\(3),
1467         cout0 => \vga_driver_unit|un2_column_counter_next_cout\(3),
1468         cout1 => \vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12\);
1469
1470 \vga_driver_unit|column_counter_sig_3_\ : stratix_lcell
1471 -- Equation(s):
1472 -- \vga_driver_unit|column_counter_sig_3\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(3) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, )
1473
1474 -- pragma translate_off
1475 GENERIC MAP (
1476         lut_mask => "ff0f",
1477         operation_mode => "normal",
1478         output_mode => "reg_only",
1479         register_cascade_mode => "off",
1480         sum_lutc_input => "datac",
1481         synch_mode => "on")
1482 -- pragma translate_on
1483 PORT MAP (
1484         clk => \clk_pin~combout\,
1485         datac => \vga_driver_unit|un10_column_counter_siglto9\,
1486         datad => \vga_driver_unit|un2_column_counter_next_combout\(3),
1487         aclr => GND,
1488         sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\,
1489         devclrn => ww_devclrn,
1490         devpor => ww_devpor,
1491         regout => \vga_driver_unit|column_counter_sig_3\);
1492
1493 \vga_driver_unit|un2_column_counter_next_0_\ : stratix_lcell
1494 -- Equation(s):
1495 -- \vga_driver_unit|un2_column_counter_next_cout\(0) = CARRY(\vga_driver_unit|column_counter_sig_0\ & \vga_driver_unit|column_counter_sig_1\)
1496 -- \vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18\ = CARRY(\vga_driver_unit|column_counter_sig_0\ & \vga_driver_unit|column_counter_sig_1\)
1497
1498 -- pragma translate_off
1499 GENERIC MAP (
1500         lut_mask => "ff88",
1501         operation_mode => "arithmetic",
1502         output_mode => "none",
1503         register_cascade_mode => "off",
1504         sum_lutc_input => "datac",
1505         synch_mode => "off")
1506 -- pragma translate_on
1507 PORT MAP (
1508         dataa => \vga_driver_unit|column_counter_sig_0\,
1509         datab => \vga_driver_unit|column_counter_sig_1\,
1510         devclrn => ww_devclrn,
1511         devpor => ww_devpor,
1512         combout => \vga_driver_unit|un2_column_counter_next_0_~COMBOUT\,
1513         cout0 => \vga_driver_unit|un2_column_counter_next_cout\(0),
1514         cout1 => \vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18\);
1515
1516 \vga_driver_unit|un2_column_counter_next_2_\ : stratix_lcell
1517 -- Equation(s):
1518 -- \vga_driver_unit|un2_column_counter_next_combout\(2) = \vga_driver_unit|column_counter_sig_2\ $ (\vga_driver_unit|un2_column_counter_next_cout\(0))
1519 -- \vga_driver_unit|un2_column_counter_next_cout\(2) = CARRY(!\vga_driver_unit|un2_column_counter_next_cout\(0) # !\vga_driver_unit|column_counter_sig_3\ # !\vga_driver_unit|column_counter_sig_2\)
1520 -- \vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20\ = CARRY(!\vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18\ # !\vga_driver_unit|column_counter_sig_3\ # !\vga_driver_unit|column_counter_sig_2\)
1521
1522 -- pragma translate_off
1523 GENERIC MAP (
1524         cin0_used => "true",
1525         cin1_used => "true",
1526         lut_mask => "5a7f",
1527         operation_mode => "arithmetic",
1528         output_mode => "comb_only",
1529         register_cascade_mode => "off",
1530         sum_lutc_input => "cin",
1531         synch_mode => "off")
1532 -- pragma translate_on
1533 PORT MAP (
1534         dataa => \vga_driver_unit|column_counter_sig_2\,
1535         datab => \vga_driver_unit|column_counter_sig_3\,
1536         cin0 => \vga_driver_unit|un2_column_counter_next_cout\(0),
1537         cin1 => \vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18\,
1538         devclrn => ww_devclrn,
1539         devpor => ww_devpor,
1540         combout => \vga_driver_unit|un2_column_counter_next_combout\(2),
1541         cout0 => \vga_driver_unit|un2_column_counter_next_cout\(2),
1542         cout1 => \vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20\);
1543
1544 \vga_driver_unit|column_counter_sig_2_\ : stratix_lcell
1545 -- Equation(s):
1546 -- \vga_driver_unit|column_counter_sig_2\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(2) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, )
1547
1548 -- pragma translate_off
1549 GENERIC MAP (
1550         lut_mask => "f5f5",
1551         operation_mode => "normal",
1552         output_mode => "reg_only",
1553         register_cascade_mode => "off",
1554         sum_lutc_input => "datac",
1555         synch_mode => "on")
1556 -- pragma translate_on
1557 PORT MAP (
1558         clk => \clk_pin~combout\,
1559         dataa => \vga_driver_unit|un10_column_counter_siglto9\,
1560         datac => \vga_driver_unit|un2_column_counter_next_combout\(2),
1561         aclr => GND,
1562         sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\,
1563         devclrn => ww_devclrn,
1564         devpor => ww_devpor,
1565         regout => \vga_driver_unit|column_counter_sig_2\);
1566
1567 \vga_driver_unit|un2_column_counter_next_4_\ : stratix_lcell
1568 -- Equation(s):
1569 -- \vga_driver_unit|un2_column_counter_next_combout\(4) = \vga_driver_unit|column_counter_sig_4\ $ !\vga_driver_unit|un2_column_counter_next_cout\(2)
1570 -- \vga_driver_unit|un2_column_counter_next_cout\(4) = CARRY(\vga_driver_unit|column_counter_sig_5\ & \vga_driver_unit|column_counter_sig_4\ & !\vga_driver_unit|un2_column_counter_next_cout\(2))
1571 -- \vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22\ = CARRY(\vga_driver_unit|column_counter_sig_5\ & \vga_driver_unit|column_counter_sig_4\ & !\vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20\)
1572
1573 -- pragma translate_off
1574 GENERIC MAP (
1575         cin0_used => "true",
1576         cin1_used => "true",
1577         lut_mask => "c308",
1578         operation_mode => "arithmetic",
1579         output_mode => "comb_only",
1580         register_cascade_mode => "off",
1581         sum_lutc_input => "cin",
1582         synch_mode => "off")
1583 -- pragma translate_on
1584 PORT MAP (
1585         dataa => \vga_driver_unit|column_counter_sig_5\,
1586         datab => \vga_driver_unit|column_counter_sig_4\,
1587         cin0 => \vga_driver_unit|un2_column_counter_next_cout\(2),
1588         cin1 => \vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20\,
1589         devclrn => ww_devclrn,
1590         devpor => ww_devpor,
1591         combout => \vga_driver_unit|un2_column_counter_next_combout\(4),
1592         cout0 => \vga_driver_unit|un2_column_counter_next_cout\(4),
1593         cout1 => \vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22\);
1594
1595 \vga_driver_unit|column_counter_sig_4_\ : stratix_lcell
1596 -- Equation(s):
1597 -- \vga_driver_unit|column_counter_sig_4\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(4) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, )
1598
1599 -- pragma translate_off
1600 GENERIC MAP (
1601         lut_mask => "f3f3",
1602         operation_mode => "normal",
1603         output_mode => "reg_only",
1604         register_cascade_mode => "off",
1605         sum_lutc_input => "datac",
1606         synch_mode => "on")
1607 -- pragma translate_on
1608 PORT MAP (
1609         clk => \clk_pin~combout\,
1610         datab => \vga_driver_unit|un10_column_counter_siglto9\,
1611         datac => \vga_driver_unit|un2_column_counter_next_combout\(4),
1612         aclr => GND,
1613         sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\,
1614         devclrn => ww_devclrn,
1615         devpor => ww_devpor,
1616         regout => \vga_driver_unit|column_counter_sig_4\);
1617
1618 \vga_driver_unit|un2_column_counter_next_5_\ : stratix_lcell
1619 -- Equation(s):
1620 -- \vga_driver_unit|un2_column_counter_next_combout\(5) = \vga_driver_unit|column_counter_sig_5\ $ (\vga_driver_unit|column_counter_sig_4\ & !\vga_driver_unit|un2_column_counter_next_cout\(3))
1621 -- \vga_driver_unit|un2_column_counter_next_cout\(5) = CARRY(\vga_driver_unit|column_counter_sig_5\ & \vga_driver_unit|column_counter_sig_4\ & !\vga_driver_unit|un2_column_counter_next_cout\(3))
1622 -- \vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14\ = CARRY(\vga_driver_unit|column_counter_sig_5\ & \vga_driver_unit|column_counter_sig_4\ & !\vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12\)
1623
1624 -- pragma translate_off
1625 GENERIC MAP (
1626         cin0_used => "true",
1627         cin1_used => "true",
1628         lut_mask => "a608",
1629         operation_mode => "arithmetic",
1630         output_mode => "comb_only",
1631         register_cascade_mode => "off",
1632         sum_lutc_input => "cin",
1633         synch_mode => "off")
1634 -- pragma translate_on
1635 PORT MAP (
1636         dataa => \vga_driver_unit|column_counter_sig_5\,
1637         datab => \vga_driver_unit|column_counter_sig_4\,
1638         cin0 => \vga_driver_unit|un2_column_counter_next_cout\(3),
1639         cin1 => \vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12\,
1640         devclrn => ww_devclrn,
1641         devpor => ww_devpor,
1642         combout => \vga_driver_unit|un2_column_counter_next_combout\(5),
1643         cout0 => \vga_driver_unit|un2_column_counter_next_cout\(5),
1644         cout1 => \vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14\);
1645
1646 \vga_driver_unit|column_counter_sig_5_\ : stratix_lcell
1647 -- Equation(s):
1648 -- \vga_driver_unit|column_counter_sig_5\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(5) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, )
1649
1650 -- pragma translate_off
1651 GENERIC MAP (
1652         lut_mask => "afaf",
1653         operation_mode => "normal",
1654         output_mode => "reg_only",
1655         register_cascade_mode => "off",
1656         sum_lutc_input => "datac",
1657         synch_mode => "on")
1658 -- pragma translate_on
1659 PORT MAP (
1660         clk => \clk_pin~combout\,
1661         dataa => \vga_driver_unit|un2_column_counter_next_combout\(5),
1662         datac => \vga_driver_unit|un10_column_counter_siglto9\,
1663         aclr => GND,
1664         sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\,
1665         devclrn => ww_devclrn,
1666         devpor => ww_devpor,
1667         regout => \vga_driver_unit|column_counter_sig_5\);
1668
1669 \vga_driver_unit|un2_column_counter_next_7_\ : stratix_lcell
1670 -- Equation(s):
1671 -- \vga_driver_unit|un2_column_counter_next_combout\(7) = \vga_driver_unit|column_counter_sig_7\ $ (\vga_driver_unit|column_counter_sig_6\ & \vga_driver_unit|un2_column_counter_next_cout\(5))
1672 -- \vga_driver_unit|un2_column_counter_next_cout\(7) = CARRY(!\vga_driver_unit|un2_column_counter_next_cout\(5) # !\vga_driver_unit|column_counter_sig_6\ # !\vga_driver_unit|column_counter_sig_7\)
1673 -- \vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16\ = CARRY(!\vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14\ # !\vga_driver_unit|column_counter_sig_6\ # !\vga_driver_unit|column_counter_sig_7\)
1674
1675 -- pragma translate_off
1676 GENERIC MAP (
1677         cin0_used => "true",
1678         cin1_used => "true",
1679         lut_mask => "6a7f",
1680         operation_mode => "arithmetic",
1681         output_mode => "comb_only",
1682         register_cascade_mode => "off",
1683         sum_lutc_input => "cin",
1684         synch_mode => "off")
1685 -- pragma translate_on
1686 PORT MAP (
1687         dataa => \vga_driver_unit|column_counter_sig_7\,
1688         datab => \vga_driver_unit|column_counter_sig_6\,
1689         cin0 => \vga_driver_unit|un2_column_counter_next_cout\(5),
1690         cin1 => \vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14\,
1691         devclrn => ww_devclrn,
1692         devpor => ww_devpor,
1693         combout => \vga_driver_unit|un2_column_counter_next_combout\(7),
1694         cout0 => \vga_driver_unit|un2_column_counter_next_cout\(7),
1695         cout1 => \vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16\);
1696
1697 \vga_driver_unit|column_counter_sig_7_\ : stratix_lcell
1698 -- Equation(s):
1699 -- \vga_driver_unit|column_counter_sig_7\ = DFFEAS(\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\ & (\vga_driver_unit|un10_column_counter_siglto9\ & \vga_driver_unit|un2_column_counter_next_combout\(7)), GLOBAL(\clk_pin~combout\), VCC, , , , , , )
1700
1701 -- pragma translate_off
1702 GENERIC MAP (
1703         lut_mask => "a000",
1704         operation_mode => "normal",
1705         output_mode => "reg_only",
1706         register_cascade_mode => "off",
1707         sum_lutc_input => "datac",
1708         synch_mode => "off")
1709 -- pragma translate_on
1710 PORT MAP (
1711         clk => \clk_pin~combout\,
1712         dataa => \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\,
1713         datac => \vga_driver_unit|un10_column_counter_siglto9\,
1714         datad => \vga_driver_unit|un2_column_counter_next_combout\(7),
1715         aclr => GND,
1716         devclrn => ww_devclrn,
1717         devpor => ww_devpor,
1718         regout => \vga_driver_unit|column_counter_sig_7\);
1719
1720 \vga_driver_unit|un2_column_counter_next_6_\ : stratix_lcell
1721 -- Equation(s):
1722 -- \vga_driver_unit|un2_column_counter_next_combout\(6) = \vga_driver_unit|column_counter_sig_6\ $ \vga_driver_unit|un2_column_counter_next_cout\(4)
1723 -- \vga_driver_unit|un2_column_counter_next_cout\(6) = CARRY(!\vga_driver_unit|un2_column_counter_next_cout\(4) # !\vga_driver_unit|column_counter_sig_6\ # !\vga_driver_unit|column_counter_sig_7\)
1724 -- \vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24\ = CARRY(!\vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22\ # !\vga_driver_unit|column_counter_sig_6\ # !\vga_driver_unit|column_counter_sig_7\)
1725
1726 -- pragma translate_off
1727 GENERIC MAP (
1728         cin0_used => "true",
1729         cin1_used => "true",
1730         lut_mask => "3c7f",
1731         operation_mode => "arithmetic",
1732         output_mode => "comb_only",
1733         register_cascade_mode => "off",
1734         sum_lutc_input => "cin",
1735         synch_mode => "off")
1736 -- pragma translate_on
1737 PORT MAP (
1738         dataa => \vga_driver_unit|column_counter_sig_7\,
1739         datab => \vga_driver_unit|column_counter_sig_6\,
1740         cin0 => \vga_driver_unit|un2_column_counter_next_cout\(4),
1741         cin1 => \vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22\,
1742         devclrn => ww_devclrn,
1743         devpor => ww_devpor,
1744         combout => \vga_driver_unit|un2_column_counter_next_combout\(6),
1745         cout0 => \vga_driver_unit|un2_column_counter_next_cout\(6),
1746         cout1 => \vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24\);
1747
1748 \vga_driver_unit|un2_column_counter_next_8_\ : stratix_lcell
1749 -- Equation(s):
1750 -- \vga_driver_unit|un2_column_counter_next_combout\(8) = \vga_driver_unit|un2_column_counter_next_cout\(6) $ !\vga_driver_unit|column_counter_sig_8\
1751
1752 -- pragma translate_off
1753 GENERIC MAP (
1754         cin0_used => "true",
1755         cin1_used => "true",
1756         lut_mask => "f00f",
1757         operation_mode => "normal",
1758         output_mode => "comb_only",
1759         register_cascade_mode => "off",
1760         sum_lutc_input => "cin",
1761         synch_mode => "off")
1762 -- pragma translate_on
1763 PORT MAP (
1764         datad => \vga_driver_unit|column_counter_sig_8\,
1765         cin0 => \vga_driver_unit|un2_column_counter_next_cout\(6),
1766         cin1 => \vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24\,
1767         devclrn => ww_devclrn,
1768         devpor => ww_devpor,
1769         combout => \vga_driver_unit|un2_column_counter_next_combout\(8));
1770
1771 \vga_driver_unit|column_counter_sig_8_\ : stratix_lcell
1772 -- Equation(s):
1773 -- \vga_driver_unit|column_counter_sig_8\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(8) & (\vga_driver_unit|un10_column_counter_siglto9\ & \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\), GLOBAL(\clk_pin~combout\), VCC, , , , , , )
1774
1775 -- pragma translate_off
1776 GENERIC MAP (
1777         lut_mask => "a000",
1778         operation_mode => "normal",
1779         output_mode => "reg_only",
1780         register_cascade_mode => "off",
1781         sum_lutc_input => "datac",
1782         synch_mode => "off")
1783 -- pragma translate_on
1784 PORT MAP (
1785         clk => \clk_pin~combout\,
1786         dataa => \vga_driver_unit|un2_column_counter_next_combout\(8),
1787         datac => \vga_driver_unit|un10_column_counter_siglto9\,
1788         datad => \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\,
1789         aclr => GND,
1790         devclrn => ww_devclrn,
1791         devpor => ww_devpor,
1792         regout => \vga_driver_unit|column_counter_sig_8\);
1793
1794 \vga_driver_unit|un2_column_counter_next_9_\ : stratix_lcell
1795 -- Equation(s):
1796 -- \vga_driver_unit|un2_column_counter_next_combout\(9) = \vga_driver_unit|column_counter_sig_9\ $ (\vga_driver_unit|column_counter_sig_8\ & !\vga_driver_unit|un2_column_counter_next_cout\(7))
1797
1798 -- pragma translate_off
1799 GENERIC MAP (
1800         cin0_used => "true",
1801         cin1_used => "true",
1802         lut_mask => "f30c",
1803         operation_mode => "normal",
1804         output_mode => "comb_only",
1805         register_cascade_mode => "off",
1806         sum_lutc_input => "cin",
1807         synch_mode => "off")
1808 -- pragma translate_on
1809 PORT MAP (
1810         datab => \vga_driver_unit|column_counter_sig_8\,
1811         datad => \vga_driver_unit|column_counter_sig_9\,
1812         cin0 => \vga_driver_unit|un2_column_counter_next_cout\(7),
1813         cin1 => \vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16\,
1814         devclrn => ww_devclrn,
1815         devpor => ww_devpor,
1816         combout => \vga_driver_unit|un2_column_counter_next_combout\(9));
1817
1818 \vga_driver_unit|column_counter_sig_9_\ : stratix_lcell
1819 -- Equation(s):
1820 -- \vga_driver_unit|column_counter_sig_9\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(9) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, )
1821
1822 -- pragma translate_off
1823 GENERIC MAP (
1824         lut_mask => "ff0f",
1825         operation_mode => "normal",
1826         output_mode => "reg_only",
1827         register_cascade_mode => "off",
1828         sum_lutc_input => "datac",
1829         synch_mode => "on")
1830 -- pragma translate_on
1831 PORT MAP (
1832         clk => \clk_pin~combout\,
1833         datac => \vga_driver_unit|un10_column_counter_siglto9\,
1834         datad => \vga_driver_unit|un2_column_counter_next_combout\(9),
1835         aclr => GND,
1836         sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\,
1837         devclrn => ww_devclrn,
1838         devpor => ww_devpor,
1839         regout => \vga_driver_unit|column_counter_sig_9\);
1840
1841 \vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_1\ : stratix_lcell
1842 -- Equation(s):
1843 -- \vga_driver_unit|un10_column_counter_siglt6_1\ = !\vga_driver_unit|column_counter_sig_2\ # !\vga_driver_unit|column_counter_sig_1\ # !\vga_driver_unit|column_counter_sig_0\
1844
1845 -- pragma translate_off
1846 GENERIC MAP (
1847         lut_mask => "3fff",
1848         operation_mode => "normal",
1849         output_mode => "comb_only",
1850         register_cascade_mode => "off",
1851         sum_lutc_input => "datac",
1852         synch_mode => "off")
1853 -- pragma translate_on
1854 PORT MAP (
1855         datab => \vga_driver_unit|column_counter_sig_0\,
1856         datac => \vga_driver_unit|column_counter_sig_1\,
1857         datad => \vga_driver_unit|column_counter_sig_2\,
1858         devclrn => ww_devclrn,
1859         devpor => ww_devpor,
1860         combout => \vga_driver_unit|un10_column_counter_siglt6_1\);
1861
1862 \vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6\ : stratix_lcell
1863 -- Equation(s):
1864 -- \vga_driver_unit|un10_column_counter_siglt6\ = \vga_driver_unit|un10_column_counter_siglt6_3\ # \vga_driver_unit|un10_column_counter_siglt6_1\ # !\vga_driver_unit|column_counter_sig_4\ # !\vga_driver_unit|column_counter_sig_3\
1865
1866 -- pragma translate_off
1867 GENERIC MAP (
1868         lut_mask => "fdff",
1869         operation_mode => "normal",
1870         output_mode => "comb_only",
1871         register_cascade_mode => "off",
1872         sum_lutc_input => "datac",
1873         synch_mode => "off")
1874 -- pragma translate_on
1875 PORT MAP (
1876         dataa => \vga_driver_unit|column_counter_sig_3\,
1877         datab => \vga_driver_unit|un10_column_counter_siglt6_3\,
1878         datac => \vga_driver_unit|un10_column_counter_siglt6_1\,
1879         datad => \vga_driver_unit|column_counter_sig_4\,
1880         devclrn => ww_devclrn,
1881         devpor => ww_devpor,
1882         combout => \vga_driver_unit|un10_column_counter_siglt6\);
1883
1884 \vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9\ : stratix_lcell
1885 -- Equation(s):
1886 -- \vga_driver_unit|un10_column_counter_siglto9\ = !\vga_driver_unit|column_counter_sig_8\ & !\vga_driver_unit|column_counter_sig_7\ & \vga_driver_unit|un10_column_counter_siglt6\ # !\vga_driver_unit|column_counter_sig_9\
1887
1888 -- pragma translate_off
1889 GENERIC MAP (
1890         lut_mask => "1f0f",
1891         operation_mode => "normal",
1892         output_mode => "comb_only",
1893         register_cascade_mode => "off",
1894         sum_lutc_input => "datac",
1895         synch_mode => "off")
1896 -- pragma translate_on
1897 PORT MAP (
1898         dataa => \vga_driver_unit|column_counter_sig_8\,
1899         datab => \vga_driver_unit|column_counter_sig_7\,
1900         datac => \vga_driver_unit|column_counter_sig_9\,
1901         datad => \vga_driver_unit|un10_column_counter_siglt6\,
1902         devclrn => ww_devclrn,
1903         devpor => ww_devpor,
1904         combout => \vga_driver_unit|un10_column_counter_siglto9\);
1905
1906 \vga_driver_unit|column_counter_sig_6_\ : stratix_lcell
1907 -- Equation(s):
1908 -- \vga_driver_unit|column_counter_sig_6\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(6) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, )
1909
1910 -- pragma translate_off
1911 GENERIC MAP (
1912         lut_mask => "f3f3",
1913         operation_mode => "normal",
1914         output_mode => "reg_only",
1915         register_cascade_mode => "off",
1916         sum_lutc_input => "datac",
1917         synch_mode => "on")
1918 -- pragma translate_on
1919 PORT MAP (
1920         clk => \clk_pin~combout\,
1921         datab => \vga_driver_unit|un10_column_counter_siglto9\,
1922         datac => \vga_driver_unit|un2_column_counter_next_combout\(6),
1923         aclr => GND,
1924         sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\,
1925         devclrn => ww_devclrn,
1926         devpor => ww_devpor,
1927         regout => \vga_driver_unit|column_counter_sig_6\);
1928
1929 \vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_3\ : stratix_lcell
1930 -- Equation(s):
1931 -- \vga_driver_unit|un10_column_counter_siglt6_3\ = !\vga_driver_unit|column_counter_sig_5\ # !\vga_driver_unit|column_counter_sig_6\
1932
1933 -- pragma translate_off
1934 GENERIC MAP (
1935         lut_mask => "0fff",
1936         operation_mode => "normal",
1937         output_mode => "comb_only",
1938         register_cascade_mode => "off",
1939         sum_lutc_input => "datac",
1940         synch_mode => "off")
1941 -- pragma translate_on
1942 PORT MAP (
1943         datac => \vga_driver_unit|column_counter_sig_6\,
1944         datad => \vga_driver_unit|column_counter_sig_5\,
1945         devclrn => ww_devclrn,
1946         devpor => ww_devpor,
1947         combout => \vga_driver_unit|un10_column_counter_siglt6_3\);
1948
1949 \vga_control_unit|b_next_i_o3_0_cZ\ : stratix_lcell
1950 -- Equation(s):
1951 -- \vga_control_unit|b_next_i_o3_0\ = \vga_driver_unit|column_counter_sig_7\ # \vga_driver_unit|column_counter_sig_5\ & \vga_driver_unit|column_counter_sig_6\ & \vga_driver_unit|column_counter_sig_4\
1952
1953 -- pragma translate_off
1954 GENERIC MAP (
1955         lut_mask => "f8f0",
1956         operation_mode => "normal",
1957         output_mode => "comb_only",
1958         register_cascade_mode => "off",
1959         sum_lutc_input => "datac",
1960         synch_mode => "off")
1961 -- pragma translate_on
1962 PORT MAP (
1963         dataa => \vga_driver_unit|column_counter_sig_5\,
1964         datab => \vga_driver_unit|column_counter_sig_6\,
1965         datac => \vga_driver_unit|column_counter_sig_7\,
1966         datad => \vga_driver_unit|column_counter_sig_4\,
1967         devclrn => ww_devclrn,
1968         devpor => ww_devpor,
1969         combout => \vga_control_unit|b_next_i_o3_0\);
1970
1971 \vga_control_unit|g_next_i_o3_cZ\ : stratix_lcell
1972 -- Equation(s):
1973 -- \vga_control_unit|g_next_i_o3\ = \vga_driver_unit|column_counter_sig_4\ # \vga_driver_unit|column_counter_sig_3\
1974
1975 -- pragma translate_off
1976 GENERIC MAP (
1977         lut_mask => "ffaa",
1978         operation_mode => "normal",
1979         output_mode => "comb_only",
1980         register_cascade_mode => "off",
1981         sum_lutc_input => "datac",
1982         synch_mode => "off")
1983 -- pragma translate_on
1984 PORT MAP (
1985         dataa => \vga_driver_unit|column_counter_sig_4\,
1986         datad => \vga_driver_unit|column_counter_sig_3\,
1987         devclrn => ww_devclrn,
1988         devpor => ww_devpor,
1989         combout => \vga_control_unit|g_next_i_o3\);
1990
1991 \vga_driver_unit|vsync_counter_0_\ : stratix_lcell
1992 -- Equation(s):
1993 -- \vga_driver_unit|vsync_counter_0\ = DFFEAS(\vga_driver_unit|d_set_hsync_counter\ $ \vga_driver_unit|vsync_counter_0\, GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\,
1994 -- !\vga_driver_unit|un9_vsync_counterlt9\)
1995 -- \vga_driver_unit|vsync_counter_cout\(0) = CARRY(\vga_driver_unit|d_set_hsync_counter\ & \vga_driver_unit|vsync_counter_0\)
1996 -- \vga_driver_unit|vsync_counter_cout[0]~COUT1_10\ = CARRY(\vga_driver_unit|d_set_hsync_counter\ & \vga_driver_unit|vsync_counter_0\)
1997
1998 -- pragma translate_off
1999 GENERIC MAP (
2000         lut_mask => "6688",
2001         operation_mode => "arithmetic",
2002         output_mode => "reg_only",
2003         register_cascade_mode => "off",
2004         sum_lutc_input => "datac",
2005         synch_mode => "on")
2006 -- pragma translate_on
2007 PORT MAP (
2008         clk => \clk_pin~combout\,
2009         dataa => \vga_driver_unit|d_set_hsync_counter\,
2010         datab => \vga_driver_unit|vsync_counter_0\,
2011         datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
2012         aclr => GND,
2013         sclr => \vga_driver_unit|ALT_INV_G_16_i\,
2014         sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
2015         devclrn => ww_devclrn,
2016         devpor => ww_devpor,
2017         regout => \vga_driver_unit|vsync_counter_0\,
2018         cout0 => \vga_driver_unit|vsync_counter_cout\(0),
2019         cout1 => \vga_driver_unit|vsync_counter_cout[0]~COUT1_10\);
2020
2021 \vga_driver_unit|vsync_counter_1_\ : stratix_lcell
2022 -- Equation(s):
2023 -- \vga_driver_unit|vsync_counter_1\ = DFFEAS(\vga_driver_unit|vsync_counter_1\ $ \vga_driver_unit|vsync_counter_cout\(0), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\,
2024 -- !\vga_driver_unit|un9_vsync_counterlt9\)
2025 -- \vga_driver_unit|vsync_counter_cout\(1) = CARRY(!\vga_driver_unit|vsync_counter_cout\(0) # !\vga_driver_unit|vsync_counter_1\)
2026 -- \vga_driver_unit|vsync_counter_cout[1]~COUT1_12\ = CARRY(!\vga_driver_unit|vsync_counter_cout[0]~COUT1_10\ # !\vga_driver_unit|vsync_counter_1\)
2027
2028 -- pragma translate_off
2029 GENERIC MAP (
2030         cin0_used => "true",
2031         cin1_used => "true",
2032         lut_mask => "3c3f",
2033         operation_mode => "arithmetic",
2034         output_mode => "reg_only",
2035         register_cascade_mode => "off",
2036         sum_lutc_input => "cin",
2037         synch_mode => "on")
2038 -- pragma translate_on
2039 PORT MAP (
2040         clk => \clk_pin~combout\,
2041         datab => \vga_driver_unit|vsync_counter_1\,
2042         datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
2043         aclr => GND,
2044         sclr => \vga_driver_unit|ALT_INV_G_16_i\,
2045         sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
2046         cin0 => \vga_driver_unit|vsync_counter_cout\(0),
2047         cin1 => \vga_driver_unit|vsync_counter_cout[0]~COUT1_10\,
2048         devclrn => ww_devclrn,
2049         devpor => ww_devpor,
2050         regout => \vga_driver_unit|vsync_counter_1\,
2051         cout0 => \vga_driver_unit|vsync_counter_cout\(1),
2052         cout1 => \vga_driver_unit|vsync_counter_cout[1]~COUT1_12\);
2053
2054 \vga_driver_unit|vsync_counter_2_\ : stratix_lcell
2055 -- Equation(s):
2056 -- \vga_driver_unit|vsync_counter_2\ = DFFEAS(\vga_driver_unit|vsync_counter_2\ $ (!\vga_driver_unit|vsync_counter_cout\(1)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\,
2057 -- !\vga_driver_unit|un9_vsync_counterlt9\)
2058 -- \vga_driver_unit|vsync_counter_cout\(2) = CARRY(\vga_driver_unit|vsync_counter_2\ & (!\vga_driver_unit|vsync_counter_cout\(1)))
2059 -- \vga_driver_unit|vsync_counter_cout[2]~COUT1_14\ = CARRY(\vga_driver_unit|vsync_counter_2\ & (!\vga_driver_unit|vsync_counter_cout[1]~COUT1_12\))
2060
2061 -- pragma translate_off
2062 GENERIC MAP (
2063         cin0_used => "true",
2064         cin1_used => "true",
2065         lut_mask => "a50a",
2066         operation_mode => "arithmetic",
2067         output_mode => "reg_only",
2068         register_cascade_mode => "off",
2069         sum_lutc_input => "cin",
2070         synch_mode => "on")
2071 -- pragma translate_on
2072 PORT MAP (
2073         clk => \clk_pin~combout\,
2074         dataa => \vga_driver_unit|vsync_counter_2\,
2075         datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
2076         aclr => GND,
2077         sclr => \vga_driver_unit|ALT_INV_G_16_i\,
2078         sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
2079         cin0 => \vga_driver_unit|vsync_counter_cout\(1),
2080         cin1 => \vga_driver_unit|vsync_counter_cout[1]~COUT1_12\,
2081         devclrn => ww_devclrn,
2082         devpor => ww_devpor,
2083         regout => \vga_driver_unit|vsync_counter_2\,
2084         cout0 => \vga_driver_unit|vsync_counter_cout\(2),
2085         cout1 => \vga_driver_unit|vsync_counter_cout[2]~COUT1_14\);
2086
2087 \vga_driver_unit|vsync_counter_3_\ : stratix_lcell
2088 -- Equation(s):
2089 -- \vga_driver_unit|vsync_counter_3\ = DFFEAS(\vga_driver_unit|vsync_counter_3\ $ (\vga_driver_unit|vsync_counter_cout\(2)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\,
2090 -- !\vga_driver_unit|un9_vsync_counterlt9\)
2091 -- \vga_driver_unit|vsync_counter_cout\(3) = CARRY(!\vga_driver_unit|vsync_counter_cout\(2) # !\vga_driver_unit|vsync_counter_3\)
2092 -- \vga_driver_unit|vsync_counter_cout[3]~COUT1_16\ = CARRY(!\vga_driver_unit|vsync_counter_cout[2]~COUT1_14\ # !\vga_driver_unit|vsync_counter_3\)
2093
2094 -- pragma translate_off
2095 GENERIC MAP (
2096         cin0_used => "true",
2097         cin1_used => "true",
2098         lut_mask => "5a5f",
2099         operation_mode => "arithmetic",
2100         output_mode => "reg_only",
2101         register_cascade_mode => "off",
2102         sum_lutc_input => "cin",
2103         synch_mode => "on")
2104 -- pragma translate_on
2105 PORT MAP (
2106         clk => \clk_pin~combout\,
2107         dataa => \vga_driver_unit|vsync_counter_3\,
2108         datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
2109         aclr => GND,
2110         sclr => \vga_driver_unit|ALT_INV_G_16_i\,
2111         sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
2112         cin0 => \vga_driver_unit|vsync_counter_cout\(2),
2113         cin1 => \vga_driver_unit|vsync_counter_cout[2]~COUT1_14\,
2114         devclrn => ww_devclrn,
2115         devpor => ww_devpor,
2116         regout => \vga_driver_unit|vsync_counter_3\,
2117         cout0 => \vga_driver_unit|vsync_counter_cout\(3),
2118         cout1 => \vga_driver_unit|vsync_counter_cout[3]~COUT1_16\);
2119
2120 \vga_driver_unit|vsync_counter_4_\ : stratix_lcell
2121 -- Equation(s):
2122 -- \vga_driver_unit|vsync_counter_4\ = DFFEAS(\vga_driver_unit|vsync_counter_4\ $ (!\vga_driver_unit|vsync_counter_cout\(3)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\,
2123 -- !\vga_driver_unit|un9_vsync_counterlt9\)
2124 -- \vga_driver_unit|vsync_counter_cout\(4) = CARRY(\vga_driver_unit|vsync_counter_4\ & (!\vga_driver_unit|vsync_counter_cout[3]~COUT1_16\))
2125
2126 -- pragma translate_off
2127 GENERIC MAP (
2128         cin0_used => "true",
2129         cin1_used => "true",
2130         lut_mask => "a50a",
2131         operation_mode => "arithmetic",
2132         output_mode => "reg_only",
2133         register_cascade_mode => "off",
2134         sum_lutc_input => "cin",
2135         synch_mode => "on")
2136 -- pragma translate_on
2137 PORT MAP (
2138         clk => \clk_pin~combout\,
2139         dataa => \vga_driver_unit|vsync_counter_4\,
2140         datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
2141         aclr => GND,
2142         sclr => \vga_driver_unit|ALT_INV_G_16_i\,
2143         sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
2144         cin0 => \vga_driver_unit|vsync_counter_cout\(3),
2145         cin1 => \vga_driver_unit|vsync_counter_cout[3]~COUT1_16\,
2146         devclrn => ww_devclrn,
2147         devpor => ww_devpor,
2148         regout => \vga_driver_unit|vsync_counter_4\,
2149         cout => \vga_driver_unit|vsync_counter_cout\(4));
2150
2151 \vga_driver_unit|vsync_counter_5_\ : stratix_lcell
2152 -- Equation(s):
2153 -- \vga_driver_unit|vsync_counter_5\ = DFFEAS(\vga_driver_unit|vsync_counter_5\ $ \vga_driver_unit|vsync_counter_cout\(4), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\,
2154 -- !\vga_driver_unit|un9_vsync_counterlt9\)
2155 -- \vga_driver_unit|vsync_counter_cout\(5) = CARRY(!\vga_driver_unit|vsync_counter_cout\(4) # !\vga_driver_unit|vsync_counter_5\)
2156 -- \vga_driver_unit|vsync_counter_cout[5]~COUT1_18\ = CARRY(!\vga_driver_unit|vsync_counter_cout\(4) # !\vga_driver_unit|vsync_counter_5\)
2157
2158 -- pragma translate_off
2159 GENERIC MAP (
2160         cin_used => "true",
2161         lut_mask => "3c3f",
2162         operation_mode => "arithmetic",
2163         output_mode => "reg_only",
2164         register_cascade_mode => "off",
2165         sum_lutc_input => "cin",
2166         synch_mode => "on")
2167 -- pragma translate_on
2168 PORT MAP (
2169         clk => \clk_pin~combout\,
2170         datab => \vga_driver_unit|vsync_counter_5\,
2171         datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
2172         aclr => GND,
2173         sclr => \vga_driver_unit|ALT_INV_G_16_i\,
2174         sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
2175         cin => \vga_driver_unit|vsync_counter_cout\(4),
2176         devclrn => ww_devclrn,
2177         devpor => ww_devpor,
2178         regout => \vga_driver_unit|vsync_counter_5\,
2179         cout0 => \vga_driver_unit|vsync_counter_cout\(5),
2180         cout1 => \vga_driver_unit|vsync_counter_cout[5]~COUT1_18\);
2181
2182 \vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6\ : stratix_lcell
2183 -- Equation(s):
2184 -- \vga_driver_unit|un9_vsync_counterlt9_6\ = !\vga_driver_unit|vsync_counter_1\ # !\vga_driver_unit|vsync_counter_2\ # !\vga_driver_unit|vsync_counter_3\ # !\vga_driver_unit|vsync_counter_0\
2185
2186 -- pragma translate_off
2187 GENERIC MAP (
2188         lut_mask => "7fff",
2189         operation_mode => "normal",
2190         output_mode => "comb_only",
2191         register_cascade_mode => "off",
2192         sum_lutc_input => "datac",
2193         synch_mode => "off")
2194 -- pragma translate_on
2195 PORT MAP (
2196         dataa => \vga_driver_unit|vsync_counter_0\,
2197         datab => \vga_driver_unit|vsync_counter_3\,
2198         datac => \vga_driver_unit|vsync_counter_2\,
2199         datad => \vga_driver_unit|vsync_counter_1\,
2200         devclrn => ww_devclrn,
2201         devpor => ww_devpor,
2202         combout => \vga_driver_unit|un9_vsync_counterlt9_6\);
2203
2204 \vga_driver_unit|vsync_counter_6_\ : stratix_lcell
2205 -- Equation(s):
2206 -- \vga_driver_unit|vsync_counter_6\ = DFFEAS(\vga_driver_unit|vsync_counter_6\ $ !(!\vga_driver_unit|vsync_counter_cout\(4) & \vga_driver_unit|vsync_counter_cout\(5)) # (\vga_driver_unit|vsync_counter_cout\(4) &
2207 -- \vga_driver_unit|vsync_counter_cout[5]~COUT1_18\), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\, !\vga_driver_unit|un9_vsync_counterlt9\)
2208 -- \vga_driver_unit|vsync_counter_cout\(6) = CARRY(\vga_driver_unit|vsync_counter_6\ & !\vga_driver_unit|vsync_counter_cout\(5))
2209 -- \vga_driver_unit|vsync_counter_cout[6]~COUT1_20\ = CARRY(\vga_driver_unit|vsync_counter_6\ & !\vga_driver_unit|vsync_counter_cout[5]~COUT1_18\)
2210
2211 -- pragma translate_off
2212 GENERIC MAP (
2213         cin0_used => "true",
2214         cin1_used => "true",
2215         cin_used => "true",
2216         lut_mask => "c30c",
2217         operation_mode => "arithmetic",
2218         output_mode => "reg_only",
2219         register_cascade_mode => "off",
2220         sum_lutc_input => "cin",
2221         synch_mode => "on")
2222 -- pragma translate_on
2223 PORT MAP (
2224         clk => \clk_pin~combout\,
2225         datab => \vga_driver_unit|vsync_counter_6\,
2226         datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
2227         aclr => GND,
2228         sclr => \vga_driver_unit|ALT_INV_G_16_i\,
2229         sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
2230         cin => \vga_driver_unit|vsync_counter_cout\(4),
2231         cin0 => \vga_driver_unit|vsync_counter_cout\(5),
2232         cin1 => \vga_driver_unit|vsync_counter_cout[5]~COUT1_18\,
2233         devclrn => ww_devclrn,
2234         devpor => ww_devpor,
2235         regout => \vga_driver_unit|vsync_counter_6\,
2236         cout0 => \vga_driver_unit|vsync_counter_cout\(6),
2237         cout1 => \vga_driver_unit|vsync_counter_cout[6]~COUT1_20\);
2238
2239 \vga_driver_unit|vsync_counter_7_\ : stratix_lcell
2240 -- Equation(s):
2241 -- \vga_driver_unit|vsync_counter_7\ = DFFEAS(\vga_driver_unit|vsync_counter_7\ $ ((!\vga_driver_unit|vsync_counter_cout\(4) & \vga_driver_unit|vsync_counter_cout\(6)) # (\vga_driver_unit|vsync_counter_cout\(4) &
2242 -- \vga_driver_unit|vsync_counter_cout[6]~COUT1_20\)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\, !\vga_driver_unit|un9_vsync_counterlt9\)
2243 -- \vga_driver_unit|vsync_counter_cout\(7) = CARRY(!\vga_driver_unit|vsync_counter_cout\(6) # !\vga_driver_unit|vsync_counter_7\)
2244 -- \vga_driver_unit|vsync_counter_cout[7]~COUT1_22\ = CARRY(!\vga_driver_unit|vsync_counter_cout[6]~COUT1_20\ # !\vga_driver_unit|vsync_counter_7\)
2245
2246 -- pragma translate_off
2247 GENERIC MAP (
2248         cin0_used => "true",
2249         cin1_used => "true",
2250         cin_used => "true",
2251         lut_mask => "5a5f",
2252         operation_mode => "arithmetic",
2253         output_mode => "reg_only",
2254         register_cascade_mode => "off",
2255         sum_lutc_input => "cin",
2256         synch_mode => "on")
2257 -- pragma translate_on
2258 PORT MAP (
2259         clk => \clk_pin~combout\,
2260         dataa => \vga_driver_unit|vsync_counter_7\,
2261         datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
2262         aclr => GND,
2263         sclr => \vga_driver_unit|ALT_INV_G_16_i\,
2264         sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
2265         cin => \vga_driver_unit|vsync_counter_cout\(4),
2266         cin0 => \vga_driver_unit|vsync_counter_cout\(6),
2267         cin1 => \vga_driver_unit|vsync_counter_cout[6]~COUT1_20\,
2268         devclrn => ww_devclrn,
2269         devpor => ww_devpor,
2270         regout => \vga_driver_unit|vsync_counter_7\,
2271         cout0 => \vga_driver_unit|vsync_counter_cout\(7),
2272         cout1 => \vga_driver_unit|vsync_counter_cout[7]~COUT1_22\);
2273
2274 \vga_driver_unit|vsync_counter_8_\ : stratix_lcell
2275 -- Equation(s):
2276 -- \vga_driver_unit|vsync_counter_8\ = DFFEAS(\vga_driver_unit|vsync_counter_8\ $ (!(!\vga_driver_unit|vsync_counter_cout\(4) & \vga_driver_unit|vsync_counter_cout\(7)) # (\vga_driver_unit|vsync_counter_cout\(4) &
2277 -- \vga_driver_unit|vsync_counter_cout[7]~COUT1_22\)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\, !\vga_driver_unit|un9_vsync_counterlt9\)
2278 -- \vga_driver_unit|vsync_counter_cout\(8) = CARRY(\vga_driver_unit|vsync_counter_8\ & (!\vga_driver_unit|vsync_counter_cout\(7)))
2279 -- \vga_driver_unit|vsync_counter_cout[8]~COUT1_24\ = CARRY(\vga_driver_unit|vsync_counter_8\ & (!\vga_driver_unit|vsync_counter_cout[7]~COUT1_22\))
2280
2281 -- pragma translate_off
2282 GENERIC MAP (
2283         cin0_used => "true",
2284         cin1_used => "true",
2285         cin_used => "true",
2286         lut_mask => "a50a",
2287         operation_mode => "arithmetic",
2288         output_mode => "reg_only",
2289         register_cascade_mode => "off",
2290         sum_lutc_input => "cin",
2291         synch_mode => "on")
2292 -- pragma translate_on
2293 PORT MAP (
2294         clk => \clk_pin~combout\,
2295         dataa => \vga_driver_unit|vsync_counter_8\,
2296         datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
2297         aclr => GND,
2298         sclr => \vga_driver_unit|ALT_INV_G_16_i\,
2299         sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
2300         cin => \vga_driver_unit|vsync_counter_cout\(4),
2301         cin0 => \vga_driver_unit|vsync_counter_cout\(7),
2302         cin1 => \vga_driver_unit|vsync_counter_cout[7]~COUT1_22\,
2303         devclrn => ww_devclrn,
2304         devpor => ww_devpor,
2305         regout => \vga_driver_unit|vsync_counter_8\,
2306         cout0 => \vga_driver_unit|vsync_counter_cout\(8),
2307         cout1 => \vga_driver_unit|vsync_counter_cout[8]~COUT1_24\);
2308
2309 \vga_driver_unit|vsync_counter_9_\ : stratix_lcell
2310 -- Equation(s):
2311 -- \vga_driver_unit|vsync_counter_9\ = DFFEAS((!\vga_driver_unit|vsync_counter_cout\(4) & \vga_driver_unit|vsync_counter_cout\(8)) # (\vga_driver_unit|vsync_counter_cout\(4) & \vga_driver_unit|vsync_counter_cout[8]~COUT1_24\) $
2312 -- \vga_driver_unit|vsync_counter_9\, GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\, !\vga_driver_unit|un9_vsync_counterlt9\)
2313
2314 -- pragma translate_off
2315 GENERIC MAP (
2316         cin0_used => "true",
2317         cin1_used => "true",
2318         cin_used => "true",
2319         lut_mask => "0ff0",
2320         operation_mode => "normal",
2321         output_mode => "reg_only",
2322         register_cascade_mode => "off",
2323         sum_lutc_input => "cin",
2324         synch_mode => "on")
2325 -- pragma translate_on
2326 PORT MAP (
2327         clk => \clk_pin~combout\,
2328         datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
2329         datad => \vga_driver_unit|vsync_counter_9\,
2330         aclr => GND,
2331         sclr => \vga_driver_unit|ALT_INV_G_16_i\,
2332         sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
2333         cin => \vga_driver_unit|vsync_counter_cout\(4),
2334         cin0 => \vga_driver_unit|vsync_counter_cout\(8),
2335         cin1 => \vga_driver_unit|vsync_counter_cout[8]~COUT1_24\,
2336         devclrn => ww_devclrn,
2337         devpor => ww_devpor,
2338         regout => \vga_driver_unit|vsync_counter_9\);
2339
2340 \vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5\ : stratix_lcell
2341 -- Equation(s):
2342 -- \vga_driver_unit|un9_vsync_counterlt9_5\ = !\vga_driver_unit|vsync_counter_7\ # !\vga_driver_unit|vsync_counter_9\ # !\vga_driver_unit|vsync_counter_6\ # !\vga_driver_unit|vsync_counter_8\
2343
2344 -- pragma translate_off
2345 GENERIC MAP (
2346         lut_mask => "7fff",
2347         operation_mode => "normal",
2348         output_mode => "comb_only",
2349         register_cascade_mode => "off",
2350         sum_lutc_input => "datac",
2351         synch_mode => "off")
2352 -- pragma translate_on
2353 PORT MAP (
2354         dataa => \vga_driver_unit|vsync_counter_8\,
2355         datab => \vga_driver_unit|vsync_counter_6\,
2356         datac => \vga_driver_unit|vsync_counter_9\,
2357         datad => \vga_driver_unit|vsync_counter_7\,
2358         devclrn => ww_devclrn,
2359         devpor => ww_devpor,
2360         combout => \vga_driver_unit|un9_vsync_counterlt9_5\);
2361
2362 \vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9\ : stratix_lcell
2363 -- Equation(s):
2364 -- \vga_driver_unit|un9_vsync_counterlt9\ = \vga_driver_unit|un9_vsync_counterlt9_6\ # \vga_driver_unit|un9_vsync_counterlt9_5\ # !\vga_driver_unit|vsync_counter_4\ # !\vga_driver_unit|vsync_counter_5\
2365
2366 -- pragma translate_off
2367 GENERIC MAP (
2368         lut_mask => "ffdf",
2369         operation_mode => "normal",
2370         output_mode => "comb_only",
2371         register_cascade_mode => "off",
2372         sum_lutc_input => "datac",
2373         synch_mode => "off")
2374 -- pragma translate_on
2375 PORT MAP (
2376         dataa => \vga_driver_unit|vsync_counter_5\,
2377         datab => \vga_driver_unit|un9_vsync_counterlt9_6\,
2378         datac => \vga_driver_unit|vsync_counter_4\,
2379         datad => \vga_driver_unit|un9_vsync_counterlt9_5\,
2380         devclrn => ww_devclrn,
2381         devpor => ww_devpor,
2382         combout => \vga_driver_unit|un9_vsync_counterlt9\);
2383
2384 \vga_driver_unit|G_16\ : stratix_lcell
2385 -- Equation(s):
2386 -- \vga_driver_unit|G_16_i\ = !\vga_driver_unit|un6_dly_counter_0_x\ & !\vga_driver_unit|vsync_state_6\ & !\vga_driver_unit|vsync_state_0\ # !\vga_driver_unit|un9_vsync_counterlt9\
2387
2388 -- pragma translate_off
2389 GENERIC MAP (
2390         lut_mask => "01ff",
2391         operation_mode => "normal",
2392         output_mode => "comb_only",
2393         register_cascade_mode => "off",
2394         sum_lutc_input => "datac",
2395         synch_mode => "off")
2396 -- pragma translate_on
2397 PORT MAP (
2398         dataa => \vga_driver_unit|un6_dly_counter_0_x\,
2399         datab => \vga_driver_unit|vsync_state_6\,
2400         datac => \vga_driver_unit|vsync_state_0\,
2401         datad => \vga_driver_unit|un9_vsync_counterlt9\,
2402         devclrn => ww_devclrn,
2403         devpor => ww_devpor,
2404         combout => \vga_driver_unit|G_16_i\);
2405
2406 \vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6\ : stratix_lcell
2407 -- Equation(s):
2408 -- \vga_driver_unit|un12_vsync_counter_6\ = !\vga_driver_unit|vsync_counter_7\ & !\vga_driver_unit|vsync_counter_8\ & !\vga_driver_unit|vsync_counter_6\ & !\vga_driver_unit|vsync_counter_5\
2409
2410 -- pragma translate_off
2411 GENERIC MAP (
2412         lut_mask => "0001",
2413         operation_mode => "normal",
2414         output_mode => "comb_only",
2415         register_cascade_mode => "off",
2416         sum_lutc_input => "datac",
2417         synch_mode => "off")
2418 -- pragma translate_on
2419 PORT MAP (
2420         dataa => \vga_driver_unit|vsync_counter_7\,
2421         datab => \vga_driver_unit|vsync_counter_8\,
2422         datac => \vga_driver_unit|vsync_counter_6\,
2423         datad => \vga_driver_unit|vsync_counter_5\,
2424         devclrn => ww_devclrn,
2425         devpor => ww_devpor,
2426         combout => \vga_driver_unit|un12_vsync_counter_6\);
2427
2428 \vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3\ : stratix_lcell
2429 -- Equation(s):
2430 -- \vga_driver_unit|un15_vsync_counter_3\ = !\vga_driver_unit|vsync_counter_0\ & \vga_driver_unit|vsync_counter_3\ & \vga_driver_unit|vsync_counter_9\ & !\vga_driver_unit|vsync_counter_2\
2431
2432 -- pragma translate_off
2433 GENERIC MAP (
2434         lut_mask => "0040",
2435         operation_mode => "normal",
2436         output_mode => "comb_only",
2437         register_cascade_mode => "off",
2438         sum_lutc_input => "datac",
2439         synch_mode => "off")
2440 -- pragma translate_on
2441 PORT MAP (
2442         dataa => \vga_driver_unit|vsync_counter_0\,
2443         datab => \vga_driver_unit|vsync_counter_3\,
2444         datac => \vga_driver_unit|vsync_counter_9\,
2445         datad => \vga_driver_unit|vsync_counter_2\,
2446         devclrn => ww_devclrn,
2447         devpor => ww_devpor,
2448         combout => \vga_driver_unit|un15_vsync_counter_3\);
2449
2450 \vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4\ : stratix_lcell
2451 -- Equation(s):
2452 -- \vga_driver_unit|un15_vsync_counter_4\ = !\vga_driver_unit|vsync_counter_4\ & !\vga_driver_unit|vsync_counter_1\ & \vga_driver_unit|un15_vsync_counter_3\
2453
2454 -- pragma translate_off
2455 GENERIC MAP (
2456         lut_mask => "0300",
2457         operation_mode => "normal",
2458         output_mode => "comb_only",
2459         register_cascade_mode => "off",
2460         sum_lutc_input => "datac",
2461         synch_mode => "off")
2462 -- pragma translate_on
2463 PORT MAP (
2464         datab => \vga_driver_unit|vsync_counter_4\,
2465         datac => \vga_driver_unit|vsync_counter_1\,
2466         datad => \vga_driver_unit|un15_vsync_counter_3\,
2467         devclrn => ww_devclrn,
2468         devpor => ww_devpor,
2469         combout => \vga_driver_unit|un15_vsync_counter_4\);
2470
2471 \vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8\ : stratix_lcell
2472 -- Equation(s):
2473 -- \vga_driver_unit|un14_vsync_counter_8\ = \vga_driver_unit|un12_vsync_counter_6\ & \vga_driver_unit|un12_vsync_counter_7\
2474
2475 -- pragma translate_off
2476 GENERIC MAP (
2477         lut_mask => "f000",
2478         operation_mode => "normal",
2479         output_mode => "comb_only",
2480         register_cascade_mode => "off",
2481         sum_lutc_input => "datac",
2482         synch_mode => "off")
2483 -- pragma translate_on
2484 PORT MAP (
2485         datac => \vga_driver_unit|un12_vsync_counter_6\,
2486         datad => \vga_driver_unit|un12_vsync_counter_7\,
2487         devclrn => ww_devclrn,
2488         devpor => ww_devpor,
2489         combout => \vga_driver_unit|un14_vsync_counter_8\);
2490
2491 \vga_driver_unit|vsync_state_5_\ : stratix_lcell
2492 -- Equation(s):
2493 -- \vga_driver_unit|vsync_state_5\ = DFFEAS(\vga_driver_unit|vsync_state_0\ # \vga_driver_unit|vsync_state_6\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|vsync_state_next_2_sqmuxa\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
2494
2495 -- pragma translate_off
2496 GENERIC MAP (
2497         lut_mask => "fff0",
2498         operation_mode => "normal",
2499         output_mode => "reg_only",
2500         register_cascade_mode => "off",
2501         sum_lutc_input => "datac",
2502         synch_mode => "on")
2503 -- pragma translate_on
2504 PORT MAP (
2505         clk => \clk_pin~combout\,
2506         datac => \vga_driver_unit|vsync_state_0\,
2507         datad => \vga_driver_unit|vsync_state_6\,
2508         aclr => GND,
2509         sclr => \vga_driver_unit|un6_dly_counter_0_x\,
2510         ena => \vga_driver_unit|vsync_state_next_2_sqmuxa\,
2511         devclrn => ww_devclrn,
2512         devpor => ww_devpor,
2513         regout => \vga_driver_unit|vsync_state_5\);
2514
2515 \vga_driver_unit|vsync_state_4_\ : stratix_lcell
2516 -- Equation(s):
2517 -- \vga_driver_unit|vsync_state_4\ = DFFEAS(\vga_driver_unit|vsync_counter_0\ & !\vga_driver_unit|vsync_counter_9\ & \vga_driver_unit|un14_vsync_counter_8\ & \vga_driver_unit|vsync_state_5\, GLOBAL(\clk_pin~combout\), VCC, ,
2518 -- \vga_driver_unit|vsync_state_next_2_sqmuxa\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
2519
2520 -- pragma translate_off
2521 GENERIC MAP (
2522         lut_mask => "2000",
2523         operation_mode => "normal",
2524         output_mode => "reg_only",
2525         register_cascade_mode => "off",
2526         sum_lutc_input => "datac",
2527         synch_mode => "on")
2528 -- pragma translate_on
2529 PORT MAP (
2530         clk => \clk_pin~combout\,
2531         dataa => \vga_driver_unit|vsync_counter_0\,
2532         datab => \vga_driver_unit|vsync_counter_9\,
2533         datac => \vga_driver_unit|un14_vsync_counter_8\,
2534         datad => \vga_driver_unit|vsync_state_5\,
2535         aclr => GND,
2536         sclr => \vga_driver_unit|un6_dly_counter_0_x\,
2537         ena => \vga_driver_unit|vsync_state_next_2_sqmuxa\,
2538         devclrn => ww_devclrn,
2539         devpor => ww_devpor,
2540         regout => \vga_driver_unit|vsync_state_4\);
2541
2542 \vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3\ : stratix_lcell
2543 -- Equation(s):
2544 -- \vga_driver_unit|un13_vsync_counter_3\ = !\vga_driver_unit|vsync_counter_7\ & !\vga_driver_unit|vsync_counter_6\ & !\vga_driver_unit|vsync_counter_8\ & !\vga_driver_unit|vsync_counter_9\
2545
2546 -- pragma translate_off
2547 GENERIC MAP (
2548         lut_mask => "0001",
2549         operation_mode => "normal",
2550         output_mode => "comb_only",
2551         register_cascade_mode => "off",
2552         sum_lutc_input => "datac",
2553         synch_mode => "off")
2554 -- pragma translate_on
2555 PORT MAP (
2556         dataa => \vga_driver_unit|vsync_counter_7\,
2557         datab => \vga_driver_unit|vsync_counter_6\,
2558         datac => \vga_driver_unit|vsync_counter_8\,
2559         datad => \vga_driver_unit|vsync_counter_9\,
2560         devclrn => ww_devclrn,
2561         devpor => ww_devpor,
2562         combout => \vga_driver_unit|un13_vsync_counter_3\);
2563
2564 \vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4\ : stratix_lcell
2565 -- Equation(s):
2566 -- \vga_driver_unit|un13_vsync_counter_4\ = \vga_driver_unit|vsync_counter_5\ & \vga_driver_unit|vsync_counter_0\ & \vga_driver_unit|un13_vsync_counter_3\
2567
2568 -- pragma translate_off
2569 GENERIC MAP (
2570         lut_mask => "c000",
2571         operation_mode => "normal",
2572         output_mode => "comb_only",
2573         register_cascade_mode => "off",
2574         sum_lutc_input => "datac",
2575         synch_mode => "off")
2576 -- pragma translate_on
2577 PORT MAP (
2578         datab => \vga_driver_unit|vsync_counter_5\,
2579         datac => \vga_driver_unit|vsync_counter_0\,
2580         datad => \vga_driver_unit|un13_vsync_counter_3\,
2581         devclrn => ww_devclrn,
2582         devpor => ww_devpor,
2583         combout => \vga_driver_unit|un13_vsync_counter_4\);
2584
2585 \vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ\ : stratix_lcell
2586 -- Equation(s):
2587 -- \vga_driver_unit|vsync_state_next_1_sqmuxa_2\ = \vga_driver_unit|vsync_state_4\ & (!\vga_driver_unit|un13_vsync_counter_4\ # !\vga_driver_unit|un12_vsync_counter_7\)
2588
2589 -- pragma translate_off
2590 GENERIC MAP (
2591         lut_mask => "0ccc",
2592         operation_mode => "normal",
2593         output_mode => "comb_only",
2594         register_cascade_mode => "off",
2595         sum_lutc_input => "datac",
2596         synch_mode => "off")
2597 -- pragma translate_on
2598 PORT MAP (
2599         datab => \vga_driver_unit|vsync_state_4\,
2600         datac => \vga_driver_unit|un12_vsync_counter_7\,
2601         datad => \vga_driver_unit|un13_vsync_counter_4\,
2602         devclrn => ww_devclrn,
2603         devpor => ww_devpor,
2604         combout => \vga_driver_unit|vsync_state_next_1_sqmuxa_2\);
2605
2606 \vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ\ : stratix_lcell
2607 -- Equation(s):
2608 -- \vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0\ = \vga_driver_unit|vsync_state_next_1_sqmuxa_2\ # \vga_driver_unit|vsync_state_2\ & (!\vga_driver_unit|un15_vsync_counter_4\ # !\vga_driver_unit|un12_vsync_counter_6\)
2609
2610 -- pragma translate_off
2611 GENERIC MAP (
2612         lut_mask => "ff2a",
2613         operation_mode => "normal",
2614         output_mode => "comb_only",
2615         register_cascade_mode => "off",
2616         sum_lutc_input => "datac",
2617         synch_mode => "off")
2618 -- pragma translate_on
2619 PORT MAP (
2620         dataa => \vga_driver_unit|vsync_state_2\,
2621         datab => \vga_driver_unit|un12_vsync_counter_6\,
2622         datac => \vga_driver_unit|un15_vsync_counter_4\,
2623         datad => \vga_driver_unit|vsync_state_next_1_sqmuxa_2\,
2624         devclrn => ww_devclrn,
2625         devpor => ww_devpor,
2626         combout => \vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0\);
2627
2628 \vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ\ : stratix_lcell
2629 -- Equation(s):
2630 -- \vga_driver_unit|vsync_state_next_1_sqmuxa_1\ = \vga_driver_unit|vsync_state_5\ & (\vga_driver_unit|vsync_counter_9\ # !\vga_driver_unit|un14_vsync_counter_8\ # !\vga_driver_unit|vsync_counter_0\)
2631
2632 -- pragma translate_off
2633 GENERIC MAP (
2634         lut_mask => "8ccc",
2635         operation_mode => "normal",
2636         output_mode => "comb_only",
2637         register_cascade_mode => "off",
2638         sum_lutc_input => "datac",
2639         synch_mode => "off")
2640 -- pragma translate_on
2641 PORT MAP (
2642         dataa => \vga_driver_unit|vsync_counter_9\,
2643         datab => \vga_driver_unit|vsync_state_5\,
2644         datac => \vga_driver_unit|vsync_counter_0\,
2645         datad => \vga_driver_unit|un14_vsync_counter_8\,
2646         devclrn => ww_devclrn,
2647         devpor => ww_devpor,
2648         combout => \vga_driver_unit|vsync_state_next_1_sqmuxa_1\);
2649
2650 \vga_driver_unit|vsync_state_3_\ : stratix_lcell
2651 -- Equation(s):
2652 -- \vga_driver_unit|vsync_state_next_1_sqmuxa_3\ = C1_vsync_state_3 & (!\vga_driver_unit|un14_vsync_counter_8\ # !\vga_driver_unit|vsync_counter_9\ # !\vga_driver_unit|vsync_counter_0\)
2653 -- \vga_driver_unit|vsync_state_3\ = DFFEAS(\vga_driver_unit|vsync_state_next_1_sqmuxa_3\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|vsync_state_next_2_sqmuxa\, \vga_driver_unit|vsync_state_1\, , \vga_driver_unit|un6_dly_counter_0_x\, VCC)
2654
2655 -- pragma translate_off
2656 GENERIC MAP (
2657         lut_mask => "70f0",
2658         operation_mode => "normal",
2659         output_mode => "reg_and_comb",
2660         register_cascade_mode => "off",
2661         sum_lutc_input => "qfbk",
2662         synch_mode => "on")
2663 -- pragma translate_on
2664 PORT MAP (
2665         clk => \clk_pin~combout\,
2666         dataa => \vga_driver_unit|vsync_counter_0\,
2667         datab => \vga_driver_unit|vsync_counter_9\,
2668         datac => \vga_driver_unit|vsync_state_1\,
2669         datad => \vga_driver_unit|un14_vsync_counter_8\,
2670         aclr => GND,
2671         sclr => \vga_driver_unit|un6_dly_counter_0_x\,
2672         sload => VCC,
2673         ena => \vga_driver_unit|vsync_state_next_2_sqmuxa\,
2674         devclrn => ww_devclrn,
2675         devpor => ww_devpor,
2676         combout => \vga_driver_unit|vsync_state_next_1_sqmuxa_3\,
2677         regout => \vga_driver_unit|vsync_state_3\);
2678
2679 \vga_driver_unit|vsync_state_next_2_sqmuxa_cZ\ : stratix_lcell
2680 -- Equation(s):
2681 -- \vga_driver_unit|vsync_state_next_2_sqmuxa\ = \vga_driver_unit|un6_dly_counter_0_x\ # !\vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0\ & !\vga_driver_unit|vsync_state_next_1_sqmuxa_1\ & !\vga_driver_unit|vsync_state_next_1_sqmuxa_3\
2682
2683 -- pragma translate_off
2684 GENERIC MAP (
2685         lut_mask => "aaab",
2686         operation_mode => "normal",
2687         output_mode => "comb_only",
2688         register_cascade_mode => "off",
2689         sum_lutc_input => "datac",
2690         synch_mode => "off")
2691 -- pragma translate_on
2692 PORT MAP (
2693         dataa => \vga_driver_unit|un6_dly_counter_0_x\,
2694         datab => \vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0\,
2695         datac => \vga_driver_unit|vsync_state_next_1_sqmuxa_1\,
2696         datad => \vga_driver_unit|vsync_state_next_1_sqmuxa_3\,
2697         devclrn => ww_devclrn,
2698         devpor => ww_devpor,
2699         combout => \vga_driver_unit|vsync_state_next_2_sqmuxa\);
2700
2701 \vga_driver_unit|vsync_state_2_\ : stratix_lcell
2702 -- Equation(s):
2703 -- \vga_driver_unit|vsync_state_2\ = DFFEAS(\vga_driver_unit|un14_vsync_counter_8\ & \vga_driver_unit|vsync_counter_9\ & \vga_driver_unit|vsync_counter_0\ & \vga_driver_unit|vsync_state_3\, GLOBAL(\clk_pin~combout\), VCC, ,
2704 -- \vga_driver_unit|vsync_state_next_2_sqmuxa\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
2705
2706 -- pragma translate_off
2707 GENERIC MAP (
2708         lut_mask => "8000",
2709         operation_mode => "normal",
2710         output_mode => "reg_only",
2711         register_cascade_mode => "off",
2712         sum_lutc_input => "datac",
2713         synch_mode => "on")
2714 -- pragma translate_on
2715 PORT MAP (
2716         clk => \clk_pin~combout\,
2717         dataa => \vga_driver_unit|un14_vsync_counter_8\,
2718         datab => \vga_driver_unit|vsync_counter_9\,
2719         datac => \vga_driver_unit|vsync_counter_0\,
2720         datad => \vga_driver_unit|vsync_state_3\,
2721         aclr => GND,
2722         sclr => \vga_driver_unit|un6_dly_counter_0_x\,
2723         ena => \vga_driver_unit|vsync_state_next_2_sqmuxa\,
2724         devclrn => ww_devclrn,
2725         devpor => ww_devpor,
2726         regout => \vga_driver_unit|vsync_state_2\);
2727
2728 \vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ\ : stratix_lcell
2729 -- Equation(s):
2730 -- \vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0\ = \vga_driver_unit|un12_vsync_counter_6\ & \vga_driver_unit|un15_vsync_counter_4\ & \vga_driver_unit|vsync_state_2\
2731
2732 -- pragma translate_off
2733 GENERIC MAP (
2734         lut_mask => "c000",
2735         operation_mode => "normal",
2736         output_mode => "comb_only",
2737         register_cascade_mode => "off",
2738         sum_lutc_input => "datac",
2739         synch_mode => "off")
2740 -- pragma translate_on
2741 PORT MAP (
2742         datab => \vga_driver_unit|un12_vsync_counter_6\,
2743         datac => \vga_driver_unit|un15_vsync_counter_4\,
2744         datad => \vga_driver_unit|vsync_state_2\,
2745         devclrn => ww_devclrn,
2746         devpor => ww_devpor,
2747         combout => \vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0\);
2748
2749 \vga_driver_unit|vsync_state_0_\ : stratix_lcell
2750 -- Equation(s):
2751 -- \vga_driver_unit|vsync_state_0\ = DFFEAS(\vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0\ & (\vga_driver_unit|vsync_state_0\ & !\vga_driver_unit|vsync_state_next_2_sqmuxa\ # !\vga_driver_unit|un6_dly_counter_0_x\) #
2752 -- !\vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0\ & (\vga_driver_unit|vsync_state_0\ & !\vga_driver_unit|vsync_state_next_2_sqmuxa\), GLOBAL(\clk_pin~combout\), VCC, , , , , , )
2753
2754 -- pragma translate_off
2755 GENERIC MAP (
2756         lut_mask => "22f2",
2757         operation_mode => "normal",
2758         output_mode => "reg_only",
2759         register_cascade_mode => "off",
2760         sum_lutc_input => "datac",
2761         synch_mode => "off")
2762 -- pragma translate_on
2763 PORT MAP (
2764         clk => \clk_pin~combout\,
2765         dataa => \vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0\,
2766         datab => \vga_driver_unit|un6_dly_counter_0_x\,
2767         datac => \vga_driver_unit|vsync_state_0\,
2768         datad => \vga_driver_unit|vsync_state_next_2_sqmuxa\,
2769         aclr => GND,
2770         devclrn => ww_devclrn,
2771         devpor => ww_devpor,
2772         regout => \vga_driver_unit|vsync_state_0\);
2773
2774 \vga_driver_unit|d_set_vsync_counter_cZ\ : stratix_lcell
2775 -- Equation(s):
2776 -- \vga_driver_unit|d_set_vsync_counter\ = \vga_driver_unit|vsync_state_6\ # \vga_driver_unit|vsync_state_0\
2777
2778 -- pragma translate_off
2779 GENERIC MAP (
2780         lut_mask => "ffcc",
2781         operation_mode => "normal",
2782         output_mode => "comb_only",
2783         register_cascade_mode => "off",
2784         sum_lutc_input => "datac",
2785         synch_mode => "off")
2786 -- pragma translate_on
2787 PORT MAP (
2788         datab => \vga_driver_unit|vsync_state_6\,
2789         datad => \vga_driver_unit|vsync_state_0\,
2790         devclrn => ww_devclrn,
2791         devpor => ww_devpor,
2792         combout => \vga_driver_unit|d_set_vsync_counter\);
2793
2794 \vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ\ : stratix_lcell
2795 -- Equation(s):
2796 -- \vga_driver_unit|vsync_counter_next_1_sqmuxa\ = dly_counter(1) & \reset_pin~combout\ & !\vga_driver_unit|d_set_vsync_counter\ & dly_counter(0)
2797
2798 -- pragma translate_off
2799 GENERIC MAP (
2800         lut_mask => "0800",
2801         operation_mode => "normal",
2802         output_mode => "comb_only",
2803         register_cascade_mode => "off",
2804         sum_lutc_input => "datac",
2805         synch_mode => "off")
2806 -- pragma translate_on
2807 PORT MAP (
2808         dataa => dly_counter(1),
2809         datab => \reset_pin~combout\,
2810         datac => \vga_driver_unit|d_set_vsync_counter\,
2811         datad => dly_counter(0),
2812         devclrn => ww_devclrn,
2813         devpor => ww_devpor,
2814         combout => \vga_driver_unit|vsync_counter_next_1_sqmuxa\);
2815
2816 \vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7\ : stratix_lcell
2817 -- Equation(s):
2818 -- \vga_driver_unit|un12_vsync_counter_7\ = !\vga_driver_unit|vsync_counter_4\ & !\vga_driver_unit|vsync_counter_2\ & !\vga_driver_unit|vsync_counter_3\ & !\vga_driver_unit|vsync_counter_1\
2819
2820 -- pragma translate_off
2821 GENERIC MAP (
2822         lut_mask => "0001",
2823         operation_mode => "normal",
2824         output_mode => "comb_only",
2825         register_cascade_mode => "off",
2826         sum_lutc_input => "datac",
2827         synch_mode => "off")
2828 -- pragma translate_on
2829 PORT MAP (
2830         dataa => \vga_driver_unit|vsync_counter_4\,
2831         datab => \vga_driver_unit|vsync_counter_2\,
2832         datac => \vga_driver_unit|vsync_counter_3\,
2833         datad => \vga_driver_unit|vsync_counter_1\,
2834         devclrn => ww_devclrn,
2835         devpor => ww_devpor,
2836         combout => \vga_driver_unit|un12_vsync_counter_7\);
2837
2838 \vga_driver_unit|vsync_state_1_\ : stratix_lcell
2839 -- Equation(s):
2840 -- \vga_driver_unit|vsync_state_1\ = DFFEAS(\vga_driver_unit|un12_vsync_counter_7\ & !\vga_driver_unit|un6_dly_counter_0_x\ & \vga_driver_unit|un13_vsync_counter_4\ & \vga_driver_unit|vsync_state_4\, GLOBAL(\clk_pin~combout\), VCC, , , , , , )
2841
2842 -- pragma translate_off
2843 GENERIC MAP (
2844         lut_mask => "2000",
2845         operation_mode => "normal",
2846         output_mode => "reg_only",
2847         register_cascade_mode => "off",
2848         sum_lutc_input => "datac",
2849         synch_mode => "off")
2850 -- pragma translate_on
2851 PORT MAP (
2852         clk => \clk_pin~combout\,
2853         dataa => \vga_driver_unit|un12_vsync_counter_7\,
2854         datab => \vga_driver_unit|un6_dly_counter_0_x\,
2855         datac => \vga_driver_unit|un13_vsync_counter_4\,
2856         datad => \vga_driver_unit|vsync_state_4\,
2857         aclr => GND,
2858         devclrn => ww_devclrn,
2859         devpor => ww_devpor,
2860         regout => \vga_driver_unit|vsync_state_1\);
2861
2862 \vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ\ : stratix_lcell
2863 -- Equation(s):
2864 -- \vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4\ = \vga_driver_unit|un6_dly_counter_0_x\ # !\vga_driver_unit|vsync_state_4\ & (!\vga_driver_unit|vsync_state_5\)
2865
2866 -- pragma translate_off
2867 GENERIC MAP (
2868         lut_mask => "ccdd",
2869         operation_mode => "normal",
2870         output_mode => "comb_only",
2871         register_cascade_mode => "off",
2872         sum_lutc_input => "datac",
2873         synch_mode => "off")
2874 -- pragma translate_on
2875 PORT MAP (
2876         dataa => \vga_driver_unit|vsync_state_4\,
2877         datab => \vga_driver_unit|un6_dly_counter_0_x\,
2878         datad => \vga_driver_unit|vsync_state_5\,
2879         devclrn => ww_devclrn,
2880         devpor => ww_devpor,
2881         combout => \vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4\);
2882
2883 \vga_driver_unit|h_enable_sig_Z\ : stratix_lcell
2884 -- Equation(s):
2885 -- \vga_driver_unit|h_enable_sig\ = DFFEAS(\vga_driver_unit|vsync_state_1\ # \vga_driver_unit|vsync_state_3\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
2886
2887 -- pragma translate_off
2888 GENERIC MAP (
2889         lut_mask => "ffcc",
2890         operation_mode => "normal",
2891         output_mode => "reg_only",
2892         register_cascade_mode => "off",
2893         sum_lutc_input => "datac",
2894         synch_mode => "on")
2895 -- pragma translate_on
2896 PORT MAP (
2897         clk => \clk_pin~combout\,
2898         datab => \vga_driver_unit|vsync_state_1\,
2899         datad => \vga_driver_unit|vsync_state_3\,
2900         aclr => GND,
2901         sclr => \vga_driver_unit|un6_dly_counter_0_x\,
2902         ena => \vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4\,
2903         devclrn => ww_devclrn,
2904         devpor => ww_devpor,
2905         regout => \vga_driver_unit|h_enable_sig\);
2906
2907 \vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ\ : stratix_lcell
2908 -- Equation(s):
2909 -- \vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4\ = \vga_driver_unit|un6_dly_counter_0_x\ # !\vga_driver_unit|hsync_state_5\ & !\vga_driver_unit|hsync_state_4\
2910
2911 -- pragma translate_off
2912 GENERIC MAP (
2913         lut_mask => "aaaf",
2914         operation_mode => "normal",
2915         output_mode => "comb_only",
2916         register_cascade_mode => "off",
2917         sum_lutc_input => "datac",
2918         synch_mode => "off")
2919 -- pragma translate_on
2920 PORT MAP (
2921         dataa => \vga_driver_unit|un6_dly_counter_0_x\,
2922         datac => \vga_driver_unit|hsync_state_5\,
2923         datad => \vga_driver_unit|hsync_state_4\,
2924         devclrn => ww_devclrn,
2925         devpor => ww_devpor,
2926         combout => \vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4\);
2927
2928 \vga_driver_unit|v_enable_sig_Z\ : stratix_lcell
2929 -- Equation(s):
2930 -- \vga_driver_unit|v_enable_sig\ = DFFEAS(\vga_driver_unit|hsync_state_1\ # \vga_driver_unit|hsync_state_3\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
2931
2932 -- pragma translate_off
2933 GENERIC MAP (
2934         lut_mask => "fcfc",
2935         operation_mode => "normal",
2936         output_mode => "reg_only",
2937         register_cascade_mode => "off",
2938         sum_lutc_input => "datac",
2939         synch_mode => "on")
2940 -- pragma translate_on
2941 PORT MAP (
2942         clk => \clk_pin~combout\,
2943         datab => \vga_driver_unit|hsync_state_1\,
2944         datac => \vga_driver_unit|hsync_state_3\,
2945         aclr => GND,
2946         sclr => \vga_driver_unit|un6_dly_counter_0_x\,
2947         ena => \vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4\,
2948         devclrn => ww_devclrn,
2949         devpor => ww_devpor,
2950         regout => \vga_driver_unit|v_enable_sig\);
2951
2952 \vga_control_unit|r_next_i_o7_cZ\ : stratix_lcell
2953 -- Equation(s):
2954 -- \vga_control_unit|r_next_i_o7\ = \vga_driver_unit|column_counter_sig_9\ # !\vga_driver_unit|v_enable_sig\ # !\vga_driver_unit|h_enable_sig\
2955
2956 -- pragma translate_off
2957 GENERIC MAP (
2958         lut_mask => "f3ff",
2959         operation_mode => "normal",
2960         output_mode => "comb_only",
2961         register_cascade_mode => "off",
2962         sum_lutc_input => "datac",
2963         synch_mode => "off")
2964 -- pragma translate_on
2965 PORT MAP (
2966         datab => \vga_driver_unit|h_enable_sig\,
2967         datac => \vga_driver_unit|column_counter_sig_9\,
2968         datad => \vga_driver_unit|v_enable_sig\,
2969         devclrn => ww_devclrn,
2970         devpor => ww_devpor,
2971         combout => \vga_control_unit|r_next_i_o7\);
2972
2973 \vga_control_unit|N_4_i_0_g0_1_cZ\ : stratix_lcell
2974 -- Equation(s):
2975 -- \vga_control_unit|N_4_i_0_g0_1\ = !\vga_control_unit|r_next_i_o7\ & (\vga_driver_unit|column_counter_sig_8\ # \vga_control_unit|g_next_i_o3\ & \vga_driver_unit|column_counter_sig_7\)
2976
2977 -- pragma translate_off
2978 GENERIC MAP (
2979         lut_mask => "00f8",
2980         operation_mode => "normal",
2981         output_mode => "comb_only",
2982         register_cascade_mode => "off",
2983         sum_lutc_input => "datac",
2984         synch_mode => "off")
2985 -- pragma translate_on
2986 PORT MAP (
2987         dataa => \vga_control_unit|g_next_i_o3\,
2988         datab => \vga_driver_unit|column_counter_sig_7\,
2989         datac => \vga_driver_unit|column_counter_sig_8\,
2990         datad => \vga_control_unit|r_next_i_o7\,
2991         devclrn => ww_devclrn,
2992         devpor => ww_devpor,
2993         combout => \vga_control_unit|N_4_i_0_g0_1\);
2994
2995 \vga_control_unit|r_Z\ : stratix_lcell
2996 -- Equation(s):
2997 -- \vga_control_unit|r\ = DFFEAS(\vga_control_unit|N_4_i_0_g0_1\ & (\vga_driver_unit|column_counter_sig_8\ & (!\vga_control_unit|b_next_i_o3_0\) # !\vga_driver_unit|column_counter_sig_8\ & !\vga_driver_unit|un10_column_counter_siglt6_3\),
2998 -- GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , , )
2999
3000 -- pragma translate_off
3001 GENERIC MAP (
3002         lut_mask => "1d00",
3003         operation_mode => "normal",
3004         output_mode => "reg_only",
3005         register_cascade_mode => "off",
3006         sum_lutc_input => "datac",
3007         synch_mode => "off")
3008 -- pragma translate_on
3009 PORT MAP (
3010         clk => \clk_pin~combout\,
3011         dataa => \vga_driver_unit|un10_column_counter_siglt6_3\,
3012         datab => \vga_driver_unit|column_counter_sig_8\,
3013         datac => \vga_control_unit|b_next_i_o3_0\,
3014         datad => \vga_control_unit|N_4_i_0_g0_1\,
3015         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
3016         devclrn => ww_devclrn,
3017         devpor => ww_devpor,
3018         regout => \vga_control_unit|r\);
3019
3020 \vga_control_unit|N_23_i_0_g0_a_cZ\ : stratix_lcell
3021 -- Equation(s):
3022 -- \vga_control_unit|N_23_i_0_g0_a\ = \vga_driver_unit|column_counter_sig_5\ & (\vga_driver_unit|column_counter_sig_6\ & (!\vga_control_unit|g_next_i_o3\) # !\vga_driver_unit|column_counter_sig_6\ & (\vga_control_unit|g_next_i_o3\ #
3023 -- !\vga_driver_unit|un10_column_counter_siglt6_1\)) # !\vga_driver_unit|column_counter_sig_5\ & (\vga_driver_unit|column_counter_sig_6\)
3024
3025 -- pragma translate_off
3026 GENERIC MAP (
3027         lut_mask => "5af2",
3028         operation_mode => "normal",
3029         output_mode => "comb_only",
3030         register_cascade_mode => "off",
3031         sum_lutc_input => "datac",
3032         synch_mode => "off")
3033 -- pragma translate_on
3034 PORT MAP (
3035         dataa => \vga_driver_unit|column_counter_sig_5\,
3036         datab => \vga_driver_unit|un10_column_counter_siglt6_1\,
3037         datac => \vga_driver_unit|column_counter_sig_6\,
3038         datad => \vga_control_unit|g_next_i_o3\,
3039         devclrn => ww_devclrn,
3040         devpor => ww_devpor,
3041         combout => \vga_control_unit|N_23_i_0_g0_a\);
3042
3043 \vga_control_unit|g_Z\ : stratix_lcell
3044 -- Equation(s):
3045 -- \vga_control_unit|g\ = DFFEAS(\vga_driver_unit|column_counter_sig_7\ & !\vga_driver_unit|column_counter_sig_8\ & \vga_control_unit|N_23_i_0_g0_a\ & !\vga_control_unit|r_next_i_o7\, GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\),
3046 -- , , , , , )
3047
3048 -- pragma translate_off
3049 GENERIC MAP (
3050         lut_mask => "0020",
3051         operation_mode => "normal",
3052         output_mode => "reg_only",
3053         register_cascade_mode => "off",
3054         sum_lutc_input => "datac",
3055         synch_mode => "off")
3056 -- pragma translate_on
3057 PORT MAP (
3058         clk => \clk_pin~combout\,
3059         dataa => \vga_driver_unit|column_counter_sig_7\,
3060         datab => \vga_driver_unit|column_counter_sig_8\,
3061         datac => \vga_control_unit|N_23_i_0_g0_a\,
3062         datad => \vga_control_unit|r_next_i_o7\,
3063         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
3064         devclrn => ww_devclrn,
3065         devpor => ww_devpor,
3066         regout => \vga_control_unit|g\);
3067
3068 \vga_control_unit|b_next_i_a7_1_cZ\ : stratix_lcell
3069 -- Equation(s):
3070 -- \vga_control_unit|b_next_i_a7_1\ = !\vga_driver_unit|column_counter_sig_2\ & !\vga_driver_unit|column_counter_sig_8\ & !\vga_driver_unit|column_counter_sig_7\ & !\vga_control_unit|g_next_i_o3\
3071
3072 -- pragma translate_off
3073 GENERIC MAP (
3074         lut_mask => "0001",
3075         operation_mode => "normal",
3076         output_mode => "comb_only",
3077         register_cascade_mode => "off",
3078         sum_lutc_input => "datac",
3079         synch_mode => "off")
3080 -- pragma translate_on
3081 PORT MAP (
3082         dataa => \vga_driver_unit|column_counter_sig_2\,
3083         datab => \vga_driver_unit|column_counter_sig_8\,
3084         datac => \vga_driver_unit|column_counter_sig_7\,
3085         datad => \vga_control_unit|g_next_i_o3\,
3086         devclrn => ww_devclrn,
3087         devpor => ww_devpor,
3088         combout => \vga_control_unit|b_next_i_a7_1\);
3089
3090 \vga_control_unit|N_6_i_0_g0_0_cZ\ : stratix_lcell
3091 -- Equation(s):
3092 -- \vga_control_unit|N_6_i_0_g0_0\ = !\vga_control_unit|r_next_i_o7\ & (\vga_driver_unit|column_counter_sig_7\ # \vga_driver_unit|column_counter_sig_8\ # !\vga_driver_unit|un10_column_counter_siglt6_3\)
3093
3094 -- pragma translate_off
3095 GENERIC MAP (
3096         lut_mask => "00ef",
3097         operation_mode => "normal",
3098         output_mode => "comb_only",
3099         register_cascade_mode => "off",
3100         sum_lutc_input => "datac",
3101         synch_mode => "off")
3102 -- pragma translate_on
3103 PORT MAP (
3104         dataa => \vga_driver_unit|column_counter_sig_7\,
3105         datab => \vga_driver_unit|column_counter_sig_8\,
3106         datac => \vga_driver_unit|un10_column_counter_siglt6_3\,
3107         datad => \vga_control_unit|r_next_i_o7\,
3108         devclrn => ww_devclrn,
3109         devpor => ww_devpor,
3110         combout => \vga_control_unit|N_6_i_0_g0_0\);
3111
3112 \vga_control_unit|b_Z\ : stratix_lcell
3113 -- Equation(s):
3114 -- \vga_control_unit|b\ = DFFEAS(!\vga_control_unit|b_next_i_a7_1\ & \vga_control_unit|N_6_i_0_g0_0\ & (!\vga_driver_unit|column_counter_sig_8\ # !\vga_control_unit|b_next_i_o3_0\), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), ,
3115 -- , , , , )
3116
3117 -- pragma translate_off
3118 GENERIC MAP (
3119         lut_mask => "1050",
3120         operation_mode => "normal",
3121         output_mode => "reg_only",
3122         register_cascade_mode => "off",
3123         sum_lutc_input => "datac",
3124         synch_mode => "off")
3125 -- pragma translate_on
3126 PORT MAP (
3127         clk => \clk_pin~combout\,
3128         dataa => \vga_control_unit|b_next_i_a7_1\,
3129         datab => \vga_control_unit|b_next_i_o3_0\,
3130         datac => \vga_control_unit|N_6_i_0_g0_0\,
3131         datad => \vga_driver_unit|column_counter_sig_8\,
3132         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
3133         devclrn => ww_devclrn,
3134         devpor => ww_devpor,
3135         regout => \vga_control_unit|b\);
3136
3137 \vga_driver_unit|un1_hsync_state_3_0_cZ\ : stratix_lcell
3138 -- Equation(s):
3139 -- \vga_driver_unit|un1_hsync_state_3_0\ = \vga_driver_unit|hsync_state_1\ # \vga_driver_unit|hsync_state_3\
3140
3141 -- pragma translate_off
3142 GENERIC MAP (
3143         lut_mask => "fcfc",
3144         operation_mode => "normal",
3145         output_mode => "comb_only",
3146         register_cascade_mode => "off",
3147         sum_lutc_input => "datac",
3148         synch_mode => "off")
3149 -- pragma translate_on
3150 PORT MAP (
3151         datab => \vga_driver_unit|hsync_state_1\,
3152         datac => \vga_driver_unit|hsync_state_3\,
3153         devclrn => ww_devclrn,
3154         devpor => ww_devpor,
3155         combout => \vga_driver_unit|un1_hsync_state_3_0\);
3156
3157 \vga_driver_unit|h_sync_1_0_0_0_g1_cZ\ : stratix_lcell
3158 -- Equation(s):
3159 -- \vga_driver_unit|h_sync_1_0_0_0_g1\ = \vga_driver_unit|un1_hsync_state_3_0\ & (\vga_driver_unit|h_sync\) # !\vga_driver_unit|un1_hsync_state_3_0\ & (\vga_driver_unit|hsync_state_2\ & (\vga_driver_unit|h_sync\) # !\vga_driver_unit|hsync_state_2\ &
3160 -- \vga_driver_unit|hsync_state_4\)
3161
3162 -- pragma translate_off
3163 GENERIC MAP (
3164         lut_mask => "fe02",
3165         operation_mode => "normal",
3166         output_mode => "comb_only",
3167         register_cascade_mode => "off",
3168         sum_lutc_input => "datac",
3169         synch_mode => "off")
3170 -- pragma translate_on
3171 PORT MAP (
3172         dataa => \vga_driver_unit|hsync_state_4\,
3173         datab => \vga_driver_unit|un1_hsync_state_3_0\,
3174         datac => \vga_driver_unit|hsync_state_2\,
3175         datad => \vga_driver_unit|h_sync\,
3176         devclrn => ww_devclrn,
3177         devpor => ww_devpor,
3178         combout => \vga_driver_unit|h_sync_1_0_0_0_g1\);
3179
3180 \vga_driver_unit|h_sync_Z\ : stratix_lcell
3181 -- Equation(s):
3182 -- \vga_driver_unit|h_sync\ = DFFEAS(\vga_driver_unit|h_sync_1_0_0_0_g1\ # !dly_counter(0) # !dly_counter(1) # !\reset_pin~combout\, GLOBAL(\clk_pin~combout\), VCC, , , , , , )
3183
3184 -- pragma translate_off
3185 GENERIC MAP (
3186         lut_mask => "bfff",
3187         operation_mode => "normal",
3188         output_mode => "reg_only",
3189         register_cascade_mode => "off",
3190         sum_lutc_input => "datac",
3191         synch_mode => "off")
3192 -- pragma translate_on
3193 PORT MAP (
3194         clk => \clk_pin~combout\,
3195         dataa => \vga_driver_unit|h_sync_1_0_0_0_g1\,
3196         datab => \reset_pin~combout\,
3197         datac => dly_counter(1),
3198         datad => dly_counter(0),
3199         aclr => GND,
3200         devclrn => ww_devclrn,
3201         devpor => ww_devpor,
3202         regout => \vga_driver_unit|h_sync\);
3203
3204 \vga_driver_unit|un1_vsync_state_2_0_cZ\ : stratix_lcell
3205 -- Equation(s):
3206 -- \vga_driver_unit|un1_vsync_state_2_0\ = \vga_driver_unit|vsync_state_1\ # \vga_driver_unit|vsync_state_3\
3207
3208 -- pragma translate_off
3209 GENERIC MAP (
3210         lut_mask => "fff0",
3211         operation_mode => "normal",
3212         output_mode => "comb_only",
3213         register_cascade_mode => "off",
3214         sum_lutc_input => "datac",
3215         synch_mode => "off")
3216 -- pragma translate_on
3217 PORT MAP (
3218         datac => \vga_driver_unit|vsync_state_1\,
3219         datad => \vga_driver_unit|vsync_state_3\,
3220         devclrn => ww_devclrn,
3221         devpor => ww_devpor,
3222         combout => \vga_driver_unit|un1_vsync_state_2_0\);
3223
3224 \vga_driver_unit|v_sync_1_0_0_0_g1_cZ\ : stratix_lcell
3225 -- Equation(s):
3226 -- \vga_driver_unit|v_sync_1_0_0_0_g1\ = \vga_driver_unit|vsync_state_2\ & \vga_driver_unit|v_sync\ # !\vga_driver_unit|vsync_state_2\ & (\vga_driver_unit|un1_vsync_state_2_0\ & \vga_driver_unit|v_sync\ # !\vga_driver_unit|un1_vsync_state_2_0\ &
3227 -- (\vga_driver_unit|vsync_state_4\))
3228
3229 -- pragma translate_off
3230 GENERIC MAP (
3231         lut_mask => "aba8",
3232         operation_mode => "normal",
3233         output_mode => "comb_only",
3234         register_cascade_mode => "off",
3235         sum_lutc_input => "datac",
3236         synch_mode => "off")
3237 -- pragma translate_on
3238 PORT MAP (
3239         dataa => \vga_driver_unit|v_sync\,
3240         datab => \vga_driver_unit|vsync_state_2\,
3241         datac => \vga_driver_unit|un1_vsync_state_2_0\,
3242         datad => \vga_driver_unit|vsync_state_4\,
3243         devclrn => ww_devclrn,
3244         devpor => ww_devpor,
3245         combout => \vga_driver_unit|v_sync_1_0_0_0_g1\);
3246
3247 \vga_driver_unit|v_sync_Z\ : stratix_lcell
3248 -- Equation(s):
3249 -- \vga_driver_unit|v_sync\ = DFFEAS(\vga_driver_unit|v_sync_1_0_0_0_g1\ # !dly_counter(1) # !dly_counter(0) # !\reset_pin~combout\, GLOBAL(\clk_pin~combout\), VCC, , , , , , )
3250
3251 -- pragma translate_off
3252 GENERIC MAP (
3253         lut_mask => "ff7f",
3254         operation_mode => "normal",
3255         output_mode => "reg_only",
3256         register_cascade_mode => "off",
3257         sum_lutc_input => "datac",
3258         synch_mode => "off")
3259 -- pragma translate_on
3260 PORT MAP (
3261         clk => \clk_pin~combout\,
3262         dataa => \reset_pin~combout\,
3263         datab => dly_counter(0),
3264         datac => dly_counter(1),
3265         datad => \vga_driver_unit|v_sync_1_0_0_0_g1\,
3266         aclr => GND,
3267         devclrn => ww_devclrn,
3268         devpor => ww_devpor,
3269         regout => \vga_driver_unit|v_sync\);
3270
3271 \~STRATIX_FITTER_CREATED_GND~I\ : stratix_lcell
3272 -- Equation(s):
3273 -- \~STRATIX_FITTER_CREATED_GND~I_combout\ = GND
3274
3275 -- pragma translate_off
3276 GENERIC MAP (
3277         lut_mask => "0000",
3278         operation_mode => "normal",
3279         output_mode => "comb_only",
3280         register_cascade_mode => "off",
3281         sum_lutc_input => "datac",
3282         synch_mode => "off")
3283 -- pragma translate_on
3284 PORT MAP (
3285         devclrn => ww_devclrn,
3286         devpor => ww_devpor,
3287         combout => \~STRATIX_FITTER_CREATED_GND~I_combout\);
3288
3289 \vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ\ : stratix_lcell
3290 -- Equation(s):
3291 -- \vga_driver_unit|line_counter_next_0_sqmuxa_1_1\ = \reset_pin~combout\ & !\vga_driver_unit|vsync_state_1\ & dly_counter(1) & dly_counter(0)
3292
3293 -- pragma translate_off
3294 GENERIC MAP (
3295         lut_mask => "2000",
3296         operation_mode => "normal",
3297         output_mode => "comb_only",
3298         register_cascade_mode => "off",
3299         sum_lutc_input => "datac",
3300         synch_mode => "off")
3301 -- pragma translate_on
3302 PORT MAP (
3303         dataa => \reset_pin~combout\,
3304         datab => \vga_driver_unit|vsync_state_1\,
3305         datac => dly_counter(1),
3306         datad => dly_counter(0),
3307         devclrn => ww_devclrn,
3308         devpor => ww_devpor,
3309         combout => \vga_driver_unit|line_counter_next_0_sqmuxa_1_1\);
3310
3311 \vga_driver_unit|un1_line_counter_sig_a_1_\ : stratix_lcell
3312 -- Equation(s):
3313 -- \vga_driver_unit|un1_line_counter_sig_a_cout\(1) = CARRY(\vga_driver_unit|line_counter_sig_0\ & \vga_driver_unit|d_set_hsync_counter\)
3314 -- \vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3\ = CARRY(\vga_driver_unit|line_counter_sig_0\ & \vga_driver_unit|d_set_hsync_counter\)
3315
3316 -- pragma translate_off
3317 GENERIC MAP (
3318         lut_mask => "ff88",
3319         operation_mode => "arithmetic",
3320         output_mode => "none",
3321         register_cascade_mode => "off",
3322         sum_lutc_input => "datac",
3323         synch_mode => "off")
3324 -- pragma translate_on
3325 PORT MAP (
3326         dataa => \vga_driver_unit|line_counter_sig_0\,
3327         datab => \vga_driver_unit|d_set_hsync_counter\,
3328         devclrn => ww_devclrn,
3329         devpor => ww_devpor,
3330         combout => \vga_driver_unit|un1_line_counter_sig_a_1_~COMBOUT\,
3331         cout0 => \vga_driver_unit|un1_line_counter_sig_a_cout\(1),
3332         cout1 => \vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3\);
3333
3334 \vga_driver_unit|un1_line_counter_sig_2_\ : stratix_lcell
3335 -- Equation(s):
3336 -- \vga_driver_unit|un1_line_counter_sig_combout\(2) = \vga_driver_unit|line_counter_sig_1\ $ \vga_driver_unit|un1_line_counter_sig_a_cout\(1)
3337 -- \vga_driver_unit|un1_line_counter_sig_cout\(2) = CARRY(!\vga_driver_unit|un1_line_counter_sig_a_cout\(1) # !\vga_driver_unit|line_counter_sig_1\ # !\vga_driver_unit|line_counter_sig_2\)
3338 -- \vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17\ = CARRY(!\vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3\ # !\vga_driver_unit|line_counter_sig_1\ # !\vga_driver_unit|line_counter_sig_2\)
3339
3340 -- pragma translate_off
3341 GENERIC MAP (
3342         cin0_used => "true",
3343         cin1_used => "true",
3344         lut_mask => "3c7f",
3345         operation_mode => "arithmetic",
3346         output_mode => "comb_only",
3347         register_cascade_mode => "off",
3348         sum_lutc_input => "cin",
3349         synch_mode => "off")
3350 -- pragma translate_on
3351 PORT MAP (
3352         dataa => \vga_driver_unit|line_counter_sig_2\,
3353         datab => \vga_driver_unit|line_counter_sig_1\,
3354         cin0 => \vga_driver_unit|un1_line_counter_sig_a_cout\(1),
3355         cin1 => \vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3\,
3356         devclrn => ww_devclrn,
3357         devpor => ww_devpor,
3358         combout => \vga_driver_unit|un1_line_counter_sig_combout\(2),
3359         cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(2),
3360         cout1 => \vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17\);
3361
3362 \vga_driver_unit|line_counter_sig_1_\ : stratix_lcell
3363 -- Equation(s):
3364 -- \vga_driver_unit|line_counter_sig_1\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(2) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, )
3365
3366 -- pragma translate_off
3367 GENERIC MAP (
3368         lut_mask => "ff0f",
3369         operation_mode => "normal",
3370         output_mode => "reg_only",
3371         register_cascade_mode => "off",
3372         sum_lutc_input => "datac",
3373         synch_mode => "on")
3374 -- pragma translate_on
3375 PORT MAP (
3376         clk => \clk_pin~combout\,
3377         datac => \vga_driver_unit|un10_line_counter_siglto8\,
3378         datad => \vga_driver_unit|un1_line_counter_sig_combout\(2),
3379         aclr => GND,
3380         sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\,
3381         devclrn => ww_devclrn,
3382         devpor => ww_devpor,
3383         regout => \vga_driver_unit|line_counter_sig_1\);
3384
3385 \vga_driver_unit|un1_line_counter_sig_1_\ : stratix_lcell
3386 -- Equation(s):
3387 -- \vga_driver_unit|un1_line_counter_sig_combout\(1) = \vga_driver_unit|line_counter_sig_0\ $ \vga_driver_unit|d_set_hsync_counter\
3388 -- \vga_driver_unit|un1_line_counter_sig_cout\(1) = CARRY(\vga_driver_unit|line_counter_sig_0\ & \vga_driver_unit|d_set_hsync_counter\)
3389 -- \vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9\ = CARRY(\vga_driver_unit|line_counter_sig_0\ & \vga_driver_unit|d_set_hsync_counter\)
3390
3391 -- pragma translate_off
3392 GENERIC MAP (
3393         lut_mask => "6688",
3394         operation_mode => "arithmetic",
3395         output_mode => "comb_only",
3396         register_cascade_mode => "off",
3397         sum_lutc_input => "datac",
3398         synch_mode => "off")
3399 -- pragma translate_on
3400 PORT MAP (
3401         dataa => \vga_driver_unit|line_counter_sig_0\,
3402         datab => \vga_driver_unit|d_set_hsync_counter\,
3403         devclrn => ww_devclrn,
3404         devpor => ww_devpor,
3405         combout => \vga_driver_unit|un1_line_counter_sig_combout\(1),
3406         cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(1),
3407         cout1 => \vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9\);
3408
3409 \vga_driver_unit|un1_line_counter_sig_3_\ : stratix_lcell
3410 -- Equation(s):
3411 -- \vga_driver_unit|un1_line_counter_sig_combout\(3) = \vga_driver_unit|line_counter_sig_2\ $ (\vga_driver_unit|line_counter_sig_1\ & \vga_driver_unit|un1_line_counter_sig_cout\(1))
3412 -- \vga_driver_unit|un1_line_counter_sig_cout\(3) = CARRY(!\vga_driver_unit|un1_line_counter_sig_cout\(1) # !\vga_driver_unit|line_counter_sig_2\ # !\vga_driver_unit|line_counter_sig_1\)
3413 -- \vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11\ = CARRY(!\vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9\ # !\vga_driver_unit|line_counter_sig_2\ # !\vga_driver_unit|line_counter_sig_1\)
3414
3415 -- pragma translate_off
3416 GENERIC MAP (
3417         cin0_used => "true",
3418         cin1_used => "true",
3419         lut_mask => "6c7f",
3420         operation_mode => "arithmetic",
3421         output_mode => "comb_only",
3422         register_cascade_mode => "off",
3423         sum_lutc_input => "cin",
3424         synch_mode => "off")
3425 -- pragma translate_on
3426 PORT MAP (
3427         dataa => \vga_driver_unit|line_counter_sig_1\,
3428         datab => \vga_driver_unit|line_counter_sig_2\,
3429         cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(1),
3430         cin1 => \vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9\,
3431         devclrn => ww_devclrn,
3432         devpor => ww_devpor,
3433         combout => \vga_driver_unit|un1_line_counter_sig_combout\(3),
3434         cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(3),
3435         cout1 => \vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11\);
3436
3437 \vga_driver_unit|line_counter_sig_2_\ : stratix_lcell
3438 -- Equation(s):
3439 -- \vga_driver_unit|line_counter_sig_2\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(3) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, )
3440
3441 -- pragma translate_off
3442 GENERIC MAP (
3443         lut_mask => "ff0f",
3444         operation_mode => "normal",
3445         output_mode => "reg_only",
3446         register_cascade_mode => "off",
3447         sum_lutc_input => "datac",
3448         synch_mode => "on")
3449 -- pragma translate_on
3450 PORT MAP (
3451         clk => \clk_pin~combout\,
3452         datac => \vga_driver_unit|un10_line_counter_siglto8\,
3453         datad => \vga_driver_unit|un1_line_counter_sig_combout\(3),
3454         aclr => GND,
3455         sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\,
3456         devclrn => ww_devclrn,
3457         devpor => ww_devpor,
3458         regout => \vga_driver_unit|line_counter_sig_2\);
3459
3460 \vga_driver_unit|un1_line_counter_sig_4_\ : stratix_lcell
3461 -- Equation(s):
3462 -- \vga_driver_unit|un1_line_counter_sig_combout\(4) = \vga_driver_unit|line_counter_sig_3\ $ !\vga_driver_unit|un1_line_counter_sig_cout\(2)
3463 -- \vga_driver_unit|un1_line_counter_sig_cout\(4) = CARRY(\vga_driver_unit|line_counter_sig_4\ & \vga_driver_unit|line_counter_sig_3\ & !\vga_driver_unit|un1_line_counter_sig_cout\(2))
3464 -- \vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19\ = CARRY(\vga_driver_unit|line_counter_sig_4\ & \vga_driver_unit|line_counter_sig_3\ & !\vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17\)
3465
3466 -- pragma translate_off
3467 GENERIC MAP (
3468         cin0_used => "true",
3469         cin1_used => "true",
3470         lut_mask => "c308",
3471         operation_mode => "arithmetic",
3472         output_mode => "comb_only",
3473         register_cascade_mode => "off",
3474         sum_lutc_input => "cin",
3475         synch_mode => "off")
3476 -- pragma translate_on
3477 PORT MAP (
3478         dataa => \vga_driver_unit|line_counter_sig_4\,
3479         datab => \vga_driver_unit|line_counter_sig_3\,
3480         cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(2),
3481         cin1 => \vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17\,
3482         devclrn => ww_devclrn,
3483         devpor => ww_devpor,
3484         combout => \vga_driver_unit|un1_line_counter_sig_combout\(4),
3485         cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(4),
3486         cout1 => \vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19\);
3487
3488 \vga_driver_unit|line_counter_sig_3_\ : stratix_lcell
3489 -- Equation(s):
3490 -- \vga_driver_unit|line_counter_sig_3\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(4) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, )
3491
3492 -- pragma translate_off
3493 GENERIC MAP (
3494         lut_mask => "f3f3",
3495         operation_mode => "normal",
3496         output_mode => "reg_only",
3497         register_cascade_mode => "off",
3498         sum_lutc_input => "datac",
3499         synch_mode => "on")
3500 -- pragma translate_on
3501 PORT MAP (
3502         clk => \clk_pin~combout\,
3503         datab => \vga_driver_unit|un10_line_counter_siglto8\,
3504         datac => \vga_driver_unit|un1_line_counter_sig_combout\(4),
3505         aclr => GND,
3506         sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\,
3507         devclrn => ww_devclrn,
3508         devpor => ww_devpor,
3509         regout => \vga_driver_unit|line_counter_sig_3\);
3510
3511 \vga_driver_unit|un1_line_counter_sig_5_\ : stratix_lcell
3512 -- Equation(s):
3513 -- \vga_driver_unit|un1_line_counter_sig_combout\(5) = \vga_driver_unit|line_counter_sig_4\ $ (\vga_driver_unit|line_counter_sig_3\ & !\vga_driver_unit|un1_line_counter_sig_cout\(3))
3514 -- \vga_driver_unit|un1_line_counter_sig_cout\(5) = CARRY(\vga_driver_unit|line_counter_sig_4\ & \vga_driver_unit|line_counter_sig_3\ & !\vga_driver_unit|un1_line_counter_sig_cout\(3))
3515 -- \vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13\ = CARRY(\vga_driver_unit|line_counter_sig_4\ & \vga_driver_unit|line_counter_sig_3\ & !\vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11\)
3516
3517 -- pragma translate_off
3518 GENERIC MAP (
3519         cin0_used => "true",
3520         cin1_used => "true",
3521         lut_mask => "a608",
3522         operation_mode => "arithmetic",
3523         output_mode => "comb_only",
3524         register_cascade_mode => "off",
3525         sum_lutc_input => "cin",
3526         synch_mode => "off")
3527 -- pragma translate_on
3528 PORT MAP (
3529         dataa => \vga_driver_unit|line_counter_sig_4\,
3530         datab => \vga_driver_unit|line_counter_sig_3\,
3531         cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(3),
3532         cin1 => \vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11\,
3533         devclrn => ww_devclrn,
3534         devpor => ww_devpor,
3535         combout => \vga_driver_unit|un1_line_counter_sig_combout\(5),
3536         cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(5),
3537         cout1 => \vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13\);
3538
3539 \vga_driver_unit|line_counter_sig_4_\ : stratix_lcell
3540 -- Equation(s):
3541 -- \vga_driver_unit|line_counter_sig_4\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(5) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, )
3542
3543 -- pragma translate_off
3544 GENERIC MAP (
3545         lut_mask => "ff0f",
3546         operation_mode => "normal",
3547         output_mode => "reg_only",
3548         register_cascade_mode => "off",
3549         sum_lutc_input => "datac",
3550         synch_mode => "on")
3551 -- pragma translate_on
3552 PORT MAP (
3553         clk => \clk_pin~combout\,
3554         datac => \vga_driver_unit|un10_line_counter_siglto8\,
3555         datad => \vga_driver_unit|un1_line_counter_sig_combout\(5),
3556         aclr => GND,
3557         sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\,
3558         devclrn => ww_devclrn,
3559         devpor => ww_devpor,
3560         regout => \vga_driver_unit|line_counter_sig_4\);
3561
3562 \vga_driver_unit|un1_line_counter_sig_6_\ : stratix_lcell
3563 -- Equation(s):
3564 -- \vga_driver_unit|un1_line_counter_sig_combout\(6) = \vga_driver_unit|line_counter_sig_5\ $ (\vga_driver_unit|un1_line_counter_sig_cout\(4))
3565 -- \vga_driver_unit|un1_line_counter_sig_cout\(6) = CARRY(!\vga_driver_unit|un1_line_counter_sig_cout\(4) # !\vga_driver_unit|line_counter_sig_6\ # !\vga_driver_unit|line_counter_sig_5\)
3566 -- \vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21\ = CARRY(!\vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19\ # !\vga_driver_unit|line_counter_sig_6\ # !\vga_driver_unit|line_counter_sig_5\)
3567
3568 -- pragma translate_off
3569 GENERIC MAP (
3570         cin0_used => "true",
3571         cin1_used => "true",
3572         lut_mask => "5a7f",
3573         operation_mode => "arithmetic",
3574         output_mode => "comb_only",
3575         register_cascade_mode => "off",
3576         sum_lutc_input => "cin",
3577         synch_mode => "off")
3578 -- pragma translate_on
3579 PORT MAP (
3580         dataa => \vga_driver_unit|line_counter_sig_5\,
3581         datab => \vga_driver_unit|line_counter_sig_6\,
3582         cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(4),
3583         cin1 => \vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19\,
3584         devclrn => ww_devclrn,
3585         devpor => ww_devpor,
3586         combout => \vga_driver_unit|un1_line_counter_sig_combout\(6),
3587         cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(6),
3588         cout1 => \vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21\);
3589
3590 \vga_driver_unit|line_counter_sig_5_\ : stratix_lcell
3591 -- Equation(s):
3592 -- \vga_driver_unit|line_counter_sig_5\ = DFFEAS(\vga_driver_unit|un10_line_counter_siglto8\ & (\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\ & \vga_driver_unit|un1_line_counter_sig_combout\(6)), GLOBAL(\clk_pin~combout\), VCC, , , , , , )
3593
3594 -- pragma translate_off
3595 GENERIC MAP (
3596         lut_mask => "a000",
3597         operation_mode => "normal",
3598         output_mode => "reg_only",
3599         register_cascade_mode => "off",
3600         sum_lutc_input => "datac",
3601         synch_mode => "off")
3602 -- pragma translate_on
3603 PORT MAP (
3604         clk => \clk_pin~combout\,
3605         dataa => \vga_driver_unit|un10_line_counter_siglto8\,
3606         datac => \vga_driver_unit|line_counter_next_0_sqmuxa_1_1\,
3607         datad => \vga_driver_unit|un1_line_counter_sig_combout\(6),
3608         aclr => GND,
3609         devclrn => ww_devclrn,
3610         devpor => ww_devpor,
3611         regout => \vga_driver_unit|line_counter_sig_5\);
3612
3613 \vga_driver_unit|un1_line_counter_sig_7_\ : stratix_lcell
3614 -- Equation(s):
3615 -- \vga_driver_unit|un1_line_counter_sig_combout\(7) = \vga_driver_unit|line_counter_sig_6\ $ (\vga_driver_unit|line_counter_sig_5\ & \vga_driver_unit|un1_line_counter_sig_cout\(5))
3616 -- \vga_driver_unit|un1_line_counter_sig_cout\(7) = CARRY(!\vga_driver_unit|un1_line_counter_sig_cout\(5) # !\vga_driver_unit|line_counter_sig_5\ # !\vga_driver_unit|line_counter_sig_6\)
3617 -- \vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15\ = CARRY(!\vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13\ # !\vga_driver_unit|line_counter_sig_5\ # !\vga_driver_unit|line_counter_sig_6\)
3618
3619 -- pragma translate_off
3620 GENERIC MAP (
3621         cin0_used => "true",
3622         cin1_used => "true",
3623         lut_mask => "6a7f",
3624         operation_mode => "arithmetic",
3625         output_mode => "comb_only",
3626         register_cascade_mode => "off",
3627         sum_lutc_input => "cin",
3628         synch_mode => "off")
3629 -- pragma translate_on
3630 PORT MAP (
3631         dataa => \vga_driver_unit|line_counter_sig_6\,
3632         datab => \vga_driver_unit|line_counter_sig_5\,
3633         cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(5),
3634         cin1 => \vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13\,
3635         devclrn => ww_devclrn,
3636         devpor => ww_devpor,
3637         combout => \vga_driver_unit|un1_line_counter_sig_combout\(7),
3638         cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(7),
3639         cout1 => \vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15\);
3640
3641 \vga_driver_unit|line_counter_sig_6_\ : stratix_lcell
3642 -- Equation(s):
3643 -- \vga_driver_unit|line_counter_sig_6\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(7) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, )
3644
3645 -- pragma translate_off
3646 GENERIC MAP (
3647         lut_mask => "f0ff",
3648         operation_mode => "normal",
3649         output_mode => "reg_only",
3650         register_cascade_mode => "off",
3651         sum_lutc_input => "datac",
3652         synch_mode => "on")
3653 -- pragma translate_on
3654 PORT MAP (
3655         clk => \clk_pin~combout\,
3656         datac => \vga_driver_unit|un1_line_counter_sig_combout\(7),
3657         datad => \vga_driver_unit|un10_line_counter_siglto8\,
3658         aclr => GND,
3659         sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\,
3660         devclrn => ww_devclrn,
3661         devpor => ww_devpor,
3662         regout => \vga_driver_unit|line_counter_sig_6\);
3663
3664 \vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2\ : stratix_lcell
3665 -- Equation(s):
3666 -- \vga_driver_unit|un10_line_counter_siglt4_2\ = !\vga_driver_unit|line_counter_sig_0\ # !\vga_driver_unit|line_counter_sig_3\ # !\vga_driver_unit|line_counter_sig_4\
3667
3668 -- pragma translate_off
3669 GENERIC MAP (
3670         lut_mask => "77ff",
3671         operation_mode => "normal",
3672         output_mode => "comb_only",
3673         register_cascade_mode => "off",
3674         sum_lutc_input => "datac",
3675         synch_mode => "off")
3676 -- pragma translate_on
3677 PORT MAP (
3678         dataa => \vga_driver_unit|line_counter_sig_4\,
3679         datab => \vga_driver_unit|line_counter_sig_3\,
3680         datad => \vga_driver_unit|line_counter_sig_0\,
3681         devclrn => ww_devclrn,
3682         devpor => ww_devpor,
3683         combout => \vga_driver_unit|un10_line_counter_siglt4_2\);
3684
3685 \vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5\ : stratix_lcell
3686 -- Equation(s):
3687 -- \vga_driver_unit|un10_line_counter_siglto5\ = !\vga_driver_unit|line_counter_sig_5\ & (\vga_driver_unit|un10_line_counter_siglt4_2\ # !\vga_driver_unit|line_counter_sig_2\ # !\vga_driver_unit|line_counter_sig_1\)
3688
3689 -- pragma translate_off
3690 GENERIC MAP (
3691         lut_mask => "0f07",
3692         operation_mode => "normal",
3693         output_mode => "comb_only",
3694         register_cascade_mode => "off",
3695         sum_lutc_input => "datac",
3696         synch_mode => "off")
3697 -- pragma translate_on
3698 PORT MAP (
3699         dataa => \vga_driver_unit|line_counter_sig_1\,
3700         datab => \vga_driver_unit|line_counter_sig_2\,
3701         datac => \vga_driver_unit|line_counter_sig_5\,
3702         datad => \vga_driver_unit|un10_line_counter_siglt4_2\,
3703         devclrn => ww_devclrn,
3704         devpor => ww_devpor,
3705         combout => \vga_driver_unit|un10_line_counter_siglto5\);
3706
3707 \vga_driver_unit|un1_line_counter_sig_8_\ : stratix_lcell
3708 -- Equation(s):
3709 -- \vga_driver_unit|un1_line_counter_sig_combout\(8) = \vga_driver_unit|line_counter_sig_7\ $ (!\vga_driver_unit|un1_line_counter_sig_cout\(6))
3710
3711 -- pragma translate_off
3712 GENERIC MAP (
3713         cin0_used => "true",
3714         cin1_used => "true",
3715         lut_mask => "a5a5",
3716         operation_mode => "normal",
3717         output_mode => "comb_only",
3718         register_cascade_mode => "off",
3719         sum_lutc_input => "cin",
3720         synch_mode => "off")
3721 -- pragma translate_on
3722 PORT MAP (
3723         dataa => \vga_driver_unit|line_counter_sig_7\,
3724         cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(6),
3725         cin1 => \vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21\,
3726         devclrn => ww_devclrn,
3727         devpor => ww_devpor,
3728         combout => \vga_driver_unit|un1_line_counter_sig_combout\(8));
3729
3730 \vga_driver_unit|line_counter_sig_7_\ : stratix_lcell
3731 -- Equation(s):
3732 -- \vga_driver_unit|line_counter_sig_7\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(8) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, )
3733
3734 -- pragma translate_off
3735 GENERIC MAP (
3736         lut_mask => "ff0f",
3737         operation_mode => "normal",
3738         output_mode => "reg_only",
3739         register_cascade_mode => "off",
3740         sum_lutc_input => "datac",
3741         synch_mode => "on")
3742 -- pragma translate_on
3743 PORT MAP (
3744         clk => \clk_pin~combout\,
3745         datac => \vga_driver_unit|un10_line_counter_siglto8\,
3746         datad => \vga_driver_unit|un1_line_counter_sig_combout\(8),
3747         aclr => GND,
3748         sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\,
3749         devclrn => ww_devclrn,
3750         devpor => ww_devpor,
3751         regout => \vga_driver_unit|line_counter_sig_7\);
3752
3753 \vga_driver_unit|un1_line_counter_sig_9_\ : stratix_lcell
3754 -- Equation(s):
3755 -- \vga_driver_unit|un1_line_counter_sig_combout\(9) = \vga_driver_unit|line_counter_sig_8\ $ (\vga_driver_unit|line_counter_sig_7\ & !\vga_driver_unit|un1_line_counter_sig_cout\(7))
3756
3757 -- pragma translate_off
3758 GENERIC MAP (
3759         cin0_used => "true",
3760         cin1_used => "true",
3761         lut_mask => "f30c",
3762         operation_mode => "normal",
3763         output_mode => "comb_only",
3764         register_cascade_mode => "off",
3765         sum_lutc_input => "cin",
3766         synch_mode => "off")
3767 -- pragma translate_on
3768 PORT MAP (
3769         datab => \vga_driver_unit|line_counter_sig_7\,
3770         datad => \vga_driver_unit|line_counter_sig_8\,
3771         cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(7),
3772         cin1 => \vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15\,
3773         devclrn => ww_devclrn,
3774         devpor => ww_devpor,
3775         combout => \vga_driver_unit|un1_line_counter_sig_combout\(9));
3776
3777 \vga_driver_unit|line_counter_sig_8_\ : stratix_lcell
3778 -- Equation(s):
3779 -- \vga_driver_unit|line_counter_sig_8\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(9) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, )
3780
3781 -- pragma translate_off
3782 GENERIC MAP (
3783         lut_mask => "ff33",
3784         operation_mode => "normal",
3785         output_mode => "reg_only",
3786         register_cascade_mode => "off",
3787         sum_lutc_input => "datac",
3788         synch_mode => "on")
3789 -- pragma translate_on
3790 PORT MAP (
3791         clk => \clk_pin~combout\,
3792         datab => \vga_driver_unit|un10_line_counter_siglto8\,
3793         datad => \vga_driver_unit|un1_line_counter_sig_combout\(9),
3794         aclr => GND,
3795         sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\,
3796         devclrn => ww_devclrn,
3797         devpor => ww_devpor,
3798         regout => \vga_driver_unit|line_counter_sig_8\);
3799
3800 \vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8\ : stratix_lcell
3801 -- Equation(s):
3802 -- \vga_driver_unit|un10_line_counter_siglto8\ = \vga_driver_unit|un10_line_counter_siglto5\ # !\vga_driver_unit|line_counter_sig_8\ # !\vga_driver_unit|line_counter_sig_7\ # !\vga_driver_unit|line_counter_sig_6\
3803
3804 -- pragma translate_off
3805 GENERIC MAP (
3806         lut_mask => "dfff",
3807         operation_mode => "normal",
3808         output_mode => "comb_only",
3809         register_cascade_mode => "off",
3810         sum_lutc_input => "datac",
3811         synch_mode => "off")
3812 -- pragma translate_on
3813 PORT MAP (
3814         dataa => \vga_driver_unit|line_counter_sig_6\,
3815         datab => \vga_driver_unit|un10_line_counter_siglto5\,
3816         datac => \vga_driver_unit|line_counter_sig_7\,
3817         datad => \vga_driver_unit|line_counter_sig_8\,
3818         devclrn => ww_devclrn,
3819         devpor => ww_devpor,
3820         combout => \vga_driver_unit|un10_line_counter_siglto8\);
3821
3822 \vga_driver_unit|line_counter_sig_0_\ : stratix_lcell
3823 -- Equation(s):
3824 -- \vga_driver_unit|line_counter_sig_0\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(1) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, )
3825
3826 -- pragma translate_off
3827 GENERIC MAP (
3828         lut_mask => "ff33",
3829         operation_mode => "normal",
3830         output_mode => "reg_only",
3831         register_cascade_mode => "off",
3832         sum_lutc_input => "datac",
3833         synch_mode => "on")
3834 -- pragma translate_on
3835 PORT MAP (
3836         clk => \clk_pin~combout\,
3837         datab => \vga_driver_unit|un10_line_counter_siglto8\,
3838         datad => \vga_driver_unit|un1_line_counter_sig_combout\(1),
3839         aclr => GND,
3840         sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\,
3841         devclrn => ww_devclrn,
3842         devpor => ww_devpor,
3843         regout => \vga_driver_unit|line_counter_sig_0\);
3844
3845 r0_pin_out : stratix_io
3846 -- pragma translate_off
3847 GENERIC MAP (
3848         ddio_mode => "none",
3849         input_async_reset => "none",
3850         input_power_up => "low",
3851         input_register_mode => "none",
3852         input_sync_reset => "none",
3853         oe_async_reset => "none",
3854         oe_power_up => "low",
3855         oe_register_mode => "none",
3856         oe_sync_reset => "none",
3857         operation_mode => "output",
3858         output_async_reset => "none",
3859         output_power_up => "low",
3860         output_register_mode => "none",
3861         output_sync_reset => "none")
3862 -- pragma translate_on
3863 PORT MAP (
3864         datain => \vga_control_unit|r\,
3865         devclrn => ww_devclrn,
3866         devpor => ww_devpor,
3867         devoe => ww_devoe,
3868         oe => VCC,
3869         padio => ww_r0_pin);
3870
3871 r1_pin_out : stratix_io
3872 -- pragma translate_off
3873 GENERIC MAP (
3874         ddio_mode => "none",
3875         input_async_reset => "none",
3876         input_power_up => "low",
3877         input_register_mode => "none",
3878         input_sync_reset => "none",
3879         oe_async_reset => "none",
3880         oe_power_up => "low",
3881         oe_register_mode => "none",
3882         oe_sync_reset => "none",
3883         operation_mode => "output",
3884         output_async_reset => "none",
3885         output_power_up => "low",
3886         output_register_mode => "none",
3887         output_sync_reset => "none")
3888 -- pragma translate_on
3889 PORT MAP (
3890         datain => \vga_control_unit|r\,
3891         devclrn => ww_devclrn,
3892         devpor => ww_devpor,
3893         devoe => ww_devoe,
3894         oe => VCC,
3895         padio => ww_r1_pin);
3896
3897 r2_pin_out : stratix_io
3898 -- pragma translate_off
3899 GENERIC MAP (
3900         ddio_mode => "none",
3901         input_async_reset => "none",
3902         input_power_up => "low",
3903         input_register_mode => "none",
3904         input_sync_reset => "none",
3905         oe_async_reset => "none",
3906         oe_power_up => "low",
3907         oe_register_mode => "none",
3908         oe_sync_reset => "none",
3909         operation_mode => "output",
3910         output_async_reset => "none",
3911         output_power_up => "low",
3912         output_register_mode => "none",
3913         output_sync_reset => "none")
3914 -- pragma translate_on
3915 PORT MAP (
3916         datain => \vga_control_unit|r\,
3917         devclrn => ww_devclrn,
3918         devpor => ww_devpor,
3919         devoe => ww_devoe,
3920         oe => VCC,
3921         padio => ww_r2_pin);
3922
3923 g0_pin_out : stratix_io
3924 -- pragma translate_off
3925 GENERIC MAP (
3926         ddio_mode => "none",
3927         input_async_reset => "none",
3928         input_power_up => "low",
3929         input_register_mode => "none",
3930         input_sync_reset => "none",
3931         oe_async_reset => "none",
3932         oe_power_up => "low",
3933         oe_register_mode => "none",
3934         oe_sync_reset => "none",
3935         operation_mode => "output",
3936         output_async_reset => "none",
3937         output_power_up => "low",
3938         output_register_mode => "none",
3939         output_sync_reset => "none")
3940 -- pragma translate_on
3941 PORT MAP (
3942         datain => \vga_control_unit|g\,
3943         devclrn => ww_devclrn,
3944         devpor => ww_devpor,
3945         devoe => ww_devoe,
3946         oe => VCC,
3947         padio => ww_g0_pin);
3948
3949 g1_pin_out : stratix_io
3950 -- pragma translate_off
3951 GENERIC MAP (
3952         ddio_mode => "none",
3953         input_async_reset => "none",
3954         input_power_up => "low",
3955         input_register_mode => "none",
3956         input_sync_reset => "none",
3957         oe_async_reset => "none",
3958         oe_power_up => "low",
3959         oe_register_mode => "none",
3960         oe_sync_reset => "none",
3961         operation_mode => "output",
3962         output_async_reset => "none",
3963         output_power_up => "low",
3964         output_register_mode => "none",
3965         output_sync_reset => "none")
3966 -- pragma translate_on
3967 PORT MAP (
3968         datain => \vga_control_unit|g\,
3969         devclrn => ww_devclrn,
3970         devpor => ww_devpor,
3971         devoe => ww_devoe,
3972         oe => VCC,
3973         padio => ww_g1_pin);
3974
3975 g2_pin_out : stratix_io
3976 -- pragma translate_off
3977 GENERIC MAP (
3978         ddio_mode => "none",
3979         input_async_reset => "none",
3980         input_power_up => "low",
3981         input_register_mode => "none",
3982         input_sync_reset => "none",
3983         oe_async_reset => "none",
3984         oe_power_up => "low",
3985         oe_register_mode => "none",
3986         oe_sync_reset => "none",
3987         operation_mode => "output",
3988         output_async_reset => "none",
3989         output_power_up => "low",
3990         output_register_mode => "none",
3991         output_sync_reset => "none")
3992 -- pragma translate_on
3993 PORT MAP (
3994         datain => \vga_control_unit|g\,
3995         devclrn => ww_devclrn,
3996         devpor => ww_devpor,
3997         devoe => ww_devoe,
3998         oe => VCC,
3999         padio => ww_g2_pin);
4000
4001 b0_pin_out : stratix_io
4002 -- pragma translate_off
4003 GENERIC MAP (
4004         ddio_mode => "none",
4005         input_async_reset => "none",
4006         input_power_up => "low",
4007         input_register_mode => "none",
4008         input_sync_reset => "none",
4009         oe_async_reset => "none",
4010         oe_power_up => "low",
4011         oe_register_mode => "none",
4012         oe_sync_reset => "none",
4013         operation_mode => "output",
4014         output_async_reset => "none",
4015         output_power_up => "low",
4016         output_register_mode => "none",
4017         output_sync_reset => "none")
4018 -- pragma translate_on
4019 PORT MAP (
4020         datain => \vga_control_unit|b\,
4021         devclrn => ww_devclrn,
4022         devpor => ww_devpor,
4023         devoe => ww_devoe,
4024         oe => VCC,
4025         padio => ww_b0_pin);
4026
4027 b1_pin_out : stratix_io
4028 -- pragma translate_off
4029 GENERIC MAP (
4030         ddio_mode => "none",
4031         input_async_reset => "none",
4032         input_power_up => "low",
4033         input_register_mode => "none",
4034         input_sync_reset => "none",
4035         oe_async_reset => "none",
4036         oe_power_up => "low",
4037         oe_register_mode => "none",
4038         oe_sync_reset => "none",
4039         operation_mode => "output",
4040         output_async_reset => "none",
4041         output_power_up => "low",
4042         output_register_mode => "none",
4043         output_sync_reset => "none")
4044 -- pragma translate_on
4045 PORT MAP (
4046         datain => \vga_control_unit|b\,
4047         devclrn => ww_devclrn,
4048         devpor => ww_devpor,
4049         devoe => ww_devoe,
4050         oe => VCC,
4051         padio => ww_b1_pin);
4052
4053 hsync_pin_out : stratix_io
4054 -- pragma translate_off
4055 GENERIC MAP (
4056         ddio_mode => "none",
4057         input_async_reset => "none",
4058         input_power_up => "low",
4059         input_register_mode => "none",
4060         input_sync_reset => "none",
4061         oe_async_reset => "none",
4062         oe_power_up => "low",
4063         oe_register_mode => "none",
4064         oe_sync_reset => "none",
4065         operation_mode => "output",
4066         output_async_reset => "none",
4067         output_power_up => "low",
4068         output_register_mode => "none",
4069         output_sync_reset => "none")
4070 -- pragma translate_on
4071 PORT MAP (
4072         datain => \vga_driver_unit|h_sync\,
4073         devclrn => ww_devclrn,
4074         devpor => ww_devpor,
4075         devoe => ww_devoe,
4076         oe => VCC,
4077         padio => ww_hsync_pin);
4078
4079 vsync_pin_out : stratix_io
4080 -- pragma translate_off
4081 GENERIC MAP (
4082         ddio_mode => "none",
4083         input_async_reset => "none",
4084         input_power_up => "low",
4085         input_register_mode => "none",
4086         input_sync_reset => "none",
4087         oe_async_reset => "none",
4088         oe_power_up => "low",
4089         oe_register_mode => "none",
4090         oe_sync_reset => "none",
4091         operation_mode => "output",
4092         output_async_reset => "none",
4093         output_power_up => "low",
4094         output_register_mode => "none",
4095         output_sync_reset => "none")
4096 -- pragma translate_on
4097 PORT MAP (
4098         datain => \vga_driver_unit|v_sync\,
4099         devclrn => ww_devclrn,
4100         devpor => ww_devpor,
4101         devoe => ww_devoe,
4102         oe => VCC,
4103         padio => ww_vsync_pin);
4104
4105 \seven_seg_pin_tri_0_\ : stratix_io
4106 -- pragma translate_off
4107 GENERIC MAP (
4108         ddio_mode => "none",
4109         input_async_reset => "none",
4110         input_power_up => "low",
4111         input_register_mode => "none",
4112         input_sync_reset => "none",
4113         oe_async_reset => "none",
4114         oe_power_up => "low",
4115         oe_register_mode => "none",
4116         oe_sync_reset => "none",
4117         operation_mode => "output",
4118         output_async_reset => "none",
4119         output_power_up => "low",
4120         output_register_mode => "none",
4121         output_sync_reset => "none")
4122 -- pragma translate_on
4123 PORT MAP (
4124         datain => \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\,
4125         devclrn => ww_devclrn,
4126         devpor => ww_devpor,
4127         devoe => ww_devoe,
4128         oe => VCC,
4129         padio => ww_seven_seg_pin(0));
4130
4131 \seven_seg_pin_out_1_\ : stratix_io
4132 -- pragma translate_off
4133 GENERIC MAP (
4134         ddio_mode => "none",
4135         input_async_reset => "none",
4136         input_power_up => "low",
4137         input_register_mode => "none",
4138         input_sync_reset => "none",
4139         oe_async_reset => "none",
4140         oe_power_up => "low",
4141         oe_register_mode => "none",
4142         oe_sync_reset => "none",
4143         operation_mode => "output",
4144         output_async_reset => "none",
4145         output_power_up => "low",
4146         output_register_mode => "none",
4147         output_sync_reset => "none")
4148 -- pragma translate_on
4149 PORT MAP (
4150         datain => \vga_driver_unit|un6_dly_counter_0_x\,
4151         devclrn => ww_devclrn,
4152         devpor => ww_devpor,
4153         devoe => ww_devoe,
4154         oe => VCC,
4155         padio => ww_seven_seg_pin(1));
4156
4157 \seven_seg_pin_out_2_\ : stratix_io
4158 -- pragma translate_off
4159 GENERIC MAP (
4160         ddio_mode => "none",
4161         input_async_reset => "none",
4162         input_power_up => "low",
4163         input_register_mode => "none",
4164         input_sync_reset => "none",
4165         oe_async_reset => "none",
4166         oe_power_up => "low",
4167         oe_register_mode => "none",
4168         oe_sync_reset => "none",
4169         operation_mode => "output",
4170         output_async_reset => "none",
4171         output_power_up => "low",
4172         output_register_mode => "none",
4173         output_sync_reset => "none")
4174 -- pragma translate_on
4175 PORT MAP (
4176         datain => \vga_driver_unit|un6_dly_counter_0_x\,
4177         devclrn => ww_devclrn,
4178         devpor => ww_devpor,
4179         devoe => ww_devoe,
4180         oe => VCC,
4181         padio => ww_seven_seg_pin(2));
4182
4183 \seven_seg_pin_tri_3_\ : stratix_io
4184 -- pragma translate_off
4185 GENERIC MAP (
4186         ddio_mode => "none",
4187         input_async_reset => "none",
4188         input_power_up => "low",
4189         input_register_mode => "none",
4190         input_sync_reset => "none",
4191         oe_async_reset => "none",
4192         oe_power_up => "low",
4193         oe_register_mode => "none",
4194         oe_sync_reset => "none",
4195         operation_mode => "output",
4196         output_async_reset => "none",
4197         output_power_up => "low",
4198         output_register_mode => "none",
4199         output_sync_reset => "none")
4200 -- pragma translate_on
4201 PORT MAP (
4202         datain => \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\,
4203         devclrn => ww_devclrn,
4204         devpor => ww_devpor,
4205         devoe => ww_devoe,
4206         oe => VCC,
4207         padio => ww_seven_seg_pin(3));
4208
4209 \seven_seg_pin_tri_4_\ : stratix_io
4210 -- pragma translate_off
4211 GENERIC MAP (
4212         ddio_mode => "none",
4213         input_async_reset => "none",
4214         input_power_up => "low",
4215         input_register_mode => "none",
4216         input_sync_reset => "none",
4217         oe_async_reset => "none",
4218         oe_power_up => "low",
4219         oe_register_mode => "none",
4220         oe_sync_reset => "none",
4221         operation_mode => "output",
4222         output_async_reset => "none",
4223         output_power_up => "low",
4224         output_register_mode => "none",
4225         output_sync_reset => "none")
4226 -- pragma translate_on
4227 PORT MAP (
4228         datain => \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\,
4229         devclrn => ww_devclrn,
4230         devpor => ww_devpor,
4231         devoe => ww_devoe,
4232         oe => VCC,
4233         padio => ww_seven_seg_pin(4));
4234
4235 \seven_seg_pin_tri_5_\ : stratix_io
4236 -- pragma translate_off
4237 GENERIC MAP (
4238         ddio_mode => "none",
4239         input_async_reset => "none",
4240         input_power_up => "low",
4241         input_register_mode => "none",
4242         input_sync_reset => "none",
4243         oe_async_reset => "none",
4244         oe_power_up => "low",
4245         oe_register_mode => "none",
4246         oe_sync_reset => "none",
4247         operation_mode => "output",
4248         output_async_reset => "none",
4249         output_power_up => "low",
4250         output_register_mode => "none",
4251         output_sync_reset => "none")
4252 -- pragma translate_on
4253 PORT MAP (
4254         datain => \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\,
4255         devclrn => ww_devclrn,
4256         devpor => ww_devpor,
4257         devoe => ww_devoe,
4258         oe => VCC,
4259         padio => ww_seven_seg_pin(5));
4260
4261 \seven_seg_pin_tri_6_\ : stratix_io
4262 -- pragma translate_off
4263 GENERIC MAP (
4264         ddio_mode => "none",
4265         input_async_reset => "none",
4266         input_power_up => "low",
4267         input_register_mode => "none",
4268         input_sync_reset => "none",
4269         oe_async_reset => "none",
4270         oe_power_up => "low",
4271         oe_register_mode => "none",
4272         oe_sync_reset => "none",
4273         operation_mode => "output",
4274         output_async_reset => "none",
4275         output_power_up => "low",
4276         output_register_mode => "none",
4277         output_sync_reset => "none")
4278 -- pragma translate_on
4279 PORT MAP (
4280         datain => \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\,
4281         devclrn => ww_devclrn,
4282         devpor => ww_devpor,
4283         devoe => ww_devoe,
4284         oe => VCC,
4285         padio => ww_seven_seg_pin(6));
4286
4287 \seven_seg_pin_out_7_\ : stratix_io
4288 -- pragma translate_off
4289 GENERIC MAP (
4290         ddio_mode => "none",
4291         input_async_reset => "none",
4292         input_power_up => "low",
4293         input_register_mode => "none",
4294         input_sync_reset => "none",
4295         oe_async_reset => "none",
4296         oe_power_up => "low",
4297         oe_register_mode => "none",
4298         oe_sync_reset => "none",
4299         operation_mode => "output",
4300         output_async_reset => "none",
4301         output_power_up => "low",
4302         output_register_mode => "none",
4303         output_sync_reset => "none")
4304 -- pragma translate_on
4305 PORT MAP (
4306         datain => \vga_driver_unit|un6_dly_counter_0_x\,
4307         devclrn => ww_devclrn,
4308         devpor => ww_devpor,
4309         devoe => ww_devoe,
4310         oe => VCC,
4311         padio => ww_seven_seg_pin(7));
4312
4313 \seven_seg_pin_out_8_\ : stratix_io
4314 -- pragma translate_off
4315 GENERIC MAP (
4316         ddio_mode => "none",
4317         input_async_reset => "none",
4318         input_power_up => "low",
4319         input_register_mode => "none",
4320         input_sync_reset => "none",
4321         oe_async_reset => "none",
4322         oe_power_up => "low",
4323         oe_register_mode => "none",
4324         oe_sync_reset => "none",
4325         operation_mode => "output",
4326         output_async_reset => "none",
4327         output_power_up => "low",
4328         output_register_mode => "none",
4329         output_sync_reset => "none")
4330 -- pragma translate_on
4331 PORT MAP (
4332         datain => \vga_driver_unit|un6_dly_counter_0_x\,
4333         devclrn => ww_devclrn,
4334         devpor => ww_devpor,
4335         devoe => ww_devoe,
4336         oe => VCC,
4337         padio => ww_seven_seg_pin(8));
4338
4339 \seven_seg_pin_out_9_\ : stratix_io
4340 -- pragma translate_off
4341 GENERIC MAP (
4342         ddio_mode => "none",
4343         input_async_reset => "none",
4344         input_power_up => "low",
4345         input_register_mode => "none",
4346         input_sync_reset => "none",
4347         oe_async_reset => "none",
4348         oe_power_up => "low",
4349         oe_register_mode => "none",
4350         oe_sync_reset => "none",
4351         operation_mode => "output",
4352         output_async_reset => "none",
4353         output_power_up => "low",
4354         output_register_mode => "none",
4355         output_sync_reset => "none")
4356 -- pragma translate_on
4357 PORT MAP (
4358         datain => \vga_driver_unit|un6_dly_counter_0_x\,
4359         devclrn => ww_devclrn,
4360         devpor => ww_devpor,
4361         devoe => ww_devoe,
4362         oe => VCC,
4363         padio => ww_seven_seg_pin(9));
4364
4365 \seven_seg_pin_out_10_\ : stratix_io
4366 -- pragma translate_off
4367 GENERIC MAP (
4368         ddio_mode => "none",
4369         input_async_reset => "none",
4370         input_power_up => "low",
4371         input_register_mode => "none",
4372         input_sync_reset => "none",
4373         oe_async_reset => "none",
4374         oe_power_up => "low",
4375         oe_register_mode => "none",
4376         oe_sync_reset => "none",
4377         operation_mode => "output",
4378         output_async_reset => "none",
4379         output_power_up => "low",
4380         output_register_mode => "none",
4381         output_sync_reset => "none")
4382 -- pragma translate_on
4383 PORT MAP (
4384         datain => \vga_driver_unit|un6_dly_counter_0_x\,
4385         devclrn => ww_devclrn,
4386         devpor => ww_devpor,
4387         devoe => ww_devoe,
4388         oe => VCC,
4389         padio => ww_seven_seg_pin(10));
4390
4391 \seven_seg_pin_out_11_\ : stratix_io
4392 -- pragma translate_off
4393 GENERIC MAP (
4394         ddio_mode => "none",
4395         input_async_reset => "none",
4396         input_power_up => "low",
4397         input_register_mode => "none",
4398         input_sync_reset => "none",
4399         oe_async_reset => "none",
4400         oe_power_up => "low",
4401         oe_register_mode => "none",
4402         oe_sync_reset => "none",
4403         operation_mode => "output",
4404         output_async_reset => "none",
4405         output_power_up => "low",
4406         output_register_mode => "none",
4407         output_sync_reset => "none")
4408 -- pragma translate_on
4409 PORT MAP (
4410         datain => \vga_driver_unit|un6_dly_counter_0_x\,
4411         devclrn => ww_devclrn,
4412         devpor => ww_devpor,
4413         devoe => ww_devoe,
4414         oe => VCC,
4415         padio => ww_seven_seg_pin(11));
4416
4417 \seven_seg_pin_out_12_\ : stratix_io
4418 -- pragma translate_off
4419 GENERIC MAP (
4420         ddio_mode => "none",
4421         input_async_reset => "none",
4422         input_power_up => "low",
4423         input_register_mode => "none",
4424         input_sync_reset => "none",
4425         oe_async_reset => "none",
4426         oe_power_up => "low",
4427         oe_register_mode => "none",
4428         oe_sync_reset => "none",
4429         operation_mode => "output",
4430         output_async_reset => "none",
4431         output_power_up => "low",
4432         output_register_mode => "none",
4433         output_sync_reset => "none")
4434 -- pragma translate_on
4435 PORT MAP (
4436         datain => \vga_driver_unit|un6_dly_counter_0_x\,
4437         devclrn => ww_devclrn,
4438         devpor => ww_devpor,
4439         devoe => ww_devoe,
4440         oe => VCC,
4441         padio => ww_seven_seg_pin(12));
4442
4443 \seven_seg_pin_tri_13_\ : stratix_io
4444 -- pragma translate_off
4445 GENERIC MAP (
4446         ddio_mode => "none",
4447         input_async_reset => "none",
4448         input_power_up => "low",
4449         input_register_mode => "none",
4450         input_sync_reset => "none",
4451         oe_async_reset => "none",
4452         oe_power_up => "low",
4453         oe_register_mode => "none",
4454         oe_sync_reset => "none",
4455         operation_mode => "output",
4456         output_async_reset => "none",
4457         output_power_up => "low",
4458         output_register_mode => "none",
4459         output_sync_reset => "none")
4460 -- pragma translate_on
4461 PORT MAP (
4462         datain => \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\,
4463         devclrn => ww_devclrn,
4464         devpor => ww_devpor,
4465         devoe => ww_devoe,
4466         oe => VCC,
4467         padio => ww_seven_seg_pin(13));
4468
4469 d_hsync_out : stratix_io
4470 -- pragma translate_off
4471 GENERIC MAP (
4472         ddio_mode => "none",
4473         input_async_reset => "none",
4474         input_power_up => "low",
4475         input_register_mode => "none",
4476         input_sync_reset => "none",
4477         oe_async_reset => "none",
4478         oe_power_up => "low",
4479         oe_register_mode => "none",
4480         oe_sync_reset => "none",
4481         operation_mode => "output",
4482         output_async_reset => "none",
4483         output_power_up => "low",
4484         output_register_mode => "none",
4485         output_sync_reset => "none")
4486 -- pragma translate_on
4487 PORT MAP (
4488         datain => \vga_driver_unit|h_sync\,
4489         devclrn => ww_devclrn,
4490         devpor => ww_devpor,
4491         devoe => ww_devoe,
4492         oe => VCC,
4493         padio => ww_d_hsync);
4494
4495 d_vsync_out : stratix_io
4496 -- pragma translate_off
4497 GENERIC MAP (
4498         ddio_mode => "none",
4499         input_async_reset => "none",
4500         input_power_up => "low",
4501         input_register_mode => "none",
4502         input_sync_reset => "none",
4503         oe_async_reset => "none",
4504         oe_power_up => "low",
4505         oe_register_mode => "none",
4506         oe_sync_reset => "none",
4507         operation_mode => "output",
4508         output_async_reset => "none",
4509         output_power_up => "low",
4510         output_register_mode => "none",
4511         output_sync_reset => "none")
4512 -- pragma translate_on
4513 PORT MAP (
4514         datain => \vga_driver_unit|v_sync\,
4515         devclrn => ww_devclrn,
4516         devpor => ww_devpor,
4517         devoe => ww_devoe,
4518         oe => VCC,
4519         padio => ww_d_vsync);
4520
4521 \d_column_counter_out_0_\ : stratix_io
4522 -- pragma translate_off
4523 GENERIC MAP (
4524         ddio_mode => "none",
4525         input_async_reset => "none",
4526         input_power_up => "low",
4527         input_register_mode => "none",
4528         input_sync_reset => "none",
4529         oe_async_reset => "none",
4530         oe_power_up => "low",
4531         oe_register_mode => "none",
4532         oe_sync_reset => "none",
4533         operation_mode => "output",
4534         output_async_reset => "none",
4535         output_power_up => "low",
4536         output_register_mode => "none",
4537         output_sync_reset => "none")
4538 -- pragma translate_on
4539 PORT MAP (
4540         datain => \vga_driver_unit|column_counter_sig_0\,
4541         devclrn => ww_devclrn,
4542         devpor => ww_devpor,
4543         devoe => ww_devoe,
4544         oe => VCC,
4545         padio => ww_d_column_counter(0));
4546
4547 \d_column_counter_out_1_\ : stratix_io
4548 -- pragma translate_off
4549 GENERIC MAP (
4550         ddio_mode => "none",
4551         input_async_reset => "none",
4552         input_power_up => "low",
4553         input_register_mode => "none",
4554         input_sync_reset => "none",
4555         oe_async_reset => "none",
4556         oe_power_up => "low",
4557         oe_register_mode => "none",
4558         oe_sync_reset => "none",
4559         operation_mode => "output",
4560         output_async_reset => "none",
4561         output_power_up => "low",
4562         output_register_mode => "none",
4563         output_sync_reset => "none")
4564 -- pragma translate_on
4565 PORT MAP (
4566         datain => \vga_driver_unit|column_counter_sig_1\,
4567         devclrn => ww_devclrn,
4568         devpor => ww_devpor,
4569         devoe => ww_devoe,
4570         oe => VCC,
4571         padio => ww_d_column_counter(1));
4572
4573 \d_column_counter_out_2_\ : stratix_io
4574 -- pragma translate_off
4575 GENERIC MAP (
4576         ddio_mode => "none",
4577         input_async_reset => "none",
4578         input_power_up => "low",
4579         input_register_mode => "none",
4580         input_sync_reset => "none",
4581         oe_async_reset => "none",
4582         oe_power_up => "low",
4583         oe_register_mode => "none",
4584         oe_sync_reset => "none",
4585         operation_mode => "output",
4586         output_async_reset => "none",
4587         output_power_up => "low",
4588         output_register_mode => "none",
4589         output_sync_reset => "none")
4590 -- pragma translate_on
4591 PORT MAP (
4592         datain => \vga_driver_unit|column_counter_sig_2\,
4593         devclrn => ww_devclrn,
4594         devpor => ww_devpor,
4595         devoe => ww_devoe,
4596         oe => VCC,
4597         padio => ww_d_column_counter(2));
4598
4599 \d_column_counter_out_3_\ : stratix_io
4600 -- pragma translate_off
4601 GENERIC MAP (
4602         ddio_mode => "none",
4603         input_async_reset => "none",
4604         input_power_up => "low",
4605         input_register_mode => "none",
4606         input_sync_reset => "none",
4607         oe_async_reset => "none",
4608         oe_power_up => "low",
4609         oe_register_mode => "none",
4610         oe_sync_reset => "none",
4611         operation_mode => "output",
4612         output_async_reset => "none",
4613         output_power_up => "low",
4614         output_register_mode => "none",
4615         output_sync_reset => "none")
4616 -- pragma translate_on
4617 PORT MAP (
4618         datain => \vga_driver_unit|column_counter_sig_3\,
4619         devclrn => ww_devclrn,
4620         devpor => ww_devpor,
4621         devoe => ww_devoe,
4622         oe => VCC,
4623         padio => ww_d_column_counter(3));
4624
4625 \d_column_counter_out_4_\ : stratix_io
4626 -- pragma translate_off
4627 GENERIC MAP (
4628         ddio_mode => "none",
4629         input_async_reset => "none",
4630         input_power_up => "low",
4631         input_register_mode => "none",
4632         input_sync_reset => "none",
4633         oe_async_reset => "none",
4634         oe_power_up => "low",
4635         oe_register_mode => "none",
4636         oe_sync_reset => "none",
4637         operation_mode => "output",
4638         output_async_reset => "none",
4639         output_power_up => "low",
4640         output_register_mode => "none",
4641         output_sync_reset => "none")
4642 -- pragma translate_on
4643 PORT MAP (
4644         datain => \vga_driver_unit|column_counter_sig_4\,
4645         devclrn => ww_devclrn,
4646         devpor => ww_devpor,
4647         devoe => ww_devoe,
4648         oe => VCC,
4649         padio => ww_d_column_counter(4));
4650
4651 \d_column_counter_out_5_\ : stratix_io
4652 -- pragma translate_off
4653 GENERIC MAP (
4654         ddio_mode => "none",
4655         input_async_reset => "none",
4656         input_power_up => "low",
4657         input_register_mode => "none",
4658         input_sync_reset => "none",
4659         oe_async_reset => "none",
4660         oe_power_up => "low",
4661         oe_register_mode => "none",
4662         oe_sync_reset => "none",
4663         operation_mode => "output",
4664         output_async_reset => "none",
4665         output_power_up => "low",
4666         output_register_mode => "none",
4667         output_sync_reset => "none")
4668 -- pragma translate_on
4669 PORT MAP (
4670         datain => \vga_driver_unit|column_counter_sig_5\,
4671         devclrn => ww_devclrn,
4672         devpor => ww_devpor,
4673         devoe => ww_devoe,
4674         oe => VCC,
4675         padio => ww_d_column_counter(5));
4676
4677 \d_column_counter_out_6_\ : stratix_io
4678 -- pragma translate_off
4679 GENERIC MAP (
4680         ddio_mode => "none",
4681         input_async_reset => "none",
4682         input_power_up => "low",
4683         input_register_mode => "none",
4684         input_sync_reset => "none",
4685         oe_async_reset => "none",
4686         oe_power_up => "low",
4687         oe_register_mode => "none",
4688         oe_sync_reset => "none",
4689         operation_mode => "output",
4690         output_async_reset => "none",
4691         output_power_up => "low",
4692         output_register_mode => "none",
4693         output_sync_reset => "none")
4694 -- pragma translate_on
4695 PORT MAP (
4696         datain => \vga_driver_unit|column_counter_sig_6\,
4697         devclrn => ww_devclrn,
4698         devpor => ww_devpor,
4699         devoe => ww_devoe,
4700         oe => VCC,
4701         padio => ww_d_column_counter(6));
4702
4703 \d_column_counter_out_7_\ : stratix_io
4704 -- pragma translate_off
4705 GENERIC MAP (
4706         ddio_mode => "none",
4707         input_async_reset => "none",
4708         input_power_up => "low",
4709         input_register_mode => "none",
4710         input_sync_reset => "none",
4711         oe_async_reset => "none",
4712         oe_power_up => "low",
4713         oe_register_mode => "none",
4714         oe_sync_reset => "none",
4715         operation_mode => "output",
4716         output_async_reset => "none",
4717         output_power_up => "low",
4718         output_register_mode => "none",
4719         output_sync_reset => "none")
4720 -- pragma translate_on
4721 PORT MAP (
4722         datain => \vga_driver_unit|column_counter_sig_7\,
4723         devclrn => ww_devclrn,
4724         devpor => ww_devpor,
4725         devoe => ww_devoe,
4726         oe => VCC,
4727         padio => ww_d_column_counter(7));
4728
4729 \d_column_counter_out_8_\ : stratix_io
4730 -- pragma translate_off
4731 GENERIC MAP (
4732         ddio_mode => "none",
4733         input_async_reset => "none",
4734         input_power_up => "low",
4735         input_register_mode => "none",
4736         input_sync_reset => "none",
4737         oe_async_reset => "none",
4738         oe_power_up => "low",
4739         oe_register_mode => "none",
4740         oe_sync_reset => "none",
4741         operation_mode => "output",
4742         output_async_reset => "none",
4743         output_power_up => "low",
4744         output_register_mode => "none",
4745         output_sync_reset => "none")
4746 -- pragma translate_on
4747 PORT MAP (
4748         datain => \vga_driver_unit|column_counter_sig_8\,
4749         devclrn => ww_devclrn,
4750         devpor => ww_devpor,
4751         devoe => ww_devoe,
4752         oe => VCC,
4753         padio => ww_d_column_counter(8));
4754
4755 \d_column_counter_out_9_\ : stratix_io
4756 -- pragma translate_off
4757 GENERIC MAP (
4758         ddio_mode => "none",
4759         input_async_reset => "none",
4760         input_power_up => "low",
4761         input_register_mode => "none",
4762         input_sync_reset => "none",
4763         oe_async_reset => "none",
4764         oe_power_up => "low",
4765         oe_register_mode => "none",
4766         oe_sync_reset => "none",
4767         operation_mode => "output",
4768         output_async_reset => "none",
4769         output_power_up => "low",
4770         output_register_mode => "none",
4771         output_sync_reset => "none")
4772 -- pragma translate_on
4773 PORT MAP (
4774         datain => \vga_driver_unit|column_counter_sig_9\,
4775         devclrn => ww_devclrn,
4776         devpor => ww_devpor,
4777         devoe => ww_devoe,
4778         oe => VCC,
4779         padio => ww_d_column_counter(9));
4780
4781 \d_line_counter_out_0_\ : stratix_io
4782 -- pragma translate_off
4783 GENERIC MAP (
4784         ddio_mode => "none",
4785         input_async_reset => "none",
4786         input_power_up => "low",
4787         input_register_mode => "none",
4788         input_sync_reset => "none",
4789         oe_async_reset => "none",
4790         oe_power_up => "low",
4791         oe_register_mode => "none",
4792         oe_sync_reset => "none",
4793         operation_mode => "output",
4794         output_async_reset => "none",
4795         output_power_up => "low",
4796         output_register_mode => "none",
4797         output_sync_reset => "none")
4798 -- pragma translate_on
4799 PORT MAP (
4800         datain => \vga_driver_unit|line_counter_sig_0\,
4801         devclrn => ww_devclrn,
4802         devpor => ww_devpor,
4803         devoe => ww_devoe,
4804         oe => VCC,
4805         padio => ww_d_line_counter(0));
4806
4807 \d_line_counter_out_1_\ : stratix_io
4808 -- pragma translate_off
4809 GENERIC MAP (
4810         ddio_mode => "none",
4811         input_async_reset => "none",
4812         input_power_up => "low",
4813         input_register_mode => "none",
4814         input_sync_reset => "none",
4815         oe_async_reset => "none",
4816         oe_power_up => "low",
4817         oe_register_mode => "none",
4818         oe_sync_reset => "none",
4819         operation_mode => "output",
4820         output_async_reset => "none",
4821         output_power_up => "low",
4822         output_register_mode => "none",
4823         output_sync_reset => "none")
4824 -- pragma translate_on
4825 PORT MAP (
4826         datain => \vga_driver_unit|line_counter_sig_1\,
4827         devclrn => ww_devclrn,
4828         devpor => ww_devpor,
4829         devoe => ww_devoe,
4830         oe => VCC,
4831         padio => ww_d_line_counter(1));
4832
4833 \d_line_counter_out_2_\ : stratix_io
4834 -- pragma translate_off
4835 GENERIC MAP (
4836         ddio_mode => "none",
4837         input_async_reset => "none",
4838         input_power_up => "low",
4839         input_register_mode => "none",
4840         input_sync_reset => "none",
4841         oe_async_reset => "none",
4842         oe_power_up => "low",
4843         oe_register_mode => "none",
4844         oe_sync_reset => "none",
4845         operation_mode => "output",
4846         output_async_reset => "none",
4847         output_power_up => "low",
4848         output_register_mode => "none",
4849         output_sync_reset => "none")
4850 -- pragma translate_on
4851 PORT MAP (
4852         datain => \vga_driver_unit|line_counter_sig_2\,
4853         devclrn => ww_devclrn,
4854         devpor => ww_devpor,
4855         devoe => ww_devoe,
4856         oe => VCC,
4857         padio => ww_d_line_counter(2));
4858
4859 \d_line_counter_out_3_\ : stratix_io
4860 -- pragma translate_off
4861 GENERIC MAP (
4862         ddio_mode => "none",
4863         input_async_reset => "none",
4864         input_power_up => "low",
4865         input_register_mode => "none",
4866         input_sync_reset => "none",
4867         oe_async_reset => "none",
4868         oe_power_up => "low",
4869         oe_register_mode => "none",
4870         oe_sync_reset => "none",
4871         operation_mode => "output",
4872         output_async_reset => "none",
4873         output_power_up => "low",
4874         output_register_mode => "none",
4875         output_sync_reset => "none")
4876 -- pragma translate_on
4877 PORT MAP (
4878         datain => \vga_driver_unit|line_counter_sig_3\,
4879         devclrn => ww_devclrn,
4880         devpor => ww_devpor,
4881         devoe => ww_devoe,
4882         oe => VCC,
4883         padio => ww_d_line_counter(3));
4884
4885 \d_line_counter_out_4_\ : stratix_io
4886 -- pragma translate_off
4887 GENERIC MAP (
4888         ddio_mode => "none",
4889         input_async_reset => "none",
4890         input_power_up => "low",
4891         input_register_mode => "none",
4892         input_sync_reset => "none",
4893         oe_async_reset => "none",
4894         oe_power_up => "low",
4895         oe_register_mode => "none",
4896         oe_sync_reset => "none",
4897         operation_mode => "output",
4898         output_async_reset => "none",
4899         output_power_up => "low",
4900         output_register_mode => "none",
4901         output_sync_reset => "none")
4902 -- pragma translate_on
4903 PORT MAP (
4904         datain => \vga_driver_unit|line_counter_sig_4\,
4905         devclrn => ww_devclrn,
4906         devpor => ww_devpor,
4907         devoe => ww_devoe,
4908         oe => VCC,
4909         padio => ww_d_line_counter(4));
4910
4911 \d_line_counter_out_5_\ : stratix_io
4912 -- pragma translate_off
4913 GENERIC MAP (
4914         ddio_mode => "none",
4915         input_async_reset => "none",
4916         input_power_up => "low",
4917         input_register_mode => "none",
4918         input_sync_reset => "none",
4919         oe_async_reset => "none",
4920         oe_power_up => "low",
4921         oe_register_mode => "none",
4922         oe_sync_reset => "none",
4923         operation_mode => "output",
4924         output_async_reset => "none",
4925         output_power_up => "low",
4926         output_register_mode => "none",
4927         output_sync_reset => "none")
4928 -- pragma translate_on
4929 PORT MAP (
4930         datain => \vga_driver_unit|line_counter_sig_5\,
4931         devclrn => ww_devclrn,
4932         devpor => ww_devpor,
4933         devoe => ww_devoe,
4934         oe => VCC,
4935         padio => ww_d_line_counter(5));
4936
4937 \d_line_counter_out_6_\ : stratix_io
4938 -- pragma translate_off
4939 GENERIC MAP (
4940         ddio_mode => "none",
4941         input_async_reset => "none",
4942         input_power_up => "low",
4943         input_register_mode => "none",
4944         input_sync_reset => "none",
4945         oe_async_reset => "none",
4946         oe_power_up => "low",
4947         oe_register_mode => "none",
4948         oe_sync_reset => "none",
4949         operation_mode => "output",
4950         output_async_reset => "none",
4951         output_power_up => "low",
4952         output_register_mode => "none",
4953         output_sync_reset => "none")
4954 -- pragma translate_on
4955 PORT MAP (
4956         datain => \vga_driver_unit|line_counter_sig_6\,
4957         devclrn => ww_devclrn,
4958         devpor => ww_devpor,
4959         devoe => ww_devoe,
4960         oe => VCC,
4961         padio => ww_d_line_counter(6));
4962
4963 \d_line_counter_out_7_\ : stratix_io
4964 -- pragma translate_off
4965 GENERIC MAP (
4966         ddio_mode => "none",
4967         input_async_reset => "none",
4968         input_power_up => "low",
4969         input_register_mode => "none",
4970         input_sync_reset => "none",
4971         oe_async_reset => "none",
4972         oe_power_up => "low",
4973         oe_register_mode => "none",
4974         oe_sync_reset => "none",
4975         operation_mode => "output",
4976         output_async_reset => "none",
4977         output_power_up => "low",
4978         output_register_mode => "none",
4979         output_sync_reset => "none")
4980 -- pragma translate_on
4981 PORT MAP (
4982         datain => \vga_driver_unit|line_counter_sig_7\,
4983         devclrn => ww_devclrn,
4984         devpor => ww_devpor,
4985         devoe => ww_devoe,
4986         oe => VCC,
4987         padio => ww_d_line_counter(7));
4988
4989 \d_line_counter_out_8_\ : stratix_io
4990 -- pragma translate_off
4991 GENERIC MAP (
4992         ddio_mode => "none",
4993         input_async_reset => "none",
4994         input_power_up => "low",
4995         input_register_mode => "none",
4996         input_sync_reset => "none",
4997         oe_async_reset => "none",
4998         oe_power_up => "low",
4999         oe_register_mode => "none",
5000         oe_sync_reset => "none",
5001         operation_mode => "output",
5002         output_async_reset => "none",
5003         output_power_up => "low",
5004         output_register_mode => "none",
5005         output_sync_reset => "none")
5006 -- pragma translate_on
5007 PORT MAP (
5008         datain => \vga_driver_unit|line_counter_sig_8\,
5009         devclrn => ww_devclrn,
5010         devpor => ww_devpor,
5011         devoe => ww_devoe,
5012         oe => VCC,
5013         padio => ww_d_line_counter(8));
5014
5015 d_set_column_counter_out : stratix_io
5016 -- pragma translate_off
5017 GENERIC MAP (
5018         ddio_mode => "none",
5019         input_async_reset => "none",
5020         input_power_up => "low",
5021         input_register_mode => "none",
5022         input_sync_reset => "none",
5023         oe_async_reset => "none",
5024         oe_power_up => "low",
5025         oe_register_mode => "none",
5026         oe_sync_reset => "none",
5027         operation_mode => "output",
5028         output_async_reset => "none",
5029         output_power_up => "low",
5030         output_register_mode => "none",
5031         output_sync_reset => "none")
5032 -- pragma translate_on
5033 PORT MAP (
5034         datain => \vga_driver_unit|hsync_state_1\,
5035         devclrn => ww_devclrn,
5036         devpor => ww_devpor,
5037         devoe => ww_devoe,
5038         oe => VCC,
5039         padio => ww_d_set_column_counter);
5040
5041 d_set_line_counter_out : stratix_io
5042 -- pragma translate_off
5043 GENERIC MAP (
5044         ddio_mode => "none",
5045         input_async_reset => "none",
5046         input_power_up => "low",
5047         input_register_mode => "none",
5048         input_sync_reset => "none",
5049         oe_async_reset => "none",
5050         oe_power_up => "low",
5051         oe_register_mode => "none",
5052         oe_sync_reset => "none",
5053         operation_mode => "output",
5054         output_async_reset => "none",
5055         output_power_up => "low",
5056         output_register_mode => "none",
5057         output_sync_reset => "none")
5058 -- pragma translate_on
5059 PORT MAP (
5060         datain => \vga_driver_unit|vsync_state_1\,
5061         devclrn => ww_devclrn,
5062         devpor => ww_devpor,
5063         devoe => ww_devoe,
5064         oe => VCC,
5065         padio => ww_d_set_line_counter);
5066
5067 \d_hsync_counter_out_0_\ : stratix_io
5068 -- pragma translate_off
5069 GENERIC MAP (
5070         ddio_mode => "none",
5071         input_async_reset => "none",
5072         input_power_up => "low",
5073         input_register_mode => "none",
5074         input_sync_reset => "none",
5075         oe_async_reset => "none",
5076         oe_power_up => "low",
5077         oe_register_mode => "none",
5078         oe_sync_reset => "none",
5079         operation_mode => "output",
5080         output_async_reset => "none",
5081         output_power_up => "low",
5082         output_register_mode => "none",
5083         output_sync_reset => "none")
5084 -- pragma translate_on
5085 PORT MAP (
5086         datain => \vga_driver_unit|hsync_counter_0\,
5087         devclrn => ww_devclrn,
5088         devpor => ww_devpor,
5089         devoe => ww_devoe,
5090         oe => VCC,
5091         padio => ww_d_hsync_counter(0));
5092
5093 \d_hsync_counter_out_1_\ : stratix_io
5094 -- pragma translate_off
5095 GENERIC MAP (
5096         ddio_mode => "none",
5097         input_async_reset => "none",
5098         input_power_up => "low",
5099         input_register_mode => "none",
5100         input_sync_reset => "none",
5101         oe_async_reset => "none",
5102         oe_power_up => "low",
5103         oe_register_mode => "none",
5104         oe_sync_reset => "none",
5105         operation_mode => "output",
5106         output_async_reset => "none",
5107         output_power_up => "low",
5108         output_register_mode => "none",
5109         output_sync_reset => "none")
5110 -- pragma translate_on
5111 PORT MAP (
5112         datain => \vga_driver_unit|hsync_counter_1\,
5113         devclrn => ww_devclrn,
5114         devpor => ww_devpor,
5115         devoe => ww_devoe,
5116         oe => VCC,
5117         padio => ww_d_hsync_counter(1));
5118
5119 \d_hsync_counter_out_2_\ : stratix_io
5120 -- pragma translate_off
5121 GENERIC MAP (
5122         ddio_mode => "none",
5123         input_async_reset => "none",
5124         input_power_up => "low",
5125         input_register_mode => "none",
5126         input_sync_reset => "none",
5127         oe_async_reset => "none",
5128         oe_power_up => "low",
5129         oe_register_mode => "none",
5130         oe_sync_reset => "none",
5131         operation_mode => "output",
5132         output_async_reset => "none",
5133         output_power_up => "low",
5134         output_register_mode => "none",
5135         output_sync_reset => "none")
5136 -- pragma translate_on
5137 PORT MAP (
5138         datain => \vga_driver_unit|hsync_counter_2\,
5139         devclrn => ww_devclrn,
5140         devpor => ww_devpor,
5141         devoe => ww_devoe,
5142         oe => VCC,
5143         padio => ww_d_hsync_counter(2));
5144
5145 \d_hsync_counter_out_3_\ : stratix_io
5146 -- pragma translate_off
5147 GENERIC MAP (
5148         ddio_mode => "none",
5149         input_async_reset => "none",
5150         input_power_up => "low",
5151         input_register_mode => "none",
5152         input_sync_reset => "none",
5153         oe_async_reset => "none",
5154         oe_power_up => "low",
5155         oe_register_mode => "none",
5156         oe_sync_reset => "none",
5157         operation_mode => "output",
5158         output_async_reset => "none",
5159         output_power_up => "low",
5160         output_register_mode => "none",
5161         output_sync_reset => "none")
5162 -- pragma translate_on
5163 PORT MAP (
5164         datain => \vga_driver_unit|hsync_counter_3\,
5165         devclrn => ww_devclrn,
5166         devpor => ww_devpor,
5167         devoe => ww_devoe,
5168         oe => VCC,
5169         padio => ww_d_hsync_counter(3));
5170
5171 \d_hsync_counter_out_4_\ : stratix_io
5172 -- pragma translate_off
5173 GENERIC MAP (
5174         ddio_mode => "none",
5175         input_async_reset => "none",
5176         input_power_up => "low",
5177         input_register_mode => "none",
5178         input_sync_reset => "none",
5179         oe_async_reset => "none",
5180         oe_power_up => "low",
5181         oe_register_mode => "none",
5182         oe_sync_reset => "none",
5183         operation_mode => "output",
5184         output_async_reset => "none",
5185         output_power_up => "low",
5186         output_register_mode => "none",
5187         output_sync_reset => "none")
5188 -- pragma translate_on
5189 PORT MAP (
5190         datain => \vga_driver_unit|hsync_counter_4\,
5191         devclrn => ww_devclrn,
5192         devpor => ww_devpor,
5193         devoe => ww_devoe,
5194         oe => VCC,
5195         padio => ww_d_hsync_counter(4));
5196
5197 \d_hsync_counter_out_5_\ : stratix_io
5198 -- pragma translate_off
5199 GENERIC MAP (
5200         ddio_mode => "none",
5201         input_async_reset => "none",
5202         input_power_up => "low",
5203         input_register_mode => "none",
5204         input_sync_reset => "none",
5205         oe_async_reset => "none",
5206         oe_power_up => "low",
5207         oe_register_mode => "none",
5208         oe_sync_reset => "none",
5209         operation_mode => "output",
5210         output_async_reset => "none",
5211         output_power_up => "low",
5212         output_register_mode => "none",
5213         output_sync_reset => "none")
5214 -- pragma translate_on
5215 PORT MAP (
5216         datain => \vga_driver_unit|hsync_counter_5\,
5217         devclrn => ww_devclrn,
5218         devpor => ww_devpor,
5219         devoe => ww_devoe,
5220         oe => VCC,
5221         padio => ww_d_hsync_counter(5));
5222
5223 \d_hsync_counter_out_6_\ : stratix_io
5224 -- pragma translate_off
5225 GENERIC MAP (
5226         ddio_mode => "none",
5227         input_async_reset => "none",
5228         input_power_up => "low",
5229         input_register_mode => "none",
5230         input_sync_reset => "none",
5231         oe_async_reset => "none",
5232         oe_power_up => "low",
5233         oe_register_mode => "none",
5234         oe_sync_reset => "none",
5235         operation_mode => "output",
5236         output_async_reset => "none",
5237         output_power_up => "low",
5238         output_register_mode => "none",
5239         output_sync_reset => "none")
5240 -- pragma translate_on
5241 PORT MAP (
5242         datain => \vga_driver_unit|hsync_counter_6\,
5243         devclrn => ww_devclrn,
5244         devpor => ww_devpor,
5245         devoe => ww_devoe,
5246         oe => VCC,
5247         padio => ww_d_hsync_counter(6));
5248
5249 \d_hsync_counter_out_7_\ : stratix_io
5250 -- pragma translate_off
5251 GENERIC MAP (
5252         ddio_mode => "none",
5253         input_async_reset => "none",
5254         input_power_up => "low",
5255         input_register_mode => "none",
5256         input_sync_reset => "none",
5257         oe_async_reset => "none",
5258         oe_power_up => "low",
5259         oe_register_mode => "none",
5260         oe_sync_reset => "none",
5261         operation_mode => "output",
5262         output_async_reset => "none",
5263         output_power_up => "low",
5264         output_register_mode => "none",
5265         output_sync_reset => "none")
5266 -- pragma translate_on
5267 PORT MAP (
5268         datain => \vga_driver_unit|hsync_counter_7\,
5269         devclrn => ww_devclrn,
5270         devpor => ww_devpor,
5271         devoe => ww_devoe,
5272         oe => VCC,
5273         padio => ww_d_hsync_counter(7));
5274
5275 \d_hsync_counter_out_8_\ : stratix_io
5276 -- pragma translate_off
5277 GENERIC MAP (
5278         ddio_mode => "none",
5279         input_async_reset => "none",
5280         input_power_up => "low",
5281         input_register_mode => "none",
5282         input_sync_reset => "none",
5283         oe_async_reset => "none",
5284         oe_power_up => "low",
5285         oe_register_mode => "none",
5286         oe_sync_reset => "none",
5287         operation_mode => "output",
5288         output_async_reset => "none",
5289         output_power_up => "low",
5290         output_register_mode => "none",
5291         output_sync_reset => "none")
5292 -- pragma translate_on
5293 PORT MAP (
5294         datain => \vga_driver_unit|hsync_counter_8\,
5295         devclrn => ww_devclrn,
5296         devpor => ww_devpor,
5297         devoe => ww_devoe,
5298         oe => VCC,
5299         padio => ww_d_hsync_counter(8));
5300
5301 \d_hsync_counter_out_9_\ : stratix_io
5302 -- pragma translate_off
5303 GENERIC MAP (
5304         ddio_mode => "none",
5305         input_async_reset => "none",
5306         input_power_up => "low",
5307         input_register_mode => "none",
5308         input_sync_reset => "none",
5309         oe_async_reset => "none",
5310         oe_power_up => "low",
5311         oe_register_mode => "none",
5312         oe_sync_reset => "none",
5313         operation_mode => "output",
5314         output_async_reset => "none",
5315         output_power_up => "low",
5316         output_register_mode => "none",
5317         output_sync_reset => "none")
5318 -- pragma translate_on
5319 PORT MAP (
5320         datain => \vga_driver_unit|hsync_counter_9\,
5321         devclrn => ww_devclrn,
5322         devpor => ww_devpor,
5323         devoe => ww_devoe,
5324         oe => VCC,
5325         padio => ww_d_hsync_counter(9));
5326
5327 \d_vsync_counter_out_0_\ : stratix_io
5328 -- pragma translate_off
5329 GENERIC MAP (
5330         ddio_mode => "none",
5331         input_async_reset => "none",
5332         input_power_up => "low",
5333         input_register_mode => "none",
5334         input_sync_reset => "none",
5335         oe_async_reset => "none",
5336         oe_power_up => "low",
5337         oe_register_mode => "none",
5338         oe_sync_reset => "none",
5339         operation_mode => "output",
5340         output_async_reset => "none",
5341         output_power_up => "low",
5342         output_register_mode => "none",
5343         output_sync_reset => "none")
5344 -- pragma translate_on
5345 PORT MAP (
5346         datain => \vga_driver_unit|vsync_counter_0\,
5347         devclrn => ww_devclrn,
5348         devpor => ww_devpor,
5349         devoe => ww_devoe,
5350         oe => VCC,
5351         padio => ww_d_vsync_counter(0));
5352
5353 \d_vsync_counter_out_1_\ : stratix_io
5354 -- pragma translate_off
5355 GENERIC MAP (
5356         ddio_mode => "none",
5357         input_async_reset => "none",
5358         input_power_up => "low",
5359         input_register_mode => "none",
5360         input_sync_reset => "none",
5361         oe_async_reset => "none",
5362         oe_power_up => "low",
5363         oe_register_mode => "none",
5364         oe_sync_reset => "none",
5365         operation_mode => "output",
5366         output_async_reset => "none",
5367         output_power_up => "low",
5368         output_register_mode => "none",
5369         output_sync_reset => "none")
5370 -- pragma translate_on
5371 PORT MAP (
5372         datain => \vga_driver_unit|vsync_counter_1\,
5373         devclrn => ww_devclrn,
5374         devpor => ww_devpor,
5375         devoe => ww_devoe,
5376         oe => VCC,
5377         padio => ww_d_vsync_counter(1));
5378
5379 \d_vsync_counter_out_2_\ : stratix_io
5380 -- pragma translate_off
5381 GENERIC MAP (
5382         ddio_mode => "none",
5383         input_async_reset => "none",
5384         input_power_up => "low",
5385         input_register_mode => "none",
5386         input_sync_reset => "none",
5387         oe_async_reset => "none",
5388         oe_power_up => "low",
5389         oe_register_mode => "none",
5390         oe_sync_reset => "none",
5391         operation_mode => "output",
5392         output_async_reset => "none",
5393         output_power_up => "low",
5394         output_register_mode => "none",
5395         output_sync_reset => "none")
5396 -- pragma translate_on
5397 PORT MAP (
5398         datain => \vga_driver_unit|vsync_counter_2\,
5399         devclrn => ww_devclrn,
5400         devpor => ww_devpor,
5401         devoe => ww_devoe,
5402         oe => VCC,
5403         padio => ww_d_vsync_counter(2));
5404
5405 \d_vsync_counter_out_3_\ : stratix_io
5406 -- pragma translate_off
5407 GENERIC MAP (
5408         ddio_mode => "none",
5409         input_async_reset => "none",
5410         input_power_up => "low",
5411         input_register_mode => "none",
5412         input_sync_reset => "none",
5413         oe_async_reset => "none",
5414         oe_power_up => "low",
5415         oe_register_mode => "none",
5416         oe_sync_reset => "none",
5417         operation_mode => "output",
5418         output_async_reset => "none",
5419         output_power_up => "low",
5420         output_register_mode => "none",
5421         output_sync_reset => "none")
5422 -- pragma translate_on
5423 PORT MAP (
5424         datain => \vga_driver_unit|vsync_counter_3\,
5425         devclrn => ww_devclrn,
5426         devpor => ww_devpor,
5427         devoe => ww_devoe,
5428         oe => VCC,
5429         padio => ww_d_vsync_counter(3));
5430
5431 \d_vsync_counter_out_4_\ : stratix_io
5432 -- pragma translate_off
5433 GENERIC MAP (
5434         ddio_mode => "none",
5435         input_async_reset => "none",
5436         input_power_up => "low",
5437         input_register_mode => "none",
5438         input_sync_reset => "none",
5439         oe_async_reset => "none",
5440         oe_power_up => "low",
5441         oe_register_mode => "none",
5442         oe_sync_reset => "none",
5443         operation_mode => "output",
5444         output_async_reset => "none",
5445         output_power_up => "low",
5446         output_register_mode => "none",
5447         output_sync_reset => "none")
5448 -- pragma translate_on
5449 PORT MAP (
5450         datain => \vga_driver_unit|vsync_counter_4\,
5451         devclrn => ww_devclrn,
5452         devpor => ww_devpor,
5453         devoe => ww_devoe,
5454         oe => VCC,
5455         padio => ww_d_vsync_counter(4));
5456
5457 \d_vsync_counter_out_5_\ : stratix_io
5458 -- pragma translate_off
5459 GENERIC MAP (
5460         ddio_mode => "none",
5461         input_async_reset => "none",
5462         input_power_up => "low",
5463         input_register_mode => "none",
5464         input_sync_reset => "none",
5465         oe_async_reset => "none",
5466         oe_power_up => "low",
5467         oe_register_mode => "none",
5468         oe_sync_reset => "none",
5469         operation_mode => "output",
5470         output_async_reset => "none",
5471         output_power_up => "low",
5472         output_register_mode => "none",
5473         output_sync_reset => "none")
5474 -- pragma translate_on
5475 PORT MAP (
5476         datain => \vga_driver_unit|vsync_counter_5\,
5477         devclrn => ww_devclrn,
5478         devpor => ww_devpor,
5479         devoe => ww_devoe,
5480         oe => VCC,
5481         padio => ww_d_vsync_counter(5));
5482
5483 \d_vsync_counter_out_6_\ : stratix_io
5484 -- pragma translate_off
5485 GENERIC MAP (
5486         ddio_mode => "none",
5487         input_async_reset => "none",
5488         input_power_up => "low",
5489         input_register_mode => "none",
5490         input_sync_reset => "none",
5491         oe_async_reset => "none",
5492         oe_power_up => "low",
5493         oe_register_mode => "none",
5494         oe_sync_reset => "none",
5495         operation_mode => "output",
5496         output_async_reset => "none",
5497         output_power_up => "low",
5498         output_register_mode => "none",
5499         output_sync_reset => "none")
5500 -- pragma translate_on
5501 PORT MAP (
5502         datain => \vga_driver_unit|vsync_counter_6\,
5503         devclrn => ww_devclrn,
5504         devpor => ww_devpor,
5505         devoe => ww_devoe,
5506         oe => VCC,
5507         padio => ww_d_vsync_counter(6));
5508
5509 \d_vsync_counter_out_7_\ : stratix_io
5510 -- pragma translate_off
5511 GENERIC MAP (
5512         ddio_mode => "none",
5513         input_async_reset => "none",
5514         input_power_up => "low",
5515         input_register_mode => "none",
5516         input_sync_reset => "none",
5517         oe_async_reset => "none",
5518         oe_power_up => "low",
5519         oe_register_mode => "none",
5520         oe_sync_reset => "none",
5521         operation_mode => "output",
5522         output_async_reset => "none",
5523         output_power_up => "low",
5524         output_register_mode => "none",
5525         output_sync_reset => "none")
5526 -- pragma translate_on
5527 PORT MAP (
5528         datain => \vga_driver_unit|vsync_counter_7\,
5529         devclrn => ww_devclrn,
5530         devpor => ww_devpor,
5531         devoe => ww_devoe,
5532         oe => VCC,
5533         padio => ww_d_vsync_counter(7));
5534
5535 \d_vsync_counter_out_8_\ : stratix_io
5536 -- pragma translate_off
5537 GENERIC MAP (
5538         ddio_mode => "none",
5539         input_async_reset => "none",
5540         input_power_up => "low",
5541         input_register_mode => "none",
5542         input_sync_reset => "none",
5543         oe_async_reset => "none",
5544         oe_power_up => "low",
5545         oe_register_mode => "none",
5546         oe_sync_reset => "none",
5547         operation_mode => "output",
5548         output_async_reset => "none",
5549         output_power_up => "low",
5550         output_register_mode => "none",
5551         output_sync_reset => "none")
5552 -- pragma translate_on
5553 PORT MAP (
5554         datain => \vga_driver_unit|vsync_counter_8\,
5555         devclrn => ww_devclrn,
5556         devpor => ww_devpor,
5557         devoe => ww_devoe,
5558         oe => VCC,
5559         padio => ww_d_vsync_counter(8));
5560
5561 \d_vsync_counter_out_9_\ : stratix_io
5562 -- pragma translate_off
5563 GENERIC MAP (
5564         ddio_mode => "none",
5565         input_async_reset => "none",
5566         input_power_up => "low",
5567         input_register_mode => "none",
5568         input_sync_reset => "none",
5569         oe_async_reset => "none",
5570         oe_power_up => "low",
5571         oe_register_mode => "none",
5572         oe_sync_reset => "none",
5573         operation_mode => "output",
5574         output_async_reset => "none",
5575         output_power_up => "low",
5576         output_register_mode => "none",
5577         output_sync_reset => "none")
5578 -- pragma translate_on
5579 PORT MAP (
5580         datain => \vga_driver_unit|vsync_counter_9\,
5581         devclrn => ww_devclrn,
5582         devpor => ww_devpor,
5583         devoe => ww_devoe,
5584         oe => VCC,
5585         padio => ww_d_vsync_counter(9));
5586
5587 d_set_hsync_counter_out : stratix_io
5588 -- pragma translate_off
5589 GENERIC MAP (
5590         ddio_mode => "none",
5591         input_async_reset => "none",
5592         input_power_up => "low",
5593         input_register_mode => "none",
5594         input_sync_reset => "none",
5595         oe_async_reset => "none",
5596         oe_power_up => "low",
5597         oe_register_mode => "none",
5598         oe_sync_reset => "none",
5599         operation_mode => "output",
5600         output_async_reset => "none",
5601         output_power_up => "low",
5602         output_register_mode => "none",
5603         output_sync_reset => "none")
5604 -- pragma translate_on
5605 PORT MAP (
5606         datain => \vga_driver_unit|d_set_hsync_counter\,
5607         devclrn => ww_devclrn,
5608         devpor => ww_devpor,
5609         devoe => ww_devoe,
5610         oe => VCC,
5611         padio => ww_d_set_hsync_counter);
5612
5613 d_set_vsync_counter_out : stratix_io
5614 -- pragma translate_off
5615 GENERIC MAP (
5616         ddio_mode => "none",
5617         input_async_reset => "none",
5618         input_power_up => "low",
5619         input_register_mode => "none",
5620         input_sync_reset => "none",
5621         oe_async_reset => "none",
5622         oe_power_up => "low",
5623         oe_register_mode => "none",
5624         oe_sync_reset => "none",
5625         operation_mode => "output",
5626         output_async_reset => "none",
5627         output_power_up => "low",
5628         output_register_mode => "none",
5629         output_sync_reset => "none")
5630 -- pragma translate_on
5631 PORT MAP (
5632         datain => \vga_driver_unit|d_set_vsync_counter\,
5633         devclrn => ww_devclrn,
5634         devpor => ww_devpor,
5635         devoe => ww_devoe,
5636         oe => VCC,
5637         padio => ww_d_set_vsync_counter);
5638
5639 d_h_enable_out : stratix_io
5640 -- pragma translate_off
5641 GENERIC MAP (
5642         ddio_mode => "none",
5643         input_async_reset => "none",
5644         input_power_up => "low",
5645         input_register_mode => "none",
5646         input_sync_reset => "none",
5647         oe_async_reset => "none",
5648         oe_power_up => "low",
5649         oe_register_mode => "none",
5650         oe_sync_reset => "none",
5651         operation_mode => "output",
5652         output_async_reset => "none",
5653         output_power_up => "low",
5654         output_register_mode => "none",
5655         output_sync_reset => "none")
5656 -- pragma translate_on
5657 PORT MAP (
5658         datain => \vga_driver_unit|h_enable_sig\,
5659         devclrn => ww_devclrn,
5660         devpor => ww_devpor,
5661         devoe => ww_devoe,
5662         oe => VCC,
5663         padio => ww_d_h_enable);
5664
5665 d_v_enable_out : stratix_io
5666 -- pragma translate_off
5667 GENERIC MAP (
5668         ddio_mode => "none",
5669         input_async_reset => "none",
5670         input_power_up => "low",
5671         input_register_mode => "none",
5672         input_sync_reset => "none",
5673         oe_async_reset => "none",
5674         oe_power_up => "low",
5675         oe_register_mode => "none",
5676         oe_sync_reset => "none",
5677         operation_mode => "output",
5678         output_async_reset => "none",
5679         output_power_up => "low",
5680         output_register_mode => "none",
5681         output_sync_reset => "none")
5682 -- pragma translate_on
5683 PORT MAP (
5684         datain => \vga_driver_unit|v_enable_sig\,
5685         devclrn => ww_devclrn,
5686         devpor => ww_devpor,
5687         devoe => ww_devoe,
5688         oe => VCC,
5689         padio => ww_d_v_enable);
5690
5691 d_r_out : stratix_io
5692 -- pragma translate_off
5693 GENERIC MAP (
5694         ddio_mode => "none",
5695         input_async_reset => "none",
5696         input_power_up => "low",
5697         input_register_mode => "none",
5698         input_sync_reset => "none",
5699         oe_async_reset => "none",
5700         oe_power_up => "low",
5701         oe_register_mode => "none",
5702         oe_sync_reset => "none",
5703         operation_mode => "output",
5704         output_async_reset => "none",
5705         output_power_up => "low",
5706         output_register_mode => "none",
5707         output_sync_reset => "none")
5708 -- pragma translate_on
5709 PORT MAP (
5710         datain => \vga_control_unit|r\,
5711         devclrn => ww_devclrn,
5712         devpor => ww_devpor,
5713         devoe => ww_devoe,
5714         oe => VCC,
5715         padio => ww_d_r);
5716
5717 d_g_out : stratix_io
5718 -- pragma translate_off
5719 GENERIC MAP (
5720         ddio_mode => "none",
5721         input_async_reset => "none",
5722         input_power_up => "low",
5723         input_register_mode => "none",
5724         input_sync_reset => "none",
5725         oe_async_reset => "none",
5726         oe_power_up => "low",
5727         oe_register_mode => "none",
5728         oe_sync_reset => "none",
5729         operation_mode => "output",
5730         output_async_reset => "none",
5731         output_power_up => "low",
5732         output_register_mode => "none",
5733         output_sync_reset => "none")
5734 -- pragma translate_on
5735 PORT MAP (
5736         datain => \vga_control_unit|g\,
5737         devclrn => ww_devclrn,
5738         devpor => ww_devpor,
5739         devoe => ww_devoe,
5740         oe => VCC,
5741         padio => ww_d_g);
5742
5743 d_b_out : stratix_io
5744 -- pragma translate_off
5745 GENERIC MAP (
5746         ddio_mode => "none",
5747         input_async_reset => "none",
5748         input_power_up => "low",
5749         input_register_mode => "none",
5750         input_sync_reset => "none",
5751         oe_async_reset => "none",
5752         oe_power_up => "low",
5753         oe_register_mode => "none",
5754         oe_sync_reset => "none",
5755         operation_mode => "output",
5756         output_async_reset => "none",
5757         output_power_up => "low",
5758         output_register_mode => "none",
5759         output_sync_reset => "none")
5760 -- pragma translate_on
5761 PORT MAP (
5762         datain => \vga_control_unit|b\,
5763         devclrn => ww_devclrn,
5764         devpor => ww_devpor,
5765         devoe => ww_devoe,
5766         oe => VCC,
5767         padio => ww_d_b);
5768
5769 \d_hsync_state_out_6_\ : stratix_io
5770 -- pragma translate_off
5771 GENERIC MAP (
5772         ddio_mode => "none",
5773         input_async_reset => "none",
5774         input_power_up => "low",
5775         input_register_mode => "none",
5776         input_sync_reset => "none",
5777         oe_async_reset => "none",
5778         oe_power_up => "low",
5779         oe_register_mode => "none",
5780         oe_sync_reset => "none",
5781         operation_mode => "output",
5782         output_async_reset => "none",
5783         output_power_up => "low",
5784         output_register_mode => "none",
5785         output_sync_reset => "none")
5786 -- pragma translate_on
5787 PORT MAP (
5788         datain => \vga_driver_unit|hsync_state_6\,
5789         devclrn => ww_devclrn,
5790         devpor => ww_devpor,
5791         devoe => ww_devoe,
5792         oe => VCC,
5793         padio => ww_d_hsync_state(6));
5794
5795 \d_hsync_state_out_5_\ : stratix_io
5796 -- pragma translate_off
5797 GENERIC MAP (
5798         ddio_mode => "none",
5799         input_async_reset => "none",
5800         input_power_up => "low",
5801         input_register_mode => "none",
5802         input_sync_reset => "none",
5803         oe_async_reset => "none",
5804         oe_power_up => "low",
5805         oe_register_mode => "none",
5806         oe_sync_reset => "none",
5807         operation_mode => "output",
5808         output_async_reset => "none",
5809         output_power_up => "low",
5810         output_register_mode => "none",
5811         output_sync_reset => "none")
5812 -- pragma translate_on
5813 PORT MAP (
5814         datain => \vga_driver_unit|hsync_state_5\,
5815         devclrn => ww_devclrn,
5816         devpor => ww_devpor,
5817         devoe => ww_devoe,
5818         oe => VCC,
5819         padio => ww_d_hsync_state(5));
5820
5821 \d_hsync_state_out_4_\ : stratix_io
5822 -- pragma translate_off
5823 GENERIC MAP (
5824         ddio_mode => "none",
5825         input_async_reset => "none",
5826         input_power_up => "low",
5827         input_register_mode => "none",
5828         input_sync_reset => "none",
5829         oe_async_reset => "none",
5830         oe_power_up => "low",
5831         oe_register_mode => "none",
5832         oe_sync_reset => "none",
5833         operation_mode => "output",
5834         output_async_reset => "none",
5835         output_power_up => "low",
5836         output_register_mode => "none",
5837         output_sync_reset => "none")
5838 -- pragma translate_on
5839 PORT MAP (
5840         datain => \vga_driver_unit|hsync_state_4\,
5841         devclrn => ww_devclrn,
5842         devpor => ww_devpor,
5843         devoe => ww_devoe,
5844         oe => VCC,
5845         padio => ww_d_hsync_state(4));
5846
5847 \d_hsync_state_out_3_\ : stratix_io
5848 -- pragma translate_off
5849 GENERIC MAP (
5850         ddio_mode => "none",
5851         input_async_reset => "none",
5852         input_power_up => "low",
5853         input_register_mode => "none",
5854         input_sync_reset => "none",
5855         oe_async_reset => "none",
5856         oe_power_up => "low",
5857         oe_register_mode => "none",
5858         oe_sync_reset => "none",
5859         operation_mode => "output",
5860         output_async_reset => "none",
5861         output_power_up => "low",
5862         output_register_mode => "none",
5863         output_sync_reset => "none")
5864 -- pragma translate_on
5865 PORT MAP (
5866         datain => \vga_driver_unit|hsync_state_3\,
5867         devclrn => ww_devclrn,
5868         devpor => ww_devpor,
5869         devoe => ww_devoe,
5870         oe => VCC,
5871         padio => ww_d_hsync_state(3));
5872
5873 \d_hsync_state_out_2_\ : stratix_io
5874 -- pragma translate_off
5875 GENERIC MAP (
5876         ddio_mode => "none",
5877         input_async_reset => "none",
5878         input_power_up => "low",
5879         input_register_mode => "none",
5880         input_sync_reset => "none",
5881         oe_async_reset => "none",
5882         oe_power_up => "low",
5883         oe_register_mode => "none",
5884         oe_sync_reset => "none",
5885         operation_mode => "output",
5886         output_async_reset => "none",
5887         output_power_up => "low",
5888         output_register_mode => "none",
5889         output_sync_reset => "none")
5890 -- pragma translate_on
5891 PORT MAP (
5892         datain => \vga_driver_unit|hsync_state_2\,
5893         devclrn => ww_devclrn,
5894         devpor => ww_devpor,
5895         devoe => ww_devoe,
5896         oe => VCC,
5897         padio => ww_d_hsync_state(2));
5898
5899 \d_hsync_state_out_1_\ : stratix_io
5900 -- pragma translate_off
5901 GENERIC MAP (
5902         ddio_mode => "none",
5903         input_async_reset => "none",
5904         input_power_up => "low",
5905         input_register_mode => "none",
5906         input_sync_reset => "none",
5907         oe_async_reset => "none",
5908         oe_power_up => "low",
5909         oe_register_mode => "none",
5910         oe_sync_reset => "none",
5911         operation_mode => "output",
5912         output_async_reset => "none",
5913         output_power_up => "low",
5914         output_register_mode => "none",
5915         output_sync_reset => "none")
5916 -- pragma translate_on
5917 PORT MAP (
5918         datain => \vga_driver_unit|hsync_state_1\,
5919         devclrn => ww_devclrn,
5920         devpor => ww_devpor,
5921         devoe => ww_devoe,
5922         oe => VCC,
5923         padio => ww_d_hsync_state(1));
5924
5925 \d_hsync_state_out_0_\ : stratix_io
5926 -- pragma translate_off
5927 GENERIC MAP (
5928         ddio_mode => "none",
5929         input_async_reset => "none",
5930         input_power_up => "low",
5931         input_register_mode => "none",
5932         input_sync_reset => "none",
5933         oe_async_reset => "none",
5934         oe_power_up => "low",
5935         oe_register_mode => "none",
5936         oe_sync_reset => "none",
5937         operation_mode => "output",
5938         output_async_reset => "none",
5939         output_power_up => "low",
5940         output_register_mode => "none",
5941         output_sync_reset => "none")
5942 -- pragma translate_on
5943 PORT MAP (
5944         datain => \vga_driver_unit|hsync_state_0\,
5945         devclrn => ww_devclrn,
5946         devpor => ww_devpor,
5947         devoe => ww_devoe,
5948         oe => VCC,
5949         padio => ww_d_hsync_state(0));
5950
5951 \d_vsync_state_out_6_\ : stratix_io
5952 -- pragma translate_off
5953 GENERIC MAP (
5954         ddio_mode => "none",
5955         input_async_reset => "none",
5956         input_power_up => "low",
5957         input_register_mode => "none",
5958         input_sync_reset => "none",
5959         oe_async_reset => "none",
5960         oe_power_up => "low",
5961         oe_register_mode => "none",
5962         oe_sync_reset => "none",
5963         operation_mode => "output",
5964         output_async_reset => "none",
5965         output_power_up => "low",
5966         output_register_mode => "none",
5967         output_sync_reset => "none")
5968 -- pragma translate_on
5969 PORT MAP (
5970         datain => \vga_driver_unit|vsync_state_6\,
5971         devclrn => ww_devclrn,
5972         devpor => ww_devpor,
5973         devoe => ww_devoe,
5974         oe => VCC,
5975         padio => ww_d_vsync_state(6));
5976
5977 \d_vsync_state_out_5_\ : stratix_io
5978 -- pragma translate_off
5979 GENERIC MAP (
5980         ddio_mode => "none",
5981         input_async_reset => "none",
5982         input_power_up => "low",
5983         input_register_mode => "none",
5984         input_sync_reset => "none",
5985         oe_async_reset => "none",
5986         oe_power_up => "low",
5987         oe_register_mode => "none",
5988         oe_sync_reset => "none",
5989         operation_mode => "output",
5990         output_async_reset => "none",
5991         output_power_up => "low",
5992         output_register_mode => "none",
5993         output_sync_reset => "none")
5994 -- pragma translate_on
5995 PORT MAP (
5996         datain => \vga_driver_unit|vsync_state_5\,
5997         devclrn => ww_devclrn,
5998         devpor => ww_devpor,
5999         devoe => ww_devoe,
6000         oe => VCC,
6001         padio => ww_d_vsync_state(5));
6002
6003 \d_vsync_state_out_4_\ : stratix_io
6004 -- pragma translate_off
6005 GENERIC MAP (
6006         ddio_mode => "none",
6007         input_async_reset => "none",
6008         input_power_up => "low",
6009         input_register_mode => "none",
6010         input_sync_reset => "none",
6011         oe_async_reset => "none",
6012         oe_power_up => "low",
6013         oe_register_mode => "none",
6014         oe_sync_reset => "none",
6015         operation_mode => "output",
6016         output_async_reset => "none",
6017         output_power_up => "low",
6018         output_register_mode => "none",
6019         output_sync_reset => "none")
6020 -- pragma translate_on
6021 PORT MAP (
6022         datain => \vga_driver_unit|vsync_state_4\,
6023         devclrn => ww_devclrn,
6024         devpor => ww_devpor,
6025         devoe => ww_devoe,
6026         oe => VCC,
6027         padio => ww_d_vsync_state(4));
6028
6029 \d_vsync_state_out_3_\ : stratix_io
6030 -- pragma translate_off
6031 GENERIC MAP (
6032         ddio_mode => "none",
6033         input_async_reset => "none",
6034         input_power_up => "low",
6035         input_register_mode => "none",
6036         input_sync_reset => "none",
6037         oe_async_reset => "none",
6038         oe_power_up => "low",
6039         oe_register_mode => "none",
6040         oe_sync_reset => "none",
6041         operation_mode => "output",
6042         output_async_reset => "none",
6043         output_power_up => "low",
6044         output_register_mode => "none",
6045         output_sync_reset => "none")
6046 -- pragma translate_on
6047 PORT MAP (
6048         datain => \vga_driver_unit|vsync_state_3\,
6049         devclrn => ww_devclrn,
6050         devpor => ww_devpor,
6051         devoe => ww_devoe,
6052         oe => VCC,
6053         padio => ww_d_vsync_state(3));
6054
6055 \d_vsync_state_out_2_\ : stratix_io
6056 -- pragma translate_off
6057 GENERIC MAP (
6058         ddio_mode => "none",
6059         input_async_reset => "none",
6060         input_power_up => "low",
6061         input_register_mode => "none",
6062         input_sync_reset => "none",
6063         oe_async_reset => "none",
6064         oe_power_up => "low",
6065         oe_register_mode => "none",
6066         oe_sync_reset => "none",
6067         operation_mode => "output",
6068         output_async_reset => "none",
6069         output_power_up => "low",
6070         output_register_mode => "none",
6071         output_sync_reset => "none")
6072 -- pragma translate_on
6073 PORT MAP (
6074         datain => \vga_driver_unit|vsync_state_2\,
6075         devclrn => ww_devclrn,
6076         devpor => ww_devpor,
6077         devoe => ww_devoe,
6078         oe => VCC,
6079         padio => ww_d_vsync_state(2));
6080
6081 \d_vsync_state_out_1_\ : stratix_io
6082 -- pragma translate_off
6083 GENERIC MAP (
6084         ddio_mode => "none",
6085         input_async_reset => "none",
6086         input_power_up => "low",
6087         input_register_mode => "none",
6088         input_sync_reset => "none",
6089         oe_async_reset => "none",
6090         oe_power_up => "low",
6091         oe_register_mode => "none",
6092         oe_sync_reset => "none",
6093         operation_mode => "output",
6094         output_async_reset => "none",
6095         output_power_up => "low",
6096         output_register_mode => "none",
6097         output_sync_reset => "none")
6098 -- pragma translate_on
6099 PORT MAP (
6100         datain => \vga_driver_unit|vsync_state_1\,
6101         devclrn => ww_devclrn,
6102         devpor => ww_devpor,
6103         devoe => ww_devoe,
6104         oe => VCC,
6105         padio => ww_d_vsync_state(1));
6106
6107 \d_vsync_state_out_0_\ : stratix_io
6108 -- pragma translate_off
6109 GENERIC MAP (
6110         ddio_mode => "none",
6111         input_async_reset => "none",
6112         input_power_up => "low",
6113         input_register_mode => "none",
6114         input_sync_reset => "none",
6115         oe_async_reset => "none",
6116         oe_power_up => "low",
6117         oe_register_mode => "none",
6118         oe_sync_reset => "none",
6119         operation_mode => "output",
6120         output_async_reset => "none",
6121         output_power_up => "low",
6122         output_register_mode => "none",
6123         output_sync_reset => "none")
6124 -- pragma translate_on
6125 PORT MAP (
6126         datain => \vga_driver_unit|vsync_state_0\,
6127         devclrn => ww_devclrn,
6128         devpor => ww_devpor,
6129         devoe => ww_devoe,
6130         oe => VCC,
6131         padio => ww_d_vsync_state(0));
6132
6133 d_state_clk_out : stratix_io
6134 -- pragma translate_off
6135 GENERIC MAP (
6136         ddio_mode => "none",
6137         input_async_reset => "none",
6138         input_power_up => "low",
6139         input_register_mode => "none",
6140         input_sync_reset => "none",
6141         oe_async_reset => "none",
6142         oe_power_up => "low",
6143         oe_register_mode => "none",
6144         oe_sync_reset => "none",
6145         operation_mode => "output",
6146         output_async_reset => "none",
6147         output_power_up => "low",
6148         output_register_mode => "none",
6149         output_sync_reset => "none")
6150 -- pragma translate_on
6151 PORT MAP (
6152         datain => \clk_pin~combout\,
6153         devclrn => ww_devclrn,
6154         devpor => ww_devpor,
6155         devoe => ww_devoe,
6156         oe => VCC,
6157         padio => ww_d_state_clk);
6158 END structure;
6159
6160