bsp3/Designflow/ppr/download/db/vga_pll.hier_info

   1 |vga_pll
   2 d_hsync <= vga:inst.d_hsync
   3 board_clk => vpll:inst1.inclk0
   4 reset => vga:inst.reset_pin
   5 d_vsync <= vga:inst.d_vsync
   6 d_set_column_counter <= vga:inst.d_set_column_counter
   7 d_set_line_counter <= vga:inst.d_set_line_counter
   8 d_set_hsync_counter <= vga:inst.d_set_hsync_counter
   9 d_set_vsync_counter <= vga:inst.d_set_vsync_counter
  10 d_r <= vga:inst.d_r
  11 d_g <= vga:inst.d_g
  12 d_b <= vga:inst.d_b
  13 d_h_enable <= vga:inst.d_h_enable
  14 d_v_enable <= vga:inst.d_v_enable
  15 d_state_clk <= vga:inst.d_state_clk
  16 r0_pin <= vga:inst.r0_pin
  17 r1_pin <= vga:inst.r1_pin
  18 r2_pin <= vga:inst.r2_pin
  19 g0_pin <= vga:inst.g0_pin
  20 g1_pin <= vga:inst.g1_pin
  21 g2_pin <= vga:inst.g2_pin
  22 b0_pin <= vga:inst.b0_pin
  23 b1_pin <= vga:inst.b1_pin
  24 hsync_pin <= vga:inst.hsync_pin
  25 vsync_pin <= vga:inst.vsync_pin
  26 d_column_counter[0] <= vga:inst.d_column_counter[0]
  27 d_column_counter[1] <= vga:inst.d_column_counter[1]
  28 d_column_counter[2] <= vga:inst.d_column_counter[2]
  29 d_column_counter[3] <= vga:inst.d_column_counter[3]
  30 d_column_counter[4] <= vga:inst.d_column_counter[4]
  31 d_column_counter[5] <= vga:inst.d_column_counter[5]
  32 d_column_counter[6] <= vga:inst.d_column_counter[6]
  33 d_column_counter[7] <= vga:inst.d_column_counter[7]
  34 d_column_counter[8] <= vga:inst.d_column_counter[8]
  35 d_column_counter[9] <= vga:inst.d_column_counter[9]
  36 d_hsync_counter[0] <= vga:inst.d_hsync_counter[0]
  37 d_hsync_counter[1] <= vga:inst.d_hsync_counter[1]
  38 d_hsync_counter[2] <= vga:inst.d_hsync_counter[2]
  39 d_hsync_counter[3] <= vga:inst.d_hsync_counter[3]
  40 d_hsync_counter[4] <= vga:inst.d_hsync_counter[4]
  41 d_hsync_counter[5] <= vga:inst.d_hsync_counter[5]
  42 d_hsync_counter[6] <= vga:inst.d_hsync_counter[6]
  43 d_hsync_counter[7] <= vga:inst.d_hsync_counter[7]
  44 d_hsync_counter[8] <= vga:inst.d_hsync_counter[8]
  45 d_hsync_counter[9] <= vga:inst.d_hsync_counter[9]
  46 d_hsync_state[6] <= vga:inst.d_hsync_state[6]
  47 d_hsync_state[5] <= vga:inst.d_hsync_state[5]
  48 d_hsync_state[4] <= vga:inst.d_hsync_state[4]
  49 d_hsync_state[3] <= vga:inst.d_hsync_state[3]
  50 d_hsync_state[2] <= vga:inst.d_hsync_state[2]
  51 d_hsync_state[1] <= vga:inst.d_hsync_state[1]
  52 d_hsync_state[0] <= vga:inst.d_hsync_state[0]
  53 d_line_counter[0] <= vga:inst.d_line_counter[0]
  54 d_line_counter[1] <= vga:inst.d_line_counter[1]
  55 d_line_counter[2] <= vga:inst.d_line_counter[2]
  56 d_line_counter[3] <= vga:inst.d_line_counter[3]
  57 d_line_counter[4] <= vga:inst.d_line_counter[4]
  58 d_line_counter[5] <= vga:inst.d_line_counter[5]
  59 d_line_counter[6] <= vga:inst.d_line_counter[6]
  60 d_line_counter[7] <= vga:inst.d_line_counter[7]
  61 d_line_counter[8] <= vga:inst.d_line_counter[8]
  62 d_vsync_counter[0] <= vga:inst.d_vsync_counter[0]
  63 d_vsync_counter[1] <= vga:inst.d_vsync_counter[1]
  64 d_vsync_counter[2] <= vga:inst.d_vsync_counter[2]
  65 d_vsync_counter[3] <= vga:inst.d_vsync_counter[3]
  66 d_vsync_counter[4] <= vga:inst.d_vsync_counter[4]
  67 d_vsync_counter[5] <= vga:inst.d_vsync_counter[5]
  68 d_vsync_counter[6] <= vga:inst.d_vsync_counter[6]
  69 d_vsync_counter[7] <= vga:inst.d_vsync_counter[7]
  70 d_vsync_counter[8] <= vga:inst.d_vsync_counter[8]
  71 d_vsync_counter[9] <= vga:inst.d_vsync_counter[9]
  72 d_vsync_state[6] <= vga:inst.d_vsync_state[6]
  73 d_vsync_state[5] <= vga:inst.d_vsync_state[5]
  74 d_vsync_state[4] <= vga:inst.d_vsync_state[4]
  75 d_vsync_state[3] <= vga:inst.d_vsync_state[3]
  76 d_vsync_state[2] <= vga:inst.d_vsync_state[2]
  77 d_vsync_state[1] <= vga:inst.d_vsync_state[1]
  78 d_vsync_state[0] <= vga:inst.d_vsync_state[0]
  79 seven_seg_pin[0] <= vga:inst.seven_seg_pin[0]
  80 seven_seg_pin[1] <= vga:inst.seven_seg_pin[1]
  81 seven_seg_pin[2] <= vga:inst.seven_seg_pin[2]
  82 seven_seg_pin[3] <= vga:inst.seven_seg_pin[3]
  83 seven_seg_pin[4] <= vga:inst.seven_seg_pin[4]
  84 seven_seg_pin[5] <= vga:inst.seven_seg_pin[5]
  85 seven_seg_pin[6] <= vga:inst.seven_seg_pin[6]
  86 seven_seg_pin[7] <= vga:inst.seven_seg_pin[7]
  87 seven_seg_pin[8] <= vga:inst.seven_seg_pin[8]
  88 seven_seg_pin[9] <= vga:inst.seven_seg_pin[9]
  89 seven_seg_pin[10] <= vga:inst.seven_seg_pin[10]
  90 seven_seg_pin[11] <= vga:inst.seven_seg_pin[11]
  91 seven_seg_pin[12] <= vga:inst.seven_seg_pin[12]
  92 seven_seg_pin[13] <= vga:inst.seven_seg_pin[13]
  93
  94
  95 |vga_pll|vga:inst
  96 clk_pin => clk_pin_in.PADIO
  97 reset_pin => reset_pin_in.PADIO
  98 r0_pin <= r0_pin_out.PADIO
  99 r1_pin <= r1_pin_out.PADIO
 100 r2_pin <= r2_pin_out.PADIO
 101 g0_pin <= g0_pin_out.PADIO
 102 g1_pin <= g1_pin_out.PADIO
 103 g2_pin <= g2_pin_out.PADIO
 104 b0_pin <= b0_pin_out.PADIO
 105 b1_pin <= b1_pin_out.PADIO
 106 hsync_pin <= hsync_pin_out.PADIO
 107 vsync_pin <= vsync_pin_out.PADIO
 108 seven_seg_pin[0] <= seven_seg_pin_tri_0_.PADIO
 109 seven_seg_pin[1] <= seven_seg_pin_out_1_.PADIO
 110 seven_seg_pin[2] <= seven_seg_pin_out_2_.PADIO
 111 seven_seg_pin[3] <= seven_seg_pin_tri_3_.PADIO
 112 seven_seg_pin[4] <= seven_seg_pin_tri_4_.PADIO
 113 seven_seg_pin[5] <= seven_seg_pin_tri_5_.PADIO
 114 seven_seg_pin[6] <= seven_seg_pin_tri_6_.PADIO
 115 seven_seg_pin[7] <= seven_seg_pin_out_7_.PADIO
 116 seven_seg_pin[8] <= seven_seg_pin_out_8_.PADIO
 117 seven_seg_pin[9] <= seven_seg_pin_out_9_.PADIO
 118 seven_seg_pin[10] <= seven_seg_pin_out_10_.PADIO
 119 seven_seg_pin[11] <= seven_seg_pin_out_11_.PADIO
 120 seven_seg_pin[12] <= seven_seg_pin_out_12_.PADIO
 121 seven_seg_pin[13] <= seven_seg_pin_tri_13_.PADIO
 122 d_hsync <= d_hsync_out.PADIO
 123 d_vsync <= d_vsync_out.PADIO
 124 d_column_counter[0] <= d_column_counter_out_0_.PADIO
 125 d_column_counter[1] <= d_column_counter_out_1_.PADIO
 126 d_column_counter[2] <= d_column_counter_out_2_.PADIO
 127 d_column_counter[3] <= d_column_counter_out_3_.PADIO
 128 d_column_counter[4] <= d_column_counter_out_4_.PADIO
 129 d_column_counter[5] <= d_column_counter_out_5_.PADIO
 130 d_column_counter[6] <= d_column_counter_out_6_.PADIO
 131 d_column_counter[7] <= d_column_counter_out_7_.PADIO
 132 d_column_counter[8] <= d_column_counter_out_8_.PADIO
 133 d_column_counter[9] <= d_column_counter_out_9_.PADIO
 134 d_line_counter[0] <= d_line_counter_out_0_.PADIO
 135 d_line_counter[1] <= d_line_counter_out_1_.PADIO
 136 d_line_counter[2] <= d_line_counter_out_2_.PADIO
 137 d_line_counter[3] <= d_line_counter_out_3_.PADIO
 138 d_line_counter[4] <= d_line_counter_out_4_.PADIO
 139 d_line_counter[5] <= d_line_counter_out_5_.PADIO
 140 d_line_counter[6] <= d_line_counter_out_6_.PADIO
 141 d_line_counter[7] <= d_line_counter_out_7_.PADIO
 142 d_line_counter[8] <= d_line_counter_out_8_.PADIO
 143 d_set_column_counter <= d_set_column_counter_out.PADIO
 144 d_set_line_counter <= d_set_line_counter_out.PADIO
 145 d_hsync_counter[0] <= d_hsync_counter_out_0_.PADIO
 146 d_hsync_counter[1] <= d_hsync_counter_out_1_.PADIO
 147 d_hsync_counter[2] <= d_hsync_counter_out_2_.PADIO
 148 d_hsync_counter[3] <= d_hsync_counter_out_3_.PADIO
 149 d_hsync_counter[4] <= d_hsync_counter_out_4_.PADIO
 150 d_hsync_counter[5] <= d_hsync_counter_out_5_.PADIO
 151 d_hsync_counter[6] <= d_hsync_counter_out_6_.PADIO
 152 d_hsync_counter[7] <= d_hsync_counter_out_7_.PADIO
 153 d_hsync_counter[8] <= d_hsync_counter_out_8_.PADIO
 154 d_hsync_counter[9] <= d_hsync_counter_out_9_.PADIO
 155 d_vsync_counter[0] <= d_vsync_counter_out_0_.PADIO
 156 d_vsync_counter[1] <= d_vsync_counter_out_1_.PADIO
 157 d_vsync_counter[2] <= d_vsync_counter_out_2_.PADIO
 158 d_vsync_counter[3] <= d_vsync_counter_out_3_.PADIO
 159 d_vsync_counter[4] <= d_vsync_counter_out_4_.PADIO
 160 d_vsync_counter[5] <= d_vsync_counter_out_5_.PADIO
 161 d_vsync_counter[6] <= d_vsync_counter_out_6_.PADIO
 162 d_vsync_counter[7] <= d_vsync_counter_out_7_.PADIO
 163 d_vsync_counter[8] <= d_vsync_counter_out_8_.PADIO
 164 d_vsync_counter[9] <= d_vsync_counter_out_9_.PADIO
 165 d_set_hsync_counter <= d_set_hsync_counter_out.PADIO
 166 d_set_vsync_counter <= d_set_vsync_counter_out.PADIO
 167 d_h_enable <= d_h_enable_out.PADIO
 168 d_v_enable <= d_v_enable_out.PADIO
 169 d_r <= d_r_out.PADIO
 170 d_g <= d_g_out.PADIO
 171 d_b <= d_b_out.PADIO
 172 d_hsync_state[6] <= d_hsync_state_out_6_.PADIO
 173 d_hsync_state[5] <= d_hsync_state_out_5_.PADIO
 174 d_hsync_state[4] <= d_hsync_state_out_4_.PADIO
 175 d_hsync_state[3] <= d_hsync_state_out_3_.PADIO
 176 d_hsync_state[2] <= d_hsync_state_out_2_.PADIO
 177 d_hsync_state[1] <= d_hsync_state_out_1_.PADIO
 178 d_hsync_state[0] <= d_hsync_state_out_0_.PADIO
 179 d_vsync_state[6] <= d_vsync_state_out_6_.PADIO
 180 d_vsync_state[5] <= d_vsync_state_out_5_.PADIO
 181 d_vsync_state[4] <= d_vsync_state_out_4_.PADIO
 182 d_vsync_state[3] <= d_vsync_state_out_3_.PADIO
 183 d_vsync_state[2] <= d_vsync_state_out_2_.PADIO
 184 d_vsync_state[1] <= d_vsync_state_out_1_.PADIO
 185 d_vsync_state[0] <= d_vsync_state_out_0_.PADIO
 186 d_state_clk <= d_state_clk_out.PADIO
 187
 188
 189 |vga_pll|vga:inst|vga_driver:vga_driver_unit
 190 line_counter_sig_0 <= line_counter_sig_0_.REGOUT
 191 line_counter_sig_1 <= line_counter_sig_1_.REGOUT
 192 line_counter_sig_2 <= line_counter_sig_2_.REGOUT
 193 line_counter_sig_3 <= line_counter_sig_3_.REGOUT
 194 line_counter_sig_4 <= line_counter_sig_4_.REGOUT
 195 line_counter_sig_5 <= line_counter_sig_5_.REGOUT
 196 line_counter_sig_6 <= line_counter_sig_6_.REGOUT
 197 line_counter_sig_7 <= line_counter_sig_7_.REGOUT
 198 line_counter_sig_8 <= line_counter_sig_8_.REGOUT
 199 dly_counter_1 => vsync_state_6_.DATAC
 200 dly_counter_1 => h_sync_Z.DATAC
 201 dly_counter_1 => v_sync_Z.DATAC
 202 dly_counter_1 => line_counter_next_0_sqmuxa_1_1_cZ.DATAC
 203 dly_counter_1 => vsync_counter_next_1_sqmuxa_cZ.DATAC
 204 dly_counter_1 => hsync_counter_next_1_sqmuxa_cZ.DATAC
 205 dly_counter_1 => column_counter_next_0_sqmuxa_1_1_cZ.DATAC
 206 dly_counter_0 => vsync_state_6_.DATAB
 207 dly_counter_0 => h_sync_Z.DATAB
 208 dly_counter_0 => v_sync_Z.DATAB
 209 dly_counter_0 => line_counter_next_0_sqmuxa_1_1_cZ.DATAB
 210 dly_counter_0 => vsync_counter_next_1_sqmuxa_cZ.DATAB
 211 dly_counter_0 => hsync_counter_next_1_sqmuxa_cZ.DATAB
 212 dly_counter_0 => column_counter_next_0_sqmuxa_1_1_cZ.DATAB
 213 vsync_state_2 <= vsync_state_2_.REGOUT
 214 vsync_state_5 <= vsync_state_5_.REGOUT
 215 vsync_state_3 <= vsync_state_3_.REGOUT
 216 vsync_state_6 <= vsync_state_6_.REGOUT
 217 vsync_state_4 <= vsync_state_4_.REGOUT
 218 vsync_state_1 <= vsync_state_1_.REGOUT
 219 vsync_state_0 <= vsync_state_0_.REGOUT
 220 hsync_state_2 <= hsync_state_2_.REGOUT
 221 hsync_state_4 <= hsync_state_4_.REGOUT
 222 hsync_state_0 <= hsync_state_0_.REGOUT
 223 hsync_state_5 <= hsync_state_5_.REGOUT
 224 hsync_state_1 <= hsync_state_1_.REGOUT
 225 hsync_state_3 <= hsync_state_3_.REGOUT
 226 hsync_state_6 <= hsync_state_6_.REGOUT
 227 column_counter_sig_0 <= column_counter_sig_0_.REGOUT
 228 column_counter_sig_1 <= column_counter_sig_1_.REGOUT
 229 column_counter_sig_2 <= column_counter_sig_2_.REGOUT
 230 column_counter_sig_3 <= column_counter_sig_3_.REGOUT
 231 column_counter_sig_4 <= column_counter_sig_4_.REGOUT
 232 column_counter_sig_5 <= column_counter_sig_5_.REGOUT
 233 column_counter_sig_6 <= column_counter_sig_6_.REGOUT
 234 column_counter_sig_7 <= column_counter_sig_7_.REGOUT
 235 column_counter_sig_8 <= column_counter_sig_8_.REGOUT
 236 column_counter_sig_9 <= column_counter_sig_9_.REGOUT
 237 vsync_counter_9 <= vsync_counter_9_.REGOUT
 238 vsync_counter_8 <= vsync_counter_8_.REGOUT
 239 vsync_counter_7 <= vsync_counter_7_.REGOUT
 240 vsync_counter_6 <= vsync_counter_6_.REGOUT
 241 vsync_counter_5 <= vsync_counter_5_.REGOUT
 242 vsync_counter_4 <= vsync_counter_4_.REGOUT
 243 vsync_counter_3 <= vsync_counter_3_.REGOUT
 244 vsync_counter_2 <= vsync_counter_2_.REGOUT
 245 vsync_counter_1 <= vsync_counter_1_.REGOUT
 246 vsync_counter_0 <= vsync_counter_0_.REGOUT
 247 hsync_counter_9 <= hsync_counter_9_.REGOUT
 248 hsync_counter_8 <= hsync_counter_8_.REGOUT
 249 hsync_counter_7 <= hsync_counter_7_.REGOUT
 250 hsync_counter_6 <= hsync_counter_6_.REGOUT
 251 hsync_counter_5 <= hsync_counter_5_.REGOUT
 252 hsync_counter_4 <= hsync_counter_4_.REGOUT
 253 hsync_counter_3 <= hsync_counter_3_.REGOUT
 254 hsync_counter_2 <= hsync_counter_2_.REGOUT
 255 hsync_counter_1 <= hsync_counter_1_.REGOUT
 256 hsync_counter_0 <= hsync_counter_0_.REGOUT
 257 d_set_vsync_counter <= d_set_vsync_counter_cZ.COMBOUT
 258 un10_column_counter_siglt6_1 <= COLUMN_COUNT_next_un10_column_counter_siglt6_1.COMBOUT
 259 un10_column_counter_siglt6_3 <= COLUMN_COUNT_next_un10_column_counter_siglt6_3.COMBOUT
 260 v_sync <= v_sync_Z.REGOUT
 261 h_sync <= h_sync_Z.REGOUT
 262 h_enable_sig <= h_enable_sig_Z.REGOUT
 263 v_enable_sig <= v_enable_sig_Z.REGOUT
 264 reset_pin_c => vsync_state_6_.DATAA
 265 reset_pin_c => h_sync_Z.DATAA
 266 reset_pin_c => v_sync_Z.DATAA
 267 reset_pin_c => line_counter_next_0_sqmuxa_1_1_cZ.DATAA
 268 reset_pin_c => vsync_counter_next_1_sqmuxa_cZ.DATAA
 269 reset_pin_c => hsync_counter_next_1_sqmuxa_cZ.DATAA
 270 reset_pin_c => column_counter_next_0_sqmuxa_1_1_cZ.DATAA
 271 un6_dly_counter_0_x <= vsync_state_6_.COMBOUT
 272 d_set_hsync_counter <= d_set_hsync_counter_cZ.COMBOUT
 273 clk_pin_c => hsync_counter_0_.CLK
 274 clk_pin_c => hsync_counter_1_.CLK
 275 clk_pin_c => hsync_counter_2_.CLK
 276 clk_pin_c => hsync_counter_3_.CLK
 277 clk_pin_c => hsync_counter_4_.CLK
 278 clk_pin_c => hsync_counter_5_.CLK
 279 clk_pin_c => hsync_counter_6_.CLK
 280 clk_pin_c => hsync_counter_7_.CLK
 281 clk_pin_c => hsync_counter_8_.CLK
 282 clk_pin_c => hsync_counter_9_.CLK
 283 clk_pin_c => vsync_counter_0_.CLK
 284 clk_pin_c => vsync_counter_1_.CLK
 285 clk_pin_c => vsync_counter_2_.CLK
 286 clk_pin_c => vsync_counter_3_.CLK
 287 clk_pin_c => vsync_counter_4_.CLK
 288 clk_pin_c => vsync_counter_5_.CLK
 289 clk_pin_c => vsync_counter_6_.CLK
 290 clk_pin_c => vsync_counter_7_.CLK
 291 clk_pin_c => vsync_counter_8_.CLK
 292 clk_pin_c => vsync_counter_9_.CLK
 293 clk_pin_c => column_counter_sig_9_.CLK
 294 clk_pin_c => column_counter_sig_8_.CLK
 295 clk_pin_c => column_counter_sig_7_.CLK
 296 clk_pin_c => column_counter_sig_6_.CLK
 297 clk_pin_c => column_counter_sig_5_.CLK
 298 clk_pin_c => column_counter_sig_4_.CLK
 299 clk_pin_c => column_counter_sig_3_.CLK
 300 clk_pin_c => column_counter_sig_2_.CLK
 301 clk_pin_c => column_counter_sig_1_.CLK
 302 clk_pin_c => column_counter_sig_0_.CLK
 303 clk_pin_c => hsync_state_6_.CLK
 304 clk_pin_c => vsync_state_0_.CLK
 305 clk_pin_c => vsync_state_1_.CLK
 306 clk_pin_c => vsync_state_6_.CLK
 307 clk_pin_c => line_counter_sig_8_.CLK
 308 clk_pin_c => line_counter_sig_7_.CLK
 309 clk_pin_c => line_counter_sig_6_.CLK
 310 clk_pin_c => line_counter_sig_5_.CLK
 311 clk_pin_c => line_counter_sig_4_.CLK
 312 clk_pin_c => line_counter_sig_3_.CLK
 313 clk_pin_c => line_counter_sig_2_.CLK
 314 clk_pin_c => line_counter_sig_1_.CLK
 315 clk_pin_c => line_counter_sig_0_.CLK
 316 clk_pin_c => v_enable_sig_Z.CLK
 317 clk_pin_c => h_enable_sig_Z.CLK
 318 clk_pin_c => h_sync_Z.CLK
 319 clk_pin_c => v_sync_Z.CLK
 320 clk_pin_c => vsync_state_5_.CLK
 321 clk_pin_c => vsync_state_4_.CLK
 322 clk_pin_c => vsync_state_3_.CLK
 323 clk_pin_c => vsync_state_2_.CLK
 324 clk_pin_c => hsync_state_5_.CLK
 325 clk_pin_c => hsync_state_4_.CLK
 326 clk_pin_c => hsync_state_3_.CLK
 327 clk_pin_c => hsync_state_2_.CLK
 328 clk_pin_c => hsync_state_1_.CLK
 329 clk_pin_c => hsync_state_0_.CLK
 330
 331
 332 |vga_pll|vga:inst|vga_control:vga_control_unit
 333 column_counter_sig_1 => g_next_i_o3_cZ.DATAB
 334 column_counter_sig_7 => r_next_i_o7_cZ.DATAA
 335 column_counter_sig_2 => b_next_i_o3_0_cZ.DATAC
 336 column_counter_sig_2 => g_next_i_o3_cZ.DATAA
 337 column_counter_sig_0 => b_next_i_a7_1_cZ.DATAC
 338 column_counter_sig_4 => N_23_i_0_g0_a_cZ.DATAB
 339 column_counter_sig_4 => b_next_i_o3_0_cZ.DATAB
 340 column_counter_sig_3 => N_23_i_0_g0_a_cZ.DATAA
 341 column_counter_sig_3 => b_next_i_o3_0_cZ.DATAA
 342 column_counter_sig_5 => g_Z.DATAB
 343 column_counter_sig_5 => N_4_i_0_g0_1_cZ.DATAA
 344 column_counter_sig_5 => N_6_i_0_g0_0_cZ.DATAA
 345 column_counter_sig_5 => b_next_i_a7_1_cZ.DATAA
 346 column_counter_sig_5 => b_next_i_o3_0_cZ.DATAD
 347 column_counter_sig_6 => b_Z.DATAA
 348 column_counter_sig_6 => r_Z.DATAA
 349 column_counter_sig_6 => g_Z.DATAA
 350 column_counter_sig_6 => N_4_i_0_g0_1_cZ.DATAB
 351 column_counter_sig_6 => N_6_i_0_g0_0_cZ.DATAB
 352 column_counter_sig_6 => b_next_i_a7_1_cZ.DATAB
 353 h_enable_sig => r_next_i_o7_cZ.DATAC
 354 v_enable_sig => r_next_i_o7_cZ.DATAB
 355 un10_column_counter_siglt6_1 => N_23_i_0_g0_a_cZ.DATAD
 356 g <= g_Z.REGOUT
 357 un10_column_counter_siglt6_3 => r_Z.DATAB
 358 un10_column_counter_siglt6_3 => N_6_i_0_g0_0_cZ.DATAC
 359 r <= r_Z.REGOUT
 360 un6_dly_counter_0_x => b_Z.ACLR
 361 un6_dly_counter_0_x => r_Z.ACLR
 362 un6_dly_counter_0_x => g_Z.ACLR
 363 clk_pin_c => b_Z.CLK
 364 clk_pin_c => r_Z.CLK
 365 clk_pin_c => g_Z.CLK
 366 b <= b_Z.REGOUT
 367
 368
 369 |vga_pll|vpll:inst1
 370 inclk0 => altpll:altpll_component.inclk[0]
 371 c0 <= altpll:altpll_component.clk[0]
 372
 373
 374 |vga_pll|vpll:inst1|altpll:altpll_component
 375 inclk[0] => pll.CLK
 376 inclk[1] => ~NO_FANOUT~
 377 fbin => ~NO_FANOUT~
 378 pllena => ~NO_FANOUT~
 379 clkswitch => ~NO_FANOUT~
 380 areset => ~NO_FANOUT~
 381 pfdena => ~NO_FANOUT~
 382 clkena[0] => ~NO_FANOUT~
 383 clkena[1] => pll.ENA1
 384 clkena[2] => pll.ENA2
 385 clkena[3] => pll.ENA3
 386 clkena[4] => pll.ENA4
 387 clkena[5] => pll.ENA5
 388 extclkena[0] => pll.EXTCLKENA
 389 extclkena[1] => pll.EXTCLKENA1
 390 extclkena[2] => pll.EXTCLKENA2
 391 extclkena[3] => pll.EXTCLKENA3
 392 scanclk => ~NO_FANOUT~
 393 scanclkena => ~NO_FANOUT~
 394 scanaclr => ~NO_FANOUT~
 395 scanread => ~NO_FANOUT~
 396 scanwrite => ~NO_FANOUT~
 397 scandata => ~NO_FANOUT~
 398 phasecounterselect[0] => ~NO_FANOUT~
 399 phasecounterselect[1] => ~NO_FANOUT~
 400 phasecounterselect[2] => ~NO_FANOUT~
 401 phasecounterselect[3] => ~NO_FANOUT~
 402 phaseupdown => ~NO_FANOUT~
 403 phasestep => ~NO_FANOUT~
 404 configupdate => ~NO_FANOUT~
 405 fbmimicbidir <= <GND>
 406 clk[0] <= clk[0]~0.DB_MAX_OUTPUT_PORT_TYPE
 407 clk[1] <= <GND>
 408 clk[2] <= <GND>
 409 clk[3] <= <GND>
 410 clk[4] <= <GND>
 411 clk[5] <= <GND>
 412 extclk[0] <= <GND>
 413 extclk[1] <= <GND>
 414 extclk[2] <= <GND>
 415 extclk[3] <= <GND>
 416 clkbad[0] <= <GND>
 417 clkbad[1] <= <GND>
 418 enable1 <= <GND>
 419 enable0 <= <GND>
 420 activeclock <= <GND>
 421 clkloss <= <GND>
 422 locked <= <GND>
 423 scandataout <= <GND>
 424 scandone <= <GND>
 425 sclkout0 <= <GND>
 426 sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE
 427 phasedone <= <GND>
 428 vcooverrange <= <GND>
 429 vcounderrange <= <GND>
 430 fbout <= <GND>
 431
 432