bsp3/Designflow/ppr/sim/db/vga.hier_info

   1 |vga
   2 clk_pin => clk_pin_in.PADIO
   3 reset_pin => reset_pin_in.PADIO
   4 r0_pin <= r0_pin_out.PADIO
   5 r1_pin <= r1_pin_out.PADIO
   6 r2_pin <= r2_pin_out.PADIO
   7 g0_pin <= g0_pin_out.PADIO
   8 g1_pin <= g1_pin_out.PADIO
   9 g2_pin <= g2_pin_out.PADIO
  10 b0_pin <= b0_pin_out.PADIO
  11 b1_pin <= b1_pin_out.PADIO
  12 hsync_pin <= hsync_pin_out.PADIO
  13 vsync_pin <= vsync_pin_out.PADIO
  14 seven_seg_pin[0] <= seven_seg_pin_tri_0_.PADIO
  15 seven_seg_pin[1] <= seven_seg_pin_out_1_.PADIO
  16 seven_seg_pin[2] <= seven_seg_pin_out_2_.PADIO
  17 seven_seg_pin[3] <= seven_seg_pin_tri_3_.PADIO
  18 seven_seg_pin[4] <= seven_seg_pin_tri_4_.PADIO
  19 seven_seg_pin[5] <= seven_seg_pin_tri_5_.PADIO
  20 seven_seg_pin[6] <= seven_seg_pin_tri_6_.PADIO
  21 seven_seg_pin[7] <= seven_seg_pin_out_7_.PADIO
  22 seven_seg_pin[8] <= seven_seg_pin_out_8_.PADIO
  23 seven_seg_pin[9] <= seven_seg_pin_out_9_.PADIO
  24 seven_seg_pin[10] <= seven_seg_pin_out_10_.PADIO
  25 seven_seg_pin[11] <= seven_seg_pin_out_11_.PADIO
  26 seven_seg_pin[12] <= seven_seg_pin_out_12_.PADIO
  27 seven_seg_pin[13] <= seven_seg_pin_tri_13_.PADIO
  28 d_hsync <= d_hsync_out.PADIO
  29 d_vsync <= d_vsync_out.PADIO
  30 d_column_counter[0] <= d_column_counter_out_0_.PADIO
  31 d_column_counter[1] <= d_column_counter_out_1_.PADIO
  32 d_column_counter[2] <= d_column_counter_out_2_.PADIO
  33 d_column_counter[3] <= d_column_counter_out_3_.PADIO
  34 d_column_counter[4] <= d_column_counter_out_4_.PADIO
  35 d_column_counter[5] <= d_column_counter_out_5_.PADIO
  36 d_column_counter[6] <= d_column_counter_out_6_.PADIO
  37 d_column_counter[7] <= d_column_counter_out_7_.PADIO
  38 d_column_counter[8] <= d_column_counter_out_8_.PADIO
  39 d_column_counter[9] <= d_column_counter_out_9_.PADIO
  40 d_line_counter[0] <= d_line_counter_out_0_.PADIO
  41 d_line_counter[1] <= d_line_counter_out_1_.PADIO
  42 d_line_counter[2] <= d_line_counter_out_2_.PADIO
  43 d_line_counter[3] <= d_line_counter_out_3_.PADIO
  44 d_line_counter[4] <= d_line_counter_out_4_.PADIO
  45 d_line_counter[5] <= d_line_counter_out_5_.PADIO
  46 d_line_counter[6] <= d_line_counter_out_6_.PADIO
  47 d_line_counter[7] <= d_line_counter_out_7_.PADIO
  48 d_line_counter[8] <= d_line_counter_out_8_.PADIO
  49 d_set_column_counter <= d_set_column_counter_out.PADIO
  50 d_set_line_counter <= d_set_line_counter_out.PADIO
  51 d_hsync_counter[0] <= d_hsync_counter_out_0_.PADIO
  52 d_hsync_counter[1] <= d_hsync_counter_out_1_.PADIO
  53 d_hsync_counter[2] <= d_hsync_counter_out_2_.PADIO
  54 d_hsync_counter[3] <= d_hsync_counter_out_3_.PADIO
  55 d_hsync_counter[4] <= d_hsync_counter_out_4_.PADIO
  56 d_hsync_counter[5] <= d_hsync_counter_out_5_.PADIO
  57 d_hsync_counter[6] <= d_hsync_counter_out_6_.PADIO
  58 d_hsync_counter[7] <= d_hsync_counter_out_7_.PADIO
  59 d_hsync_counter[8] <= d_hsync_counter_out_8_.PADIO
  60 d_hsync_counter[9] <= d_hsync_counter_out_9_.PADIO
  61 d_vsync_counter[0] <= d_vsync_counter_out_0_.PADIO
  62 d_vsync_counter[1] <= d_vsync_counter_out_1_.PADIO
  63 d_vsync_counter[2] <= d_vsync_counter_out_2_.PADIO
  64 d_vsync_counter[3] <= d_vsync_counter_out_3_.PADIO
  65 d_vsync_counter[4] <= d_vsync_counter_out_4_.PADIO
  66 d_vsync_counter[5] <= d_vsync_counter_out_5_.PADIO
  67 d_vsync_counter[6] <= d_vsync_counter_out_6_.PADIO
  68 d_vsync_counter[7] <= d_vsync_counter_out_7_.PADIO
  69 d_vsync_counter[8] <= d_vsync_counter_out_8_.PADIO
  70 d_vsync_counter[9] <= d_vsync_counter_out_9_.PADIO
  71 d_set_hsync_counter <= d_set_hsync_counter_out.PADIO
  72 d_set_vsync_counter <= d_set_vsync_counter_out.PADIO
  73 d_h_enable <= d_h_enable_out.PADIO
  74 d_v_enable <= d_v_enable_out.PADIO
  75 d_r <= d_r_out.PADIO
  76 d_g <= d_g_out.PADIO
  77 d_b <= d_b_out.PADIO
  78 d_hsync_state[6] <= d_hsync_state_out_6_.PADIO
  79 d_hsync_state[5] <= d_hsync_state_out_5_.PADIO
  80 d_hsync_state[4] <= d_hsync_state_out_4_.PADIO
  81 d_hsync_state[3] <= d_hsync_state_out_3_.PADIO
  82 d_hsync_state[2] <= d_hsync_state_out_2_.PADIO
  83 d_hsync_state[1] <= d_hsync_state_out_1_.PADIO
  84 d_hsync_state[0] <= d_hsync_state_out_0_.PADIO
  85 d_vsync_state[6] <= d_vsync_state_out_6_.PADIO
  86 d_vsync_state[5] <= d_vsync_state_out_5_.PADIO
  87 d_vsync_state[4] <= d_vsync_state_out_4_.PADIO
  88 d_vsync_state[3] <= d_vsync_state_out_3_.PADIO
  89 d_vsync_state[2] <= d_vsync_state_out_2_.PADIO
  90 d_vsync_state[1] <= d_vsync_state_out_1_.PADIO
  91 d_vsync_state[0] <= d_vsync_state_out_0_.PADIO
  92 d_state_clk <= d_state_clk_out.PADIO
  93
  94
  95 |vga|vga_driver:vga_driver_unit
  96 line_counter_sig_0 <= line_counter_sig_0_.REGOUT
  97 line_counter_sig_1 <= line_counter_sig_1_.REGOUT
  98 line_counter_sig_2 <= line_counter_sig_2_.REGOUT
  99 line_counter_sig_3 <= line_counter_sig_3_.REGOUT
 100 line_counter_sig_4 <= line_counter_sig_4_.REGOUT
 101 line_counter_sig_5 <= line_counter_sig_5_.REGOUT
 102 line_counter_sig_6 <= line_counter_sig_6_.REGOUT
 103 line_counter_sig_7 <= line_counter_sig_7_.REGOUT
 104 line_counter_sig_8 <= line_counter_sig_8_.REGOUT
 105 dly_counter_1 => vsync_state_6_.DATAC
 106 dly_counter_1 => h_sync_Z.DATAC
 107 dly_counter_1 => v_sync_Z.DATAC
 108 dly_counter_1 => line_counter_next_0_sqmuxa_1_1_cZ.DATAC
 109 dly_counter_1 => vsync_counter_next_1_sqmuxa_cZ.DATAC
 110 dly_counter_1 => hsync_counter_next_1_sqmuxa_cZ.DATAC
 111 dly_counter_1 => column_counter_next_0_sqmuxa_1_1_cZ.DATAC
 112 dly_counter_0 => vsync_state_6_.DATAB
 113 dly_counter_0 => h_sync_Z.DATAB
 114 dly_counter_0 => v_sync_Z.DATAB
 115 dly_counter_0 => line_counter_next_0_sqmuxa_1_1_cZ.DATAB
 116 dly_counter_0 => vsync_counter_next_1_sqmuxa_cZ.DATAB
 117 dly_counter_0 => hsync_counter_next_1_sqmuxa_cZ.DATAB
 118 dly_counter_0 => column_counter_next_0_sqmuxa_1_1_cZ.DATAB
 119 vsync_state_2 <= vsync_state_2_.REGOUT
 120 vsync_state_5 <= vsync_state_5_.REGOUT
 121 vsync_state_3 <= vsync_state_3_.REGOUT
 122 vsync_state_6 <= vsync_state_6_.REGOUT
 123 vsync_state_4 <= vsync_state_4_.REGOUT
 124 vsync_state_1 <= vsync_state_1_.REGOUT
 125 vsync_state_0 <= vsync_state_0_.REGOUT
 126 hsync_state_2 <= hsync_state_2_.REGOUT
 127 hsync_state_4 <= hsync_state_4_.REGOUT
 128 hsync_state_0 <= hsync_state_0_.REGOUT
 129 hsync_state_5 <= hsync_state_5_.REGOUT
 130 hsync_state_1 <= hsync_state_1_.REGOUT
 131 hsync_state_3 <= hsync_state_3_.REGOUT
 132 hsync_state_6 <= hsync_state_6_.REGOUT
 133 column_counter_sig_0 <= column_counter_sig_0_.REGOUT
 134 column_counter_sig_1 <= column_counter_sig_1_.REGOUT
 135 column_counter_sig_2 <= column_counter_sig_2_.REGOUT
 136 column_counter_sig_3 <= column_counter_sig_3_.REGOUT
 137 column_counter_sig_4 <= column_counter_sig_4_.REGOUT
 138 column_counter_sig_5 <= column_counter_sig_5_.REGOUT
 139 column_counter_sig_6 <= column_counter_sig_6_.REGOUT
 140 column_counter_sig_7 <= column_counter_sig_7_.REGOUT
 141 column_counter_sig_8 <= column_counter_sig_8_.REGOUT
 142 column_counter_sig_9 <= column_counter_sig_9_.REGOUT
 143 vsync_counter_9 <= vsync_counter_9_.REGOUT
 144 vsync_counter_8 <= vsync_counter_8_.REGOUT
 145 vsync_counter_7 <= vsync_counter_7_.REGOUT
 146 vsync_counter_6 <= vsync_counter_6_.REGOUT
 147 vsync_counter_5 <= vsync_counter_5_.REGOUT
 148 vsync_counter_4 <= vsync_counter_4_.REGOUT
 149 vsync_counter_3 <= vsync_counter_3_.REGOUT
 150 vsync_counter_2 <= vsync_counter_2_.REGOUT
 151 vsync_counter_1 <= vsync_counter_1_.REGOUT
 152 vsync_counter_0 <= vsync_counter_0_.REGOUT
 153 hsync_counter_9 <= hsync_counter_9_.REGOUT
 154 hsync_counter_8 <= hsync_counter_8_.REGOUT
 155 hsync_counter_7 <= hsync_counter_7_.REGOUT
 156 hsync_counter_6 <= hsync_counter_6_.REGOUT
 157 hsync_counter_5 <= hsync_counter_5_.REGOUT
 158 hsync_counter_4 <= hsync_counter_4_.REGOUT
 159 hsync_counter_3 <= hsync_counter_3_.REGOUT
 160 hsync_counter_2 <= hsync_counter_2_.REGOUT
 161 hsync_counter_1 <= hsync_counter_1_.REGOUT
 162 hsync_counter_0 <= hsync_counter_0_.REGOUT
 163 d_set_vsync_counter <= d_set_vsync_counter_cZ.COMBOUT
 164 un10_column_counter_siglt6_1 <= COLUMN_COUNT_next_un10_column_counter_siglt6_1.COMBOUT
 165 un10_column_counter_siglt6_3 <= COLUMN_COUNT_next_un10_column_counter_siglt6_3.COMBOUT
 166 v_sync <= v_sync_Z.REGOUT
 167 h_sync <= h_sync_Z.REGOUT
 168 h_enable_sig <= h_enable_sig_Z.REGOUT
 169 v_enable_sig <= v_enable_sig_Z.REGOUT
 170 reset_pin_c => vsync_state_6_.DATAA
 171 reset_pin_c => h_sync_Z.DATAA
 172 reset_pin_c => v_sync_Z.DATAA
 173 reset_pin_c => line_counter_next_0_sqmuxa_1_1_cZ.DATAA
 174 reset_pin_c => vsync_counter_next_1_sqmuxa_cZ.DATAA
 175 reset_pin_c => hsync_counter_next_1_sqmuxa_cZ.DATAA
 176 reset_pin_c => column_counter_next_0_sqmuxa_1_1_cZ.DATAA
 177 un6_dly_counter_0_x <= vsync_state_6_.COMBOUT
 178 d_set_hsync_counter <= d_set_hsync_counter_cZ.COMBOUT
 179 clk_pin_c => hsync_counter_0_.CLK
 180 clk_pin_c => hsync_counter_1_.CLK
 181 clk_pin_c => hsync_counter_2_.CLK
 182 clk_pin_c => hsync_counter_3_.CLK
 183 clk_pin_c => hsync_counter_4_.CLK
 184 clk_pin_c => hsync_counter_5_.CLK
 185 clk_pin_c => hsync_counter_6_.CLK
 186 clk_pin_c => hsync_counter_7_.CLK
 187 clk_pin_c => hsync_counter_8_.CLK
 188 clk_pin_c => hsync_counter_9_.CLK
 189 clk_pin_c => vsync_counter_0_.CLK
 190 clk_pin_c => vsync_counter_1_.CLK
 191 clk_pin_c => vsync_counter_2_.CLK
 192 clk_pin_c => vsync_counter_3_.CLK
 193 clk_pin_c => vsync_counter_4_.CLK
 194 clk_pin_c => vsync_counter_5_.CLK
 195 clk_pin_c => vsync_counter_6_.CLK
 196 clk_pin_c => vsync_counter_7_.CLK
 197 clk_pin_c => vsync_counter_8_.CLK
 198 clk_pin_c => vsync_counter_9_.CLK
 199 clk_pin_c => column_counter_sig_9_.CLK
 200 clk_pin_c => column_counter_sig_8_.CLK
 201 clk_pin_c => column_counter_sig_7_.CLK
 202 clk_pin_c => column_counter_sig_6_.CLK
 203 clk_pin_c => column_counter_sig_5_.CLK
 204 clk_pin_c => column_counter_sig_4_.CLK
 205 clk_pin_c => column_counter_sig_3_.CLK
 206 clk_pin_c => column_counter_sig_2_.CLK
 207 clk_pin_c => column_counter_sig_1_.CLK
 208 clk_pin_c => column_counter_sig_0_.CLK
 209 clk_pin_c => hsync_state_6_.CLK
 210 clk_pin_c => vsync_state_0_.CLK
 211 clk_pin_c => vsync_state_1_.CLK
 212 clk_pin_c => vsync_state_6_.CLK
 213 clk_pin_c => line_counter_sig_8_.CLK
 214 clk_pin_c => line_counter_sig_7_.CLK
 215 clk_pin_c => line_counter_sig_6_.CLK
 216 clk_pin_c => line_counter_sig_5_.CLK
 217 clk_pin_c => line_counter_sig_4_.CLK
 218 clk_pin_c => line_counter_sig_3_.CLK
 219 clk_pin_c => line_counter_sig_2_.CLK
 220 clk_pin_c => line_counter_sig_1_.CLK
 221 clk_pin_c => line_counter_sig_0_.CLK
 222 clk_pin_c => v_enable_sig_Z.CLK
 223 clk_pin_c => h_enable_sig_Z.CLK
 224 clk_pin_c => h_sync_Z.CLK
 225 clk_pin_c => v_sync_Z.CLK
 226 clk_pin_c => vsync_state_5_.CLK
 227 clk_pin_c => vsync_state_4_.CLK
 228 clk_pin_c => vsync_state_3_.CLK
 229 clk_pin_c => vsync_state_2_.CLK
 230 clk_pin_c => hsync_state_5_.CLK
 231 clk_pin_c => hsync_state_4_.CLK
 232 clk_pin_c => hsync_state_3_.CLK
 233 clk_pin_c => hsync_state_2_.CLK
 234 clk_pin_c => hsync_state_1_.CLK
 235 clk_pin_c => hsync_state_0_.CLK
 236
 237
 238 |vga|vga_control:vga_control_unit
 239 column_counter_sig_1 => g_next_i_o3_cZ.DATAB
 240 column_counter_sig_7 => r_next_i_o7_cZ.DATAA
 241 column_counter_sig_2 => b_next_i_o3_0_cZ.DATAC
 242 column_counter_sig_2 => g_next_i_o3_cZ.DATAA
 243 column_counter_sig_0 => b_next_i_a7_1_cZ.DATAC
 244 column_counter_sig_4 => N_23_i_0_g0_a_cZ.DATAB
 245 column_counter_sig_4 => b_next_i_o3_0_cZ.DATAB
 246 column_counter_sig_3 => N_23_i_0_g0_a_cZ.DATAA
 247 column_counter_sig_3 => b_next_i_o3_0_cZ.DATAA
 248 column_counter_sig_5 => g_Z.DATAB
 249 column_counter_sig_5 => N_4_i_0_g0_1_cZ.DATAA
 250 column_counter_sig_5 => N_6_i_0_g0_0_cZ.DATAA
 251 column_counter_sig_5 => b_next_i_a7_1_cZ.DATAA
 252 column_counter_sig_5 => b_next_i_o3_0_cZ.DATAD
 253 column_counter_sig_6 => b_Z.DATAA
 254 column_counter_sig_6 => r_Z.DATAA
 255 column_counter_sig_6 => g_Z.DATAA
 256 column_counter_sig_6 => N_4_i_0_g0_1_cZ.DATAB
 257 column_counter_sig_6 => N_6_i_0_g0_0_cZ.DATAB
 258 column_counter_sig_6 => b_next_i_a7_1_cZ.DATAB
 259 h_enable_sig => r_next_i_o7_cZ.DATAC
 260 v_enable_sig => r_next_i_o7_cZ.DATAB
 261 un10_column_counter_siglt6_1 => N_23_i_0_g0_a_cZ.DATAD
 262 g <= g_Z.REGOUT
 263 un10_column_counter_siglt6_3 => r_Z.DATAB
 264 un10_column_counter_siglt6_3 => N_6_i_0_g0_0_cZ.DATAC
 265 r <= r_Z.REGOUT
 266 un6_dly_counter_0_x => b_Z.ACLR
 267 un6_dly_counter_0_x => r_Z.ACLR
 268 un6_dly_counter_0_x => g_Z.ACLR
 269 clk_pin_c => b_Z.CLK
 270 clk_pin_c => r_Z.CLK
 271 clk_pin_c => g_Z.CLK
 272 b <= b_Z.REGOUT
 273
 274