4er slot (3. bsp fertig)

[dide_16.git] / bsp3 / Designflow / ppr / download / simulation / modelsim / vga_pll.sft

set tool_name "ModelSim-Altera (Verilog)"
set corner_file_list {
        {{"Slow Model"} {vga_pll.vo vga_pll_v.sdo}}
}