- 2.0.0
- this NEWS file is neglected in favor of the svn commit logs.
- See http://snapshots.linuxbios.org/
+ See http://tracker.coreboot.org/
- 1.1.8
- Store everything in arch
- 1.1.7
-------------------------------------------------------------------------------
-LinuxBIOS README
+Coreboot README
-------------------------------------------------------------------------------
-LinuxBIOS is a Free Software project aimed at replacing the proprietary
+Coreboot is a Free Software project aimed at replacing the proprietary
BIOS you can find in most of today's computers.
It performs just a little bit of hardware initialization and then executes
--------
After the basic initialization of the hardware has been performed, any
-desired "payload" can be started by LinuxBIOS. Examples include:
+desired "payload" can be started by coreboot. Examples include:
* A Linux kernel
* FILO (a simple bootloader with filesystem support)
Supported Hardware
------------------
-LinuxBIOS supports a wide range of chipsets, devices, and mainboards.
+Coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
- * http://www.linuxbios.org/Supported_Motherboards
- * http://www.linuxbios.org/Supported_Chipsets_and_Devices
+ * http://www.coreboot.org/Supported_Motherboards
+ * http://www.coreboot.org/Supported_Chipsets_and_Devices
Website and Mailing List
------------------------
Further details on the project, a FAQ, many HOWTOs, news, development
-guidelines and more can be found on the LinuxBIOS website:
+guidelines and more can be found on the coreboot website:
- http://www.linuxbios.org
+ http://www.coreboot.org
-You can contact us directly on the LinuxBIOS mailing list:
+You can contact us directly on the coreboot mailing list:
- http://www.linuxbios.org/Mailinglist
+ http://www.coreboot.org/Mailinglist
Copyright and License
---------------------
-The copyright on LinuxBIOS is owned by quite a large number of individual
+The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.
-LinuxBIOS is licensed under the terms of the GNU General Public License (GPL).
+Coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files (mostly those derived from the Linux kernel) are licensed under
the "GPL, version 2". For some parts, which were derived from other projects,
other (GPL-compatible) licenses may apply. Please check the individual
source files for details.
-This makes the resulting LinuxBIOS images licensed under the GPL, version 2.
+This makes the resulting coreboot images licensed under the GPL, version 2.
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x10000
- option LINUXBIOS_EXTRA_VERSION=".0Normal"
+ option COREBOOT_EXTRA_VERSION=".0Normal"
mainboard amd/solo
payload /suse/stepan/tg3ide_
disk.zelf
Default image size. Defaults to \texttt{65535} bytes.
-\item \begin{verbatim}LINUXBIOS_EXTRA_VERSION\end{verbatim}
+\item \begin{verbatim}COREBOOT_EXTRA_VERSION\end{verbatim}
LinuxBIOS extra version. This option has an empty string as default. Set
to any string to add an extra version string to your LinuxBIOS build.
export HEAP_SIZE:=8192
export STACK_SIZE:=8192
export MEMORY_HOLE:=0
-export LINUXBIOS_VERSION:=1.1.0
+export COREBOOT_VERSION:=1.1.0
export CC:=$(CROSS_COMPILE)gcc
\end{verbatim}
end
makerule all
- depends "linuxbios.rom"
+ depends "coreboot.rom"
end
makerule floppy
depends "all"
- action "mcopy -o linuxbios.rom a:"
+ action "mcopy -o coreboot.rom a:"
end
makerule nrv2b
# this one example shows the mess that has occurred. People are now mixing
# conditional if in the make style with if in the config language style.
# The -1 is linux standard.
-# I don't much like it but it is the mode nowadays. So linuxbios will change
+# I don't much like it but it is the mode nowadays. So coreboot will change
# what a mess. -- RGM
# catch the case where there is no compression
makedefine PAYLOAD-1:=payload
end
if USE_FAILOVER_IMAGE
- makedefine LINUXBIOS_APC:=
- makedefine LINUXBIOS_RAM_ROM:=
+ makedefine COREBOOT_APC:=
+ makedefine COREBOOT_RAM_ROM:=
- makerule linuxbios.rom
- depends "linuxbios.strip"
+ makerule coreboot.rom
+ depends "coreboot.strip"
action "cp $< $@"
end
else
- makerule linuxbios.rom
- depends "linuxbios.strip buildrom $(PAYLOAD-1)"
+ makerule coreboot.rom
+ depends "coreboot.strip buildrom $(PAYLOAD-1)"
action "./buildrom $< $@ $(PAYLOAD-1) $(ROM_IMAGE_SIZE) $(ROM_SECTION_SIZE)"
end
end
action "$(OBJCOPY) --rename-section .text=.init.text --rename-section .data=.init.data --rename-section .rodata=.init.rodata --rename-section .rodata.str1.1=.init.rodata.str1.1 init.pre.o init.o"
end
- makerule linuxbios
- depends "crt0.o init.o $(LINUXBIOS_APC) $(LINUXBIOS_RAM_ROM) ldscript.ld"
+ makerule coreboot
+ depends "crt0.o init.o $(COREBOOT_APC) $(COREBOOT_RAM_ROM) ldscript.ld"
action "$(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o init.o"
- action "$(CROSS_COMPILE)nm -n linuxbios | sort > linuxbios.map"
+ action "$(CROSS_COMPILE)nm -n coreboot | sort > coreboot.map"
end
end
/*
- * LinuxBIOS ACPI Table support
+ * coreboot ACPI Table support
* written by Stefan Reinauer <stepan@openbios.org>
* (C) 2004 SUSE LINUX AG
* (C) 2005 Stefan Reinauer
" addl 12(%%esp), %%eax\n\t"
" addl 8(%%esp), %%eax\n\t"
" movl %%eax, 20(%%esp)\n\t"
- /* Place a copy of linuxBIOS in it's new location */
- /* Move ``longs'' the linuxBIOS size is 4 byte aligned */
+ /* Place a copy of coreboot in it's new location */
+ /* Move ``longs'' the coreboot size is 4 byte aligned */
" movl 12(%%esp), %%edi\n\t"
" addl 8(%%esp), %%edi\n\t"
" movl 16(%%esp), %%esi\n\t"
" shrl $2, %%ecx\n\t"
" rep movsl\n\t"
- /* Adjust the stack pointer to point into the new linuxBIOS image */
+ /* Adjust the stack pointer to point into the new coreboot image */
" addl 20(%%esp), %%esp\n\t"
- /* Adjust the instruction pointer to point into the new linuxBIOS image */
+ /* Adjust the instruction pointer to point into the new coreboot image */
" movl $1f, %%eax\n\t"
" addl 20(%%esp), %%eax\n\t"
" jmp *%%eax\n\t"
"1: \n\t"
- /* Copy the linuxBIOS bounce buffer over linuxBIOS */
- /* Move ``longs'' the linuxBIOS size is 4 byte aligned */
+ /* Copy the coreboot bounce buffer over coreboot */
+ /* Move ``longs'' the coreboot size is 4 byte aligned */
" movl 16(%%esp), %%edi\n\t"
" movl 12(%%esp), %%esi\n\t"
" movl 8(%%esp), %%ecx\n\t"
" cli \n\t"
" cld \n\t"
- /* Copy the saved copy of linuxBIOS where linuxBIOS runs */
- /* Move ``longs'' the linuxBIOS size is 4 byte aligned */
+ /* Copy the saved copy of coreboot where coreboot runs */
+ /* Move ``longs'' the coreboot size is 4 byte aligned */
" movl 16(%%esp), %%edi\n\t"
" movl 12(%%esp), %%esi\n\t"
" addl 8(%%esp), %%esi\n\t"
" shrl $2, %%ecx\n\t"
" rep movsl\n\t"
- /* Adjust the stack pointer to point into the old linuxBIOS image */
+ /* Adjust the stack pointer to point into the old coreboot image */
" subl 20(%%esp), %%esp\n\t"
- /* Adjust the instruction pointer to point into the old linuxBIOS image */
+ /* Adjust the instruction pointer to point into the old coreboot image */
" movl $1f, %%eax\n\t"
" subl 20(%%esp), %%eax\n\t"
" jmp *%%eax\n\t"
uint32_t tag;
const char *string;
} strings[] = {
- { LB_TAG_VERSION, linuxbios_version, },
- { LB_TAG_EXTRA_VERSION, linuxbios_extra_version, },
- { LB_TAG_BUILD, linuxbios_build, },
- { LB_TAG_COMPILE_TIME, linuxbios_compile_time, },
- { LB_TAG_COMPILE_BY, linuxbios_compile_by, },
- { LB_TAG_COMPILE_HOST, linuxbios_compile_host, },
- { LB_TAG_COMPILE_DOMAIN, linuxbios_compile_domain, },
- { LB_TAG_COMPILER, linuxbios_compiler, },
- { LB_TAG_LINKER, linuxbios_linker, },
- { LB_TAG_ASSEMBLER, linuxbios_assembler, },
+ { LB_TAG_VERSION, coreboot_version, },
+ { LB_TAG_EXTRA_VERSION, coreboot_extra_version, },
+ { LB_TAG_BUILD, coreboot_build, },
+ { LB_TAG_COMPILE_TIME, coreboot_compile_time, },
+ { LB_TAG_COMPILE_BY, coreboot_compile_by, },
+ { LB_TAG_COMPILE_HOST, coreboot_compile_host, },
+ { LB_TAG_COMPILE_DOMAIN, coreboot_compile_domain, },
+ { LB_TAG_COMPILER, coreboot_compiler, },
+ { LB_TAG_LINKER, coreboot_linker, },
+ { LB_TAG_ASSEMBLER, coreboot_assembler, },
};
unsigned int i;
for(i = 0; i < sizeof(strings)/sizeof(strings[0]); i++) {
head->table_checksum = compute_ip_checksum(first_rec, head->table_bytes);
head->header_checksum = 0;
head->header_checksum = compute_ip_checksum(head, sizeof(*head));
- printk_debug("Wrote linuxbios table at: %p - %p checksum %lx\n",
+ printk_debug("Wrote coreboot table at: %p - %p checksum %lx\n",
head, rec, head->table_checksum);
return (unsigned long)rec;
}
lb_cleanup_memory_ranges(mem);
}
-/* Routines to extract part so the linuxBIOS table or
- * information from the linuxBIOS table after we have written it.
+/* Routines to extract part so the coreboot table or
+ * information from the coreboot table after we have written it.
* Currently get_lb_mem relies on a global we can change the
* implementaiton.
*/
return mem;
}
-unsigned long write_linuxbios_table(
+unsigned long write_coreboot_table(
unsigned long low_table_start, unsigned long low_table_end,
unsigned long rom_table_start, unsigned long rom_table_end)
{
rec_dest = lb_new_record(head);
rec_src = (struct lb_record *)(void *)&option_table;
memcpy(rec_dest, rec_src, rec_src->size);
- /* Create cmos checksum entry in linuxbios table */
+ /* Create cmos checksum entry in coreboot table */
lb_cmos_checksum(head);
}
#endif
/* Note:
* I assume that there is always memory at immediately after
- * the low_table_end. This means that after I setup the linuxbios table.
+ * the low_table_end. This means that after I setup the coreboot table.
* I can trivially fixup the reserved memory ranges to hold the correct
- * size of the linuxbios table.
+ * size of the coreboot table.
*/
/* Record our motheboard */
-#ifndef LINUXBIOS_TABLE_H
-#define LINUXBIOS_TABLE_H
+#ifndef COREBOOT_TABLE_H
+#define COREBOOT_TABLE_H
#include <boot/linuxbios_tables.h>
-/* This file holds function prototypes for building the linuxbios table. */
-unsigned long write_linuxbios_table(
+/* This file holds function prototypes for building the coreboot table. */
+unsigned long write_coreboot_table(
unsigned long low_table_start, unsigned long low_table_end,
unsigned long rom_table_start, unsigned long rom_table_end);
struct lb_mainboard *lb_mainboard(struct lb_header *header);
unsigned long lb_table_fini(struct lb_header *header);
-/* Routines to extract part so the linuxBIOS table or information
- * from the linuxBIOS table.
+/* Routines to extract part so the coreboot table or information
+ * from the coreboot table.
*/
struct lb_memory *get_lb_mem(void);
extern struct cmos_option_table option_table;
-#endif /* LINUXBIOS_TABLE_H */
+#endif /* COREBOOT_TABLE_H */
// Copy GDT to new location and reload it
// 2003-07 by SONE Takeshi
-// Ported from Etherboot to LinuxBIOS 2005-08 by Steve Magnani
+// Ported from Etherboot to coreboot 2005-08 by Steve Magnani
void move_gdt(unsigned long newgdt)
{
uint16_t num_gdt_bytes = &gdt_end - &gdt;
/* Write ACPI tables */
/* write them in the rom area because DSDT can be large (8K on epia-m) which
- * pushes linuxbios table out of first 4K if set up in low table area
+ * pushes coreboot table out of first 4K if set up in low table area
*/
rom_table_end = write_acpi_tables(rom_table_end);
rom_table_end = (rom_table_end+1023) & ~1023;
move_gdt(low_table_end);
low_table_end += &gdt_end - &gdt;
- /* The linuxbios table must be in 0-4K or 960K-1M */
- write_linuxbios_table(low_table_start, low_table_end,
+ /* The coreboot table must be in 0-4K or 960K-1M */
+ write_coreboot_table(low_table_start, low_table_end,
rom_table_start, rom_table_end);
return get_lb_mem();
/*
- * Initial LinuxBIOS ACPI Support - headers and defines.
+ * coreboot ACPI Support - headers and defines.
*
* written by Stefan Reinauer <stepan@openbios.org>
* (C) 2004 SUSE LINUX AG
typedef unsigned device_t; /* pci and pci_mmio need to have different ways to have dev */
-/* FIXME: We need to make the LinuxBIOS to run at 64bit mode, So when read/write memory above 4G,
+/* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G,
* We don't need to set %fs, and %gs anymore
* Before that We need to use %gs, and leave %fs to other RAM access
*/
*
* - Converted to gas assembly, and refitted to work with etherboot.
* Eric Biederman 20 Aug 2002
- * - Merged the nrv2b decompressor into crt0.base of LinuxBIOS
+ * - Merged the nrv2b decompressor into crt0.base of coreboot
* Eric Biederman 26 Sept 2002
*/
cld /* clear direction flag */
- /* copy linuxBIOS from it's initial load location to
+ /* copy coreboot from it's initial load location to
* the location it is compiled to run at.
* Normally this is copying from FLASH ROM to RAM.
*/
#if defined(CONSOLE_DEBUG_TX_STRING) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
.section ".rom.data"
-str_copying_to_ram: .string "Copying LinuxBIOS to RAM.\r\n"
-str_pre_main: .string "Jumping to LinuxBIOS.\r\n"
+str_copying_to_ram: .string "Copying coreboot to RAM.\r\n"
+str_pre_main: .string "Jumping to coreboot.\r\n"
.previous
#endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */
* : heap
* : stack
* _ROMBASE
- * : linuxbios text
+ * : coreboot text
* : readonly text
*/
/*
*/
TARGET(binary)
-INPUT(linuxbios_ram.rom)
+INPUT(coreboot_ram.rom)
SECTIONS
{
. = _ROMBASE;
.ram . : {
_ram = . ;
- linuxbios_ram.rom(*)
+ coreboot_ram.rom(*)
_eram = . ;
}
-INPUT(linuxbios_apc.rom)
+INPUT(coreboot_apc.rom)
SECTIONS
{
.apcrom . : {
_apcrom = .;
- linuxbios_apc.rom(*)
+ coreboot_apc.rom(*)
_eapcrom = .;
}
_iseg_apc = DCACHE_RAM_BASE;
* : heap
* : stack
* _ROMBASE
- * : linuxbios text
+ * : coreboot text
* : readonly text
*/
/*
* : heap
* : stack
* _ROMBASE
- * : linuxbios text
+ * : coreboot text
* : readonly text
*/
/*
*/
TARGET(binary)
-INPUT(linuxbios_ram.rom)
+INPUT(coreboot_ram.rom)
SECTIONS
{
. = _ROMBASE;
.ram . : {
_ram = . ;
- linuxbios_ram.rom(*)
+ coreboot_ram.rom(*)
_eram = . ;
}
.data
- /* This is the gdt for GCC part of LinuxBIOS.
- * It is different from the gdt in ROMCC/ASM part of LinuxBIOS
+ /* This is the gdt for GCC part of coreboot.
+ * It is different from the gdt in ROMCC/ASM part of coreboot
* which is defined in entry32.inc */
gdt:
/* selgdt 0, unused */
#endif /* CONFIG_USE_PRINTK_IN_CAR */
-#ifndef LINUXBIOS_EXTRA_VERSION
-#define LINUXBIOS_EXTRA_VERSION ""
+#ifndef COREBOOT_EXTRA_VERSION
+#define COREBOOT_EXTRA_VERSION ""
#endif
static void console_init(void)
{
static const char console_test[] =
- "\r\n\r\nLinuxBIOS-"
- LINUXBIOS_VERSION
- LINUXBIOS_EXTRA_VERSION
+ "\r\n\r\ncoreboot-"
+ COREBOOT_VERSION
+ COREBOOT_EXTRA_VERSION
" "
- LINUXBIOS_BUILD
+ COREBOOT_BUILD
" starting...\r\n";
print_info(console_test);
}
ldscript init/ldscript.lb
-makerule linuxbios.rom
- depends "linuxbios"
+makerule coreboot.rom
+ depends "coreboot"
action "cp $< $@"
end
*/
flush_dcache();
- /* On ppc we don't currently support loading over LinuxBIOS.
+ /* On ppc we don't currently support loading over coreboot.
* So ignore the buffer.
*/
uint32_t tag;
const uint8_t *string;
} strings[] = {
- { LB_TAG_VERSION, linuxbios_version, },
- { LB_TAG_EXTRA_VERSION, linuxbios_extra_version, },
- { LB_TAG_BUILD, linuxbios_build, },
- { LB_TAG_COMPILE_TIME, linuxbios_compile_time, },
- { LB_TAG_COMPILE_BY, linuxbios_compile_by, },
- { LB_TAG_COMPILE_HOST, linuxbios_compile_host, },
- { LB_TAG_COMPILE_DOMAIN, linuxbios_compile_domain, },
- { LB_TAG_COMPILER, linuxbios_compiler, },
- { LB_TAG_LINKER, linuxbios_linker, },
- { LB_TAG_ASSEMBLER, linuxbios_assembler, },
+ { LB_TAG_VERSION, coreboot_version, },
+ { LB_TAG_EXTRA_VERSION, coreboot_extra_version, },
+ { LB_TAG_BUILD, coreboot_build, },
+ { LB_TAG_COMPILE_TIME, coreboot_compile_time, },
+ { LB_TAG_COMPILE_BY, coreboot_compile_by, },
+ { LB_TAG_COMPILE_HOST, coreboot_compile_host, },
+ { LB_TAG_COMPILE_DOMAIN, coreboot_compile_domain, },
+ { LB_TAG_COMPILER, coreboot_compiler, },
+ { LB_TAG_LINKER, coreboot_linker, },
+ { LB_TAG_ASSEMBLER, coreboot_assembler, },
};
unsigned int i;
for(i = 0; i < sizeof(strings)/sizeof(strings[0]); i++) {
head->table_checksum = compute_ip_checksum(first_rec, head->table_bytes);
head->header_checksum = 0;
head->header_checksum = compute_ip_checksum(head, sizeof(*head));
- printk_debug("Wrote linuxbios table at: %p - %p checksum %lx\n",
+ printk_debug("Wrote coreboot table at: %p - %p checksum %lx\n",
head, rec, head->table_checksum);
return (unsigned long)rec;
}
lb_cleanup_memory_ranges(mem);
}
-/* Routines to extract part so the linuxBIOS table or
- * information from the linuxBIOS table after we have written it.
+/* Routines to extract part so the coreboot table or
+ * information from the coreboot table after we have written it.
* Currently get_lb_mem relies on a global we can change the
* implementaiton.
*/
return mem;
}
-unsigned long write_linuxbios_table(
+unsigned long write_coreboot_table(
unsigned long low_table_start, unsigned long low_table_end,
unsigned long rom_table_start, unsigned long rom_table_end)
{
/* Note:
* I assume that there is always memory at immediately after
- * the low_table_end. This means that after I setup the linuxbios table.
+ * the low_table_end. This means that after I setup the coreboot table.
* I can trivially fixup the reserved memory ranges to hold the correct
- * size of the linuxbios table.
+ * size of the coreboot table.
*/
/* Record our motheboard */
-#ifndef LINUXBIOS_TABLE_H
-#define LINUXBIOS_TABLE_H
+#ifndef COREBOOT_TABLE_H
+#define COREBOOT_TABLE_H
#include <boot/linuxbios_tables.h>
struct mem_range;
-/* This file holds function prototypes for building the linuxbios table. */
-unsigned long write_linuxbios_table(
+/* This file holds function prototypes for building the coreboot table. */
+unsigned long write_coreboot_table(
unsigned long low_table_start, unsigned long low_table_end,
unsigned long rom_table_start, unsigned long rom_table_end);
struct lb_mainboard *lb_mainboard(struct lb_header *header);
unsigned long lb_table_fini(struct lb_header *header);
-/* Routines to extract part so the linuxBIOS table or information
- * from the linuxBIOS table.
+/* Routines to extract part so the coreboot table or information
+ * from the coreboot table.
*/
struct lb_memory *get_lb_mem(void);
extern struct cmos_option_table option_table;
-#endif /* LINUXBIOS_TABLE_H */
+#endif /* COREBOOT_TABLE_H */
low_table_start = 0;
low_table_end = 16;
- /* The linuxbios table must be in 0-4K or 960K-1M */
- write_linuxbios_table(
+ /* The coreboot table must be in 0-4K or 960K-1M */
+ write_coreboot_table(
low_table_start, low_table_end,
rom_table_start, rom_table_end);
* _RESET : reset vector (may be at top of ROM)
* _EXCEPTIONS_VECTORS : exception table
*
- * _ROMSTART : linuxbios text
+ * _ROMSTART : coreboot text
* : payload text
*
* _RAMBASE : address to copy payload
ENTRY(_start)
TARGET(binary)
-INPUT(linuxbios_ram.rom)
+INPUT(coreboot_ram.rom)
SECTIONS
{
/*
}
/*
- * Absolute location of LinuxBIOS initialization code in ROM.
+ * Absolute location of coreboot initialization code in ROM.
*/
. = _ROMSTART;
.rom . : {
*(.text);
*(.rom.data);
*(.rodata);
- *(EXCLUDE_FILE(linuxbios_ram.rom) .data);
+ *(EXCLUDE_FILE(coreboot_ram.rom) .data);
. = ALIGN(16);
_erom = .;
}
_elrom = LOADADDR(.rom) + SIZEOF(.rom);
/*
- * Ram is the LinuxBIOS code that runs from RAM.
+ * Ram is the coreboot code that runs from RAM.
*/
.ram . : {
_ram = . ;
- linuxbios_ram.rom(*)
+ coreboot_ram.rom(*)
_eram = . ;
}
/*
- * Absolute location of where LinuxBIOS will be relocated in RAM.
+ * Absolute location of where coreboot will be relocated in RAM.
*/
_iseg = _RAMBASE;
_eiseg = _iseg + SIZEOF(.ram);
#include <stdlib.h>
#include <string.h>
-/* Maximum physical address we can use for the linuxBIOS bounce buffer.
+/* Maximum physical address we can use for the coreboot bounce buffer.
*/
#ifndef MAX_ADDR
#define MAX_ADDR -1UL
* a machine, and implementing general relocation is hard.
*
* The solution:
- * - Allocate a buffer twice the size of the linuxBIOS image.
- * - Anything that would overwrite linuxBIOS copy into the lower half of
+ * - Allocate a buffer twice the size of the coreboot image.
+ * - Anything that would overwrite coreboot copy into the lower half of
* the buffer.
- * - After loading an ELF image copy linuxBIOS to the upper half of the
+ * - After loading an ELF image copy coreboot to the upper half of the
* buffer.
* - Then jump to the loaded image.
*
* Benefits:
* - Nearly arbitrary standalone executables can be loaded.
- * - LinuxBIOS is preserved, so it can be returned to.
+ * - Coreboot is preserved, so it can be returned to.
* - The implementation is still relatively simple,
* and much simpler then the general case implemented in kexec.
*
unsigned long buffer;
int i;
lb_size = (unsigned long)(&_eram_seg - &_ram_seg);
- /* Double linuxBIOS size so I have somewhere to place a copy to return to */
+ /* Double coreboot size so I have somewhere to place a copy to return to */
lb_size = lb_size + lb_size;
mem_entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]);
buffer = 0;
static void relocate_segment(unsigned long buffer, struct segment *seg)
{
- /* Modify all segments that want to load onto linuxBIOS
+ /* Modify all segments that want to load onto coreboot
* to load onto the bounce buffer instead.
*/
unsigned long lb_start = (unsigned long)&_ram_seg;
start = seg->s_addr;
middle = start + seg->s_filesz;
end = start + seg->s_memsz;
- /* I don't conflict with linuxBIOS so get out of here */
+ /* I don't conflict with coreboot so get out of here */
if ((end <= lb_start) || (start >= lb_end))
return;
start, middle, end);
/* Slice off a piece at the beginning
- * that doesn't conflict with linuxBIOS.
+ * that doesn't conflict with coreboot.
*/
if (start < lb_start) {
struct segment *new;
}
/* Slice off a piece at the end
- * that doesn't conflict with linuxBIOS
+ * that doesn't conflict with coreboot
*/
if (end > lb_end) {
unsigned long len = lb_end - start;
struct verify_callback *cb_chain;
unsigned long bounce_buffer;
- /* Find a bounce buffer so I can load to linuxBIOS's current location */
+ /* Find a bounce buffer so I can load to coreboot's current location */
bounce_buffer = get_bounce_buffer(mem);
if (!bounce_buffer) {
printk_err("Could not find a bounce buffer...\n");
* Copyright (C) 2003 by SONE Takeshi <ts1@tsn.or.jp> and others.
* This program is licensed under the terms of GNU General Public License.
*
- * Modified for LinuxBIOS by Greg Watson <gwatson@lanl.gov>
+ * Modified for coreboot by Greg Watson <gwatson@lanl.gov>
*/
#include <console/console.h>
/*
- * C Bootstrap code for the LinuxBIOS
+ * C Bootstrap code for the coreboot
*/
#include <boot/elf.h>
/**
- * @brief Main function of the DRAM part of LinuxBIOS.
+ * @brief Main function of the DRAM part of coreboot.
*
- * LinuxBIOS is divided into Pre-DRAM part and DRAM part.
+ * Coreboot is divided into Pre-DRAM part and DRAM part.
*
*
* Device Enumeration:
post_code(0x39);
- printk_notice("LinuxBIOS-%s%s %s %s...\n",
- linuxbios_version, linuxbios_extra_version, linuxbios_build,
+ printk_notice("coreboot-%s%s %s %s...\n",
+ coreboot_version, coreboot_extra_version, coreboot_build,
(boot_complete)?"rebooting":"booting");
post_code(0x40);
# action "perl -e 'foreach $$var (split(\" \", $$ENV{VARIABLES})) { if ($$ENV{$$var} =~ m/^(0x[0-9a-fA-F]+|0[0-7]+|[0-9]+)$$/) { print \"$$var = $$ENV{$$var};\n\"; }}' > $@"
#end
-makerule linuxbios.strip
- depends "linuxbios"
- action "$(OBJCOPY) -O binary linuxbios linuxbios.strip"
+makerule coreboot.strip
+ depends "coreboot"
+ action "$(OBJCOPY) -O binary coreboot coreboot.strip"
end
-makerule linuxbios.a
+makerule coreboot.a
depends "$(OBJECTS)"
- action "rm -f linuxbios.a"
- action "ar cr linuxbios.a $(OBJECTS)"
+ action "rm -f coreboot.a"
+ action "ar cr coreboot.a $(OBJECTS)"
end
-makerule linuxbios_ram.o
- depends "$(DRIVER) linuxbios.a $(LIBGCC_FILE_NAME)"
- action "$(CC) -nostdlib -r -o $@ c_start.o $(DRIVER) linuxbios.a $(LIBGCC_FILE_NAME)"
+makerule coreboot_ram.o
+ depends "$(DRIVER) coreboot.a $(LIBGCC_FILE_NAME)"
+ action "$(CC) -nostdlib -r -o $@ c_start.o $(DRIVER) coreboot.a $(LIBGCC_FILE_NAME)"
end
-makerule linuxbios_ram
- depends "linuxbios_ram.o $(TOP)/src/config/linuxbios_ram.ld ldoptions"
- action "$(CC) -nostdlib -nostartfiles -static -o $@ -T $(TOP)/src/config/linuxbios_ram.ld linuxbios_ram.o"
- action "$(CROSS_COMPILE)nm -n linuxbios_ram | sort > linuxbios_ram.map"
+makerule coreboot_ram
+ depends "coreboot_ram.o $(TOP)/src/config/linuxbios_ram.ld ldoptions"
+ action "$(CC) -nostdlib -nostartfiles -static -o $@ -T $(TOP)/src/config/linuxbios_ram.ld coreboot_ram.o"
+ action "$(CROSS_COMPILE)nm -n coreboot_ram | sort > coreboot_ram.map"
end
##
-## By default compress the part of linuxbios that runs from RAM
+## By default compress the part of coreboot that runs from RAM
##
-makedefine LINUXBIOS_RAM-$(CONFIG_COMPRESS):=linuxbios_ram.nrv2b
-makedefine LINUXBIOS_RAM-$(CONFIG_UNCOMPRESSED):=linuxbios_ram.bin
+makedefine COREBOOT_RAM-$(CONFIG_COMPRESS):=coreboot_ram.nrv2b
+makedefine COREBOOT_RAM-$(CONFIG_UNCOMPRESSED):=coreboot_ram.bin
-makerule linuxbios_ram.bin
- depends "linuxbios_ram"
+makerule coreboot_ram.bin
+ depends "coreboot_ram"
action "$(OBJCOPY) -O binary $< $@"
end
-makerule linuxbios_ram.nrv2b
- depends "linuxbios_ram.bin nrv2b"
+makerule coreboot_ram.nrv2b
+ depends "coreboot_ram.bin nrv2b"
action "./nrv2b e $< $@"
end
-makerule linuxbios_ram.rom
- depends "$(LINUXBIOS_RAM-1)"
- action "cp $(LINUXBIOS_RAM-1) linuxbios_ram.rom"
+makerule coreboot_ram.rom
+ depends "$(COREBOOT_RAM-1)"
+ action "cp $(COREBOOT_RAM-1) coreboot_ram.rom"
end
-makedefine LINUXBIOS_APC:=
+makedefine COREBOOT_APC:=
if CONFIG_AP_CODE_IN_CAR
#for ap code in cache
- makerule linuxbios_apc.a
+ makerule coreboot_apc.a
depends "apc_auto.o"
- action "rm -f linuxbios_apc.a"
- action "ar cr linuxbios_apc.a apc_auto.o"
+ action "rm -f coreboot_apc.a"
+ action "ar cr coreboot_apc.a apc_auto.o"
end
- makerule linuxbios_apc.o
- depends "linuxbios_apc.a c_start.o $(LIBGCC_FILE_NAME)"
- action "$(CC) -nostdlib -r -o $@ c_start.o linuxbios_apc.a $(LIBGCC_FILE_NAME)"
+ makerule coreboot_apc.o
+ depends "coreboot_apc.a c_start.o $(LIBGCC_FILE_NAME)"
+ action "$(CC) -nostdlib -r -o $@ c_start.o coreboot_apc.a $(LIBGCC_FILE_NAME)"
end
- makerule linuxbios_apc
- depends "linuxbios_apc.o $(TOP)/src/config/linuxbios_apc.ld ldoptions"
- action "$(CC) -nostdlib -nostartfiles -static -o $@ -T $(TOP)/src/config/linuxbios_apc.ld linuxbios_apc.o"
- action "$(CROSS_COMPILE)nm -n linuxbios_apc | sort > linuxbios_apc.map"
+ makerule coreboot_apc
+ depends "coreboot_apc.o $(TOP)/src/config/linuxbios_apc.ld ldoptions"
+ action "$(CC) -nostdlib -nostartfiles -static -o $@ -T $(TOP)/src/config/linuxbios_apc.ld coreboot_apc.o"
+ action "$(CROSS_COMPILE)nm -n coreboot_apc | sort > coreboot_apc.map"
end
##
- ## By default compress the part of linuxbios that runs from cache as ram
+ ## By default compress the part of coreboot that runs from cache as ram
##
- makedefine LINUXBIOS_APC-$(CONFIG_COMPRESS):=linuxbios_apc.nrv2b
- makedefine LINUXBIOS_APC-$(CONFIG_UNCOMPRESSED):=linuxbios_apc.bin
+ makedefine COREBOOT_APC-$(CONFIG_COMPRESS):=coreboot_apc.nrv2b
+ makedefine COREBOOT_APC-$(CONFIG_UNCOMPRESSED):=coreboot_apc.bin
- makerule linuxbios_apc.bin
- depends "linuxbios_apc"
+ makerule coreboot_apc.bin
+ depends "coreboot_apc"
action "$(OBJCOPY) -O binary $< $@"
end
- makerule linuxbios_apc.nrv2b
- depends "linuxbios_apc.bin nrv2b"
+ makerule coreboot_apc.nrv2b
+ depends "coreboot_apc.bin nrv2b"
action "./nrv2b e $< $@"
end
- makerule linuxbios_apc.rom
- depends "$(LINUXBIOS_APC-1)"
- action "cp $(LINUXBIOS_APC-1) linuxbios_apc.rom"
+ makerule coreboot_apc.rom
+ depends "$(COREBOOT_APC-1)"
+ action "cp $(COREBOOT_APC-1) coreboot_apc.rom"
end
- makedefine LINUXBIOS_APC:=linuxbios_apc.rom
+ makedefine COREBOOT_APC:=coreboot_apc.rom
end
-makedefine LINUXBIOS_RAM_ROM:=linuxbios_ram.rom
+makedefine COREBOOT_RAM_ROM:=coreboot_ram.rom
-makerule linuxbios
- depends "crt0.o $(INIT-OBJECTS) $(LINUXBIOS_APC) $(LINUXBIOS_RAM_ROM) ldscript.ld"
+makerule coreboot
+ depends "crt0.o $(INIT-OBJECTS) $(COREBOOT_APC) $(COREBOOT_RAM_ROM) ldscript.ld"
action "$(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o $(INIT-OBJECTS)"
- action "$(CROSS_COMPILE)nm -n linuxbios | sort > linuxbios.map"
+ action "$(CROSS_COMPILE)nm -n coreboot | sort > coreboot.map"
end
#makerule crt0.S
depends "$(SOURCES)"
action "ctags $(SOURCES)"
end
-makerule LinuxBIOSDoc.config
- depends "$(TOP)/src/config/LinuxBIOSDoc.config"
- action "cat $(TOP)/src/config/LinuxBIOSDoc.config > LinuxBIOSDoc.config"
- action "echo 'INPUT=$(SOURCES)' >> LinuxBIOSDoc.config"
+makerule corebootDoc.config
+ depends "$(TOP)/src/config/corebootDoc.config"
+ action "cat $(TOP)/src/config/corebootDoc.config > corebootDoc.config"
+ action "echo 'INPUT=$(SOURCES)' >> corebootDoc.config"
end
makerule documentation
- depends "LinuxBIOSDoc.config"
- action "doxygen LinuxBIOSDoc.config"
+ depends "corebootDoc.config"
+ action "doxygen corebootDoc.config"
end
makerule ./romcc
end
makerule clean
- action "rm -f linuxbios.* *~"
- action "rm -f linuxbios"
+ action "rm -f coreboot.* *~"
+ action "rm -f coreboot"
action "rm -f ldscript.ld"
action "rm -f a.out *.s *.l *.o *.E *.inc"
action "rm -f TAGS tags romcc*"
- action "rm -f docipl buildrom* chips.c *chip.c linuxbios_apc* linuxbios_ram* linuxbios_pay*"
+ action "rm -f docipl buildrom* chips.c *chip.c coreboot_apc* coreboot_ram* coreboot_pay*"
action "rm -f build_opt_tbl* nrv2b* option_table.c crt0.S"
end
#---------------------------------------------------------------------------
# Project related configuration options
#---------------------------------------------------------------------------
-PROJECT_NAME = LinuxBIOS
+PROJECT_NAME = coreboot
PROJECT_NUMBER =
OUTPUT_DIRECTORY = .
CREATE_SUBDIRS = NO
#######################################################
#
-# Main options file for LinuxBIOS
+# Main options file for coreboot
#
# Each option used by a part must be defined in
# this file. The format for options is:
export always
comment "Objcopy command"
end
-define LINUXBIOS_VERSION
+define COREBOOT_VERSION
default "2.0.0"
export always
format "\"%s\""
- comment "LinuxBIOS version"
+ comment "coreboot version"
end
-define LINUXBIOS_EXTRA_VERSION
+define COREBOOT_EXTRA_VERSION
default ""
export used
format "\"%s\""
- comment "LinuxBIOS extra version"
+ comment "coreboot extra version"
end
-define LINUXBIOS_BUILD
+define COREBOOT_BUILD
default "$(shell date)"
export always
format "\"%s\""
comment "Build date"
end
-define LINUXBIOS_COMPILE_TIME
+define COREBOOT_COMPILE_TIME
default "$(shell date +%T)"
export always
format "\"%s\""
comment "Build time"
end
-define LINUXBIOS_COMPILE_BY
+define COREBOOT_COMPILE_BY
default "$(shell whoami)"
export always
format "\"%s\""
comment "Who build this image"
end
-define LINUXBIOS_COMPILE_HOST
+define COREBOOT_COMPILE_HOST
default "$(shell hostname)"
export always
format "\"%s\""
comment "Build host"
end
-define LINUXBIOS_COMPILE_DOMAIN
+define COREBOOT_COMPILE_DOMAIN
default "$(shell dnsdomainname)"
export always
format "\"%s\""
comment "Build domain name"
end
-define LINUXBIOS_COMPILER
+define COREBOOT_COMPILER
default "$(shell $(CC) $(CFLAGS) -v 2>&1 | tail -n 1)"
export always
format "\"%s\""
comment "Build compiler"
end
-define LINUXBIOS_LINKER
+define COREBOOT_LINKER
default "$(shell $(CC) -Wl,--version 2>&1 | grep version | tail -n 1)"
export always
format "\"%s\""
comment "Build linker"
end
-define LINUXBIOS_ASSEMBLER
+define COREBOOT_ASSEMBLER
default "$(shell touch dummy.s ; $(CC) -c -Wa,-v dummy.s 2>&1; rm -f dummy.s dummy.o )"
export always
format "\"%s\""
default {PAYLOAD_SIZE}
format "0x%x"
export always
- comment "Base address of LinuxBIOS in ROM"
+ comment "Base address of coreboot in ROM"
end
define _ROMSTART
default none
format "0x%x"
export used
- comment "Start address of LinuxBIOS in ROM"
+ comment "Start address of coreboot in ROM"
end
define _RESET
default {_ROMBASE}
default none
format "0x%x"
export always
- comment "Base address of LinuxBIOS in RAM"
+ comment "Base address of coreboot in RAM"
end
define _RAMSTART
default none
format "0x%x"
export used
- comment "Start address of LinuxBIOS in RAM"
+ comment "Start address of coreboot in RAM"
end
define USE_DCACHE_RAM
default 0
define CONFIG_AP_CODE_IN_CAR
default 0
export always
- comment "will copy linuxbios_apc to AP cache ane execute in AP"
+ comment "will copy coreboot_apc to AP cache ane execute in AP"
end
define MEM_TRAIN_SEQ
default 0
default 0
format "0x%x"
export used
- comment "Start address of area to cache during LinuxBIOS execution directly from ROM"
+ comment "Start address of area to cache during coreboot execution directly from ROM"
end
define XIP_ROM_SIZE
default 0
format "0x%x"
export used
- comment "Size of area to cache during LinuxBIOS execution directly from ROM"
+ comment "Size of area to cache during coreboot execution directly from ROM"
end
define CONFIG_COMPRESS
default 1
default 49
format "%d"
export always
- comment "First CMOS byte to use for LinuxBIOS options"
+ comment "First CMOS byte to use for coreboot options"
end
define LB_CKS_RANGE_END
default 125
format "%d"
export always
- comment "Last CMOS byte to use for LinuxBIOS options"
+ comment "Last CMOS byte to use for coreboot options"
end
define LB_CKS_LOC
default 126
# The PROJECT_NAME tag is a single word (or a sequence of words surrounded
# by quotes) that should identify the project.
-PROJECT_NAME = "LinuxBIOS"
+PROJECT_NAME = "coreboot"
# The PROJECT_NUMBER tag can be used to enter a project or revision number.
# This could be handy for archiving the generated documentation or
/*
* Written by Johan Rydberg, based on work by Daniel Kahlin.
* Rewritten by Eric Biederman
- * 2005.12 yhlu add linuxbios_ram cross the vga font buffer handling
+ * 2005.12 yhlu add coreboot_ram cross the vga font buffer handling
* 2006.05 yhlu tailed it to use it for AP code in cache
*/
/*
}
_eheap = .;
/* The ram segment
- * This is all address of the memory resident copy of linuxBIOS.
+ * This is all address of the memory resident copy of coreboot.
*/
_ram_seg = _text;
_eram_seg = _eheap;
- _bogus = ASSERT( ( _eram_seg <= ((DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE))) , "linuxbios_apc is too big");
+ _bogus = ASSERT( ( _eram_seg <= ((DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE))) , "coreboot_apc is too big");
/DISCARD/ : {
*(.comment)
/*
* Written by Johan Rydberg, based on work by Daniel Kahlin.
* Rewritten by Eric Biederman
- * 2005.12 yhlu add linuxbios_ram cross the vga font buffer handling
+ * 2005.12 yhlu add coreboot_ram cross the vga font buffer handling
*/
/*
* We use ELF as output format. So that we can
/*
* kevinh/Ispiri - Added an align, because the objcopy tool
* incorrectly converts sections that are not long word aligned.
- * This breaksthe linuxbios.strip target.
+ * This breaks the coreboot.strip target.
*/
. = ALIGN(4);
}
_eheap = .;
/* The ram segment
- * This is all address of the memory resident copy of linuxBIOS.
+ * This is all address of the memory resident copy of coreboot.
*/
_ram_seg = _text;
_eram_seg = _eheap;
*
* Benjamin Herrenschmidt <benh@kernel.crashing.org>
*
- * move to LinuxBIOS by LYH yhlu@tyan.com
+ * move to coreboot by LYH yhlu@tyan.com
*/
#if 0
uint8_t *src, *dst;
unsigned long ilen, olen;
- print_debug("Copying LinuxBIOS to RAM.\r\n");
+ print_debug("Copying coreboot to RAM.\r\n");
#if !CONFIG_COMPRESS
__asm__ volatile (
print_debug_cp_run("linxbios_ram.bin length = ", olen);
- print_debug("Jumping to LinuxBIOS.\r\n");
+ print_debug("Jumping to coreboot.\r\n");
__asm__ volatile (
"xorl %ebp, %ebp\n\t" /* cpu_reset for hardwaremain dummy */
uint8_t *src, *dst;
unsigned long ilen, olen;
-// print_debug("Copying LinuxBIOS AP code to CAR.\r\n");
+// print_debug("Copying coreboot AP code to CAR.\r\n");
#if !CONFIG_COMPRESS
__asm__ volatile (
// print_debug_cp_run("linxbios_apc.bin length = ", olen);
-// print_debug("Jumping to LinuxBIOS AP code in CAR.\r\n");
+// print_debug("Jumping to coreboot AP code in CAR.\r\n");
__asm__ volatile (
"movl %0, %%ebp\n\t" /* cpu_reset for hardwaremain dummy */
"wrmsr\n\t"
#endif
- /* disable fixed mtrr from now on, it will be enabled by linuxbios_ram again*/
+ /* disable fixed mtrr from now on, it will be enabled by coreboot_ram again*/
"movl $0xC0010010, %ecx\n\t"
// "movl $SYSCFG_MSR, %ecx\n\t"
"rdmsr\n\t"
// wait for ap memory to trained
// wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c
#endif
- /*copy and execute linuxbios_ram */
+ /*copy and execute coreboot_ram */
copy_and_run();
/* We will not return */
/* what a mess this uncompress thing is. I am not at all happy about how this
* was done, but can't fix it yet. RGM
*/
-#warning "Fix the uncompress once linuxbios knows how to do it"
+#warning "Fix the uncompress once coreboot knows how to do it"
#include "../lib/nrv2b.c"
/* vsmsetup.c derived from vgabios.c. Derived from: */
*--------------------------------------------------------------------*/
/* Modified to be a self sufficient plug in so that it can be used
- without reliance on other parts of core Linuxbios
+ without reliance on other parts of core coreboot
(C) 2005 Nick.Barker9@btinternet.com
Used initially for epia-m where there are problems getting the bios
// that simplifies a lot of things ...
// we'll just push all the registers on the stack as longwords,
// and pop to protected mode.
-// second, since this only ever runs as part of linuxbios,
+// second, since this only ever runs as part of coreboot,
// we know all the segment register values -- so we don't save any.
// keep the handler that calls things small. It can do a call to
-// more complex code in linuxbios itself. This helps a lot as we don't
+// more complex code in coreboot itself. This helps a lot as we don't
// have to do address fixup in this little stub, and calls are absolute
// so the handler is relocatable.
void handler(void)
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#define LX_STACK_BASE DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as LinuxBIOS normal stack */
+#define LX_STACK_BASE DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as coreboot normal stack */
#define LX_STACK_END LX_STACK_BASE+(DCACHE_RAM_SIZE-1)
#define LX_NUM_CACHELINES 0x080 /* there are 128lines per way */
cld /* clear direction flag */
- /* copy linuxBIOS from it's initial load location to
+ /* copy coreboot from it's initial load location to
* the location it is compiled to run at.
* Normally this is copying from FLASH ROM to RAM.
*/
#if defined(CONSOLE_DEBUG_TX_STRING) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
.section ".rom.data"
-str_copying_to_ram: .string "Copying LinuxBIOS to ram.\r\n"
-str_pre_main: .string "Jumping to LinuxBIOS.\r\n"
+str_copying_to_ram: .string "Copying coreboot to ram.\r\n"
+str_pre_main: .string "Jumping to coreboot.\r\n"
.previous
#endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */
*--------------------------------------------------------------------*/
/* Modified to be a self sufficient plug in so that it can be used
- without reliance on other parts of core Linuxbios
+ without reliance on other parts of core coreboot
(C) 2005 Nick.Barker9@btinternet.com
Used initially for epia-m where there are problems getting the bios
// that simplifies a lot of things ...
// we'll just push all the registers on the stack as longwords,
// and pop to protected mode.
-// second, since this only ever runs as part of linuxbios,
+// second, since this only ever runs as part of coreboot,
// we know all the segment register values -- so we don't save any.
// keep the handler that calls things small. It can do a call to
-// more complex code in linuxbios itself. This helps a lot as we don't
+// more complex code in coreboot itself. This helps a lot as we don't
// have to do address fixup in this little stub, and calls are absolute
// so the handler is relocatable.
void handler(void)
/* these are ENDING addresses, not sizes.
* if there is memory in this slot, then reg will be > rambits.
* So we just take the max, that gives us total.
- * We take the highest one to cover for once and future linuxbios
+ * We take the highest one to cover for once and future coreboot
* bugs. We warn about bugs.
*/
if (reg > rambits)
/* these are ENDING addresses, not sizes.
* if there is memory in this slot, then reg will be > rambits.
* So we just take the max, that gives us total.
- * We take the highest one to cover for once and future linuxbios
+ * We take the highest one to cover for once and future coreboot
* bugs. We warn about bugs.
*/
if (reg > rambits)
## Use cache ram for initial setup
##
default USE_DCACHE_RAM=1
-## Set dcache ram above linuxbios image
+## Set dcache ram above coreboot image
default DCACHE_RAM_BASE=_RAMBASE+0x100000
## Dcache size is 32Kb
default DCACHE_RAM_SIZE=0x8000
/*
* The aim of this code is to bring the machine from power-on to the point
- * where we can jump to the the main LinuxBIOS entry point hardwaremain()
+ * where we can jump to the the main coreboot entry point hardwaremain()
* which is written in C.
*
* At power-on, we have no RAM, a memory-mapped I/O space, and we are executing
isync
/*
- * Clear segment registers (LinuxBIOS doesn't use these)
+ * Clear segment registers (coreboot doesn't use these)
*/
mtsr 0, r0
isync
## PPC4XX always uses cache ram for initial setup
##
default USE_DCACHE_RAM=1
-## Set dcache ram above linuxbios image
+## Set dcache ram above coreboot image
default DCACHE_RAM_BASE=_RAMBASE+0x100000
## Dcache size is 16Kb
default DCACHE_RAM_SIZE=16384
## PPC7XX always uses cache ram for initial setup
##
default USE_DCACHE_RAM=1
-## Set dcache ram above linuxbios image
+## Set dcache ram above coreboot image
default DCACHE_RAM_BASE=_RAMBASE+0x100000
## Dcache size is 16Kb
default DCACHE_RAM_SIZE=16384
/*
* The aim of this code is to bring the machine from power-on to the point
- * where we can jump to the the main LinuxBIOS entry point hardwaremain()
+ * where we can jump to the the main coreboot entry point hardwaremain()
* which is written in C.
*
* At power-on, we have no RAM, a memory-mapped I/O space, and we are executing
isync
/*
- * Clear segment registers (LinuxBIOS doesn't use these)
+ * Clear segment registers (coreboot doesn't use these)
*/
li r3, 15
1: mtsrin r3, r0
-/* For starting linuxBIOS in protected mode */
+/* For starting coreboot in protected mode */
#include <arch/rom_segs.h>
.align 4
.globl gdtptr
- /* This is the gdt for ROMCC/ASM part of LinuxBIOS.
- * It is different from the gdt in GCC part of LinuxBIOS
+ /* This is the gdt for ROMCC/ASM part of coreboot.
+ * It is different from the gdt in GCC part of coreboot
* which is defined in c_start.S */
gdt:
gdtptr:
unsigned long dst_len;
unsigned long ilen, olen;
- print_debug("Copying LinuxBIOS to RAM.\r\n");
+ print_debug("Copying coreboot to RAM.\r\n");
#if !CONFIG_COMPRESS
__asm__ volatile (
#else
print_debug("linxbios_ram.bin length = "); print_debug_hex32(olen); print_debug("\r\n");
#endif
- print_debug("Jumping to LinuxBIOS.\r\n");
+ print_debug("Jumping to coreboot.\r\n");
if(cpu_reset == 1 ) {
__asm__ volatile (
/*
- 2005.12 yhlu add linuxbios_ram cross the vga font buffer handling
+ 2005.12 yhlu add coreboot_ram cross the vga font buffer handling
2005.12 yhlu add _RAMBASE above 1M support for SMP
*/
return 1;
}
-/* Number of cpus that are currently running in linuxbios */
+/* Number of cpus that are currently running in coreboot */
static atomic_t active_cpus = ATOMIC_INIT(1);
/* start_cpu_lock covers last_cpu_index and secondary_stack.
/*
- 2005.12 yhlu add linuxbios_ram cross the vga font buffer handling
+ 2005.12 yhlu add coreboot_ram cross the vga font buffer handling
*/
#include <console/console.h>
#include <x86emu/regs.h>
#include "debug.h"
#include "prim_ops.h"
-#ifdef LINUXBIOS_VERSION
+#ifdef COREBOOT_VERSION
#include "arch/io.h"
#else
#include <sys/io.h>
* stevel@mvista.com or source@mvista.com
* Copyright (C) 2004 Tyan Computer.
* Auther: Yinghai Lu yhlu@tyan.com
- * move to LinuxBIOS
+ * move to coreboot
* This code is distributed without warranty under the GPL v2 (see COPYING) *
*/
#include <delay.h>
in your MB targets Config.lb, afer romimage "normal"
3. create you vgabios.bin under normal bios and put that in dir that targets Config residues.
# dd if=/dev/mem of=atix.rom skip=1536 count=96
- 4. after build linuxbios.rom
- # cat ../atix.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > linuxbios.rom
+ 4. after build coreboot.rom
+ # cat ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > coreboot.rom
or use nsxv to build you image
# time ./nsxv s2850
tail -n 15 "$LBROOT/x_m.txt"
exit
fi
-cat ../atix.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > "$LBROOT/rom/"$MBMODEL"_linuxbios.rom"
-cp -f "$LBROOT/rom/"$MBMODEL"_linuxbios.rom" /home/yhlu/
+cat ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > "$LBROOT/rom/"$MBMODEL"_coreboot.rom"
+cp -f "$LBROOT/rom/"$MBMODEL"_coreboot.rom" /home/yhlu/
date
struct lb_memory;
extern int elfboot(struct lb_memory *mem);
-#define FIRMWARE_TYPE "LinuxBIOS"
+#define FIRMWARE_TYPE "coreboot"
#define BOOTLOADER "elfboot"
#define BOOTLOADER_VERSION "1.3"
-#ifndef LINUXBIOS_TABLES_H
-#define LINUXBIOS_TABLES_H
+#ifndef COREBOOT_TABLES_H
+#define COREBOOT_TABLES_H
#include <stdint.h>
-/* The linuxbios table information is for conveying information
+/* The coreboot table information is for conveying information
* from the firmware to the loaded OS image. Primarily this
* is expected to be information that cannot be discovered by
* other means, such as quering the hardware directly.
* table entries and be backwards compatible, but it is not required.
*/
-/* Since LinuxBIOS is usually compiled 32bit, gcc will align 64bit
- * types to 32bit boundaries. If the LinuxBIOS table is dumped on a
+/* Since coreboot is usually compiled 32bit, gcc will align 64bit
+ * types to 32bit boundaries. If the coreboot table is dumped on a
* 64bit system, a uint64_t would be aligned to 64bit boundaries,
* breaking the table format.
*
- * lb_uint64 will keep 64bit LinuxBIOS table values aligned to 32bit
+ * lb_uint64 will keep 64bit coreboot table values aligned to 32bit
* to ensure compatibility. They can be accessed with the two functions
* below: unpack_lb64() and pack_lb64()
*
-#endif /* LINUXBIOS_TABLES_H */
+#endif /* COREBOOT_TABLES_H */
*
* Written by Benjamin Herrenschmidt.
*
- * Move to LinuxBIOS by LYH yhlu@tyan.com
+ * Move to coreboot by LYH yhlu@tyan.com
*
*/
#define PCI_DEVICE_ID_SIS_SIS968_PCIE 0x000a /* D6F0,D7F0 */
#define PCI_DEVICE_ID_SIS_SIS968_HD_AUDIO 0x7502 /* DfF0 */
-/* OLD USAGE FOR LINUXBIOS */
+/* OLD USAGE FOR COREBOOT */
#define PCI_VENDOR_ID_ACER 0x10b9
#define PCI_DEVICE_ID_ACER_M1535D 0x1533
extern const char mainboard_vendor[];
extern const char mainboard_part_number[];
-/* LinuxBIOS Version */
-extern const char linuxbios_version[];
-extern const char linuxbios_extra_version[];
-extern const char linuxbios_build[];
+/* coreboot Version */
+extern const char coreboot_version[];
+extern const char coreboot_extra_version[];
+extern const char coreboot_build[];
-/* When LinuxBIOS was compiled */
-extern const char linuxbios_compile_time[];
-extern const char linuxbios_compile_by[];
-extern const char linuxbios_compile_host[];
-extern const char linuxbios_compile_domain[];
-extern const char linuxbios_compiler[];
-extern const char linuxbios_linker[];
-extern const char linuxbios_assembler[];
+/* When coreboot was compiled */
+extern const char coreboot_compile_time[];
+extern const char coreboot_compile_by[];
+extern const char coreboot_compile_host[];
+extern const char coreboot_compile_domain[];
+extern const char coreboot_compiler[];
+extern const char coreboot_linker[];
+extern const char coreboot_assembler[];
#endif /* VERSION_H */
#define __X86EMU_X86EMU_H
/* FIXME: undefine printk for the moment */
-#ifdef LINUXBIOS_VERSION
+#ifdef COREBOOT_VERSION
#include "console/console.h"
#define printk printk_debug
#else
/*
-LinuxBIOS interface to memory-saving variant of LZMA decoder
+Coreboot interface to memory-saving variant of LZMA decoder
(C)opyright 2006 Carl-Daniel Hailfinger
Released under the GNU GPL
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
- * 2006.12.10 yhlu moved it to LinuxBIOS and use struct instead
+ * 2006.12.10 yhlu moved it to corbeoot and use struct instead
*/
#ifndef __ROMCC__
#include <console/console.h>
#error MAINBOARD_PART_NUMBER not defined
#endif
-#ifndef LINUXBIOS_VERSION
-#error LINUXBIOS_VERSION not defined
+#ifndef COREBOOT_VERSION
+#error COREBOOT_VERSION not defined
#endif
-#ifndef LINUXBIOS_BUILD
-#error LINUXBIOS_BUILD not defined
+#ifndef COREBOOT_BUILD
+#error COREBOOT_BUILD not defined
#endif
-#ifndef LINUXBIOS_COMPILE_TIME
-#error LINUXBIOS_COMPILE_TIME not defined
+#ifndef COREBOOT_COMPILE_TIME
+#error COREBOOT_COMPILE_TIME not defined
#endif
-#ifndef LINUXBIOS_COMPILE_BY
-#error LINUXBIOS_COMPILE_BY not defined
+#ifndef COREBOOT_COMPILE_BY
+#error COREBOOT_COMPILE_BY not defined
#endif
-#ifndef LINUXBIOS_COMPILE_HOST
-#error LINUXBIOS_COMPILE_HOST not defined
+#ifndef COREBOOT_COMPILE_HOST
+#error COREBOOT_COMPILE_HOST not defined
#endif
-#ifndef LINUXBIOS_COMPILER
-#error LINUXBIOS_COMPILER not defined
+#ifndef COREBOOT_COMPILER
+#error COREBOOT_COMPILER not defined
#endif
-#ifndef LINUXBIOS_LINKER
-#error LINUXBIOS_LINKER not defined
+#ifndef COREBOOT_LINKER
+#error COREBOOT_LINKER not defined
#endif
-#ifndef LINUXBIOS_ASSEMBLER
-#error LINUXBIOS_ASSEMBLER not defined
+#ifndef COREBOOT_ASSEMBLER
+#error COREBOOT_ASSEMBLER not defined
#endif
-#ifndef LINUXBIOS_EXTRA_VERSION
-#define LINUXBIOS_EXTRA_VERSION ""
+#ifndef COREBOOT_EXTRA_VERSION
+#define COREBOOT_EXTRA_VERSION ""
#endif
const char mainboard_vendor[] = MAINBOARD_VENDOR;
const char mainboard_part_number[] = MAINBOARD_PART_NUMBER;
-const char linuxbios_version[] = LINUXBIOS_VERSION;
-const char linuxbios_extra_version[] = LINUXBIOS_EXTRA_VERSION;
-const char linuxbios_build[] = LINUXBIOS_BUILD;
-
-const char linuxbios_compile_time[] = LINUXBIOS_COMPILE_TIME;
-const char linuxbios_compile_by[] = LINUXBIOS_COMPILE_BY;
-const char linuxbios_compile_host[] = LINUXBIOS_COMPILE_HOST;
-const char linuxbios_compile_domain[] = LINUXBIOS_COMPILE_DOMAIN;
-const char linuxbios_compiler[] = LINUXBIOS_COMPILER;
-const char linuxbios_linker[] = LINUXBIOS_LINKER;
-const char linuxbios_assembler[] = LINUXBIOS_ASSEMBLER;
+const char coreboot_version[] = COREBOOT_VERSION;
+const char coreboot_extra_version[] = COREBOOT_EXTRA_VERSION;
+const char coreboot_build[] = COREBOOT_BUILD;
+
+const char coreboot_compile_time[] = COREBOOT_COMPILE_TIME;
+const char coreboot_compile_by[] = COREBOOT_COMPILE_BY;
+const char coreboot_compile_host[] = COREBOOT_COMPILE_HOST;
+const char coreboot_compile_domain[] = COREBOOT_COMPILE_DOMAIN;
+const char coreboot_compiler[] = COREBOOT_COMPILER;
+const char coreboot_linker[] = COREBOOT_LINKER;
+const char coreboot_assembler[] = COREBOOT_ASSEMBLER;
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
end
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
end
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD_VENDOR
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses CC
uses HOSTCC
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
## SPEW 9 Way too many details
-## These values can be overwritten by LinuxBIOSv2/targets/agami/aruma/Config.lb
+## These values can be overwritten by corebootv2/targets/agami/aruma/Config.lb
## Request this level of debugging output
default DEFAULT_CONSOLE_LOGLEVEL=8
## At a maximum only compile in this level of debugging
/* The next two tables are used by our DSDT and are freely defined
* here. This construct is used because the bus numbers containing
- * the 8131 bridges may vary so that we need to pass LinuxBIOS
+ * the 8131 bridges may vary so that we need to pass coreboot
* knowledge into the DSDT
*/
typedef struct lnxc_busses {
acpi_lnxb_busses_t busses[5];
} acpi_lnxb_t;
-/* special linuxbios acpi table */
+/* special coreboot acpi table */
void acpi_create_lnxb(acpi_lnxb_t *lnxb)
{
device_t dev;
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/32bit/entry32.lds
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /arch/i386/lib/id.lds
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
default HAVE_MP_TABLE=0
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=0
default HAVE_OPTION_TABLE=0
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
default FALLBACK_SIZE = 131072
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/32bit/entry32.lds
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /arch/i386/lib/id.lds
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
default HAVE_MP_TABLE=0
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=0
default HAVE_OPTION_TABLE=0
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
default FALLBACK_SIZE = 131072
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/32bit/entry32.lds
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /arch/i386/lib/id.lds
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
default HAVE_MP_TABLE=0
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=0
default HAVE_OPTION_TABLE=0
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
default FALLBACK_SIZE = 131072
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FAILOVER_IMAGE
default ROM_SECTION_SIZE = FAILOVER_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
if HAVE_FAILOVER_BOOT
end
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
end
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
default HAVE_FAILOVER_BOOT=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00100000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
At this time, For acpi support We got
-1. support AMK K8 SRAT --- dynamically (LinuxBIOS run-time) (src/northbridge/amd/amdk8/amdk8_acpi.c)
-2. support MADT ---- dynamically (LinuxBIOS run-time) (src/northbridge/amd/amdk8/amdk8_acpi.c , src/mainboard/amd/serengeti_cheetah/acpi_tables.c)
-3. support DSDT ---- dynamically (Compile time, LinuxBIOS run-time, ACPI run-time) (src/mainboard/amd/serengeti_cheetah/{dx/*, get_bus_conf.c}, src/northbridge/amd/amdk8/get_sblk_pci1234.c)
+1. support AMK K8 SRAT --- dynamically (coreboot run-time) (src/northbridge/amd/amdk8/amdk8_acpi.c)
+2. support MADT ---- dynamically (coreboot run-time) (src/northbridge/amd/amdk8/amdk8_acpi.c , src/mainboard/amd/serengeti_cheetah/acpi_tables.c)
+3. support DSDT ---- dynamically (Compile time, coreboot run-time, ACPI run-time) (src/mainboard/amd/serengeti_cheetah/{dx/*, get_bus_conf.c}, src/northbridge/amd/amdk8/get_sblk_pci1234.c)
4. Chipset support: amd8111, amd8132
The developers need to change for different MB
if there is HT-IO board, may use pci2.asl.... to create ssdt2.c, and ssdt3,c and ssdt4.c, ....ssdt8.c
Change acpi_tables.c
- sbdn: Real SB device Num. for 8111 =3 or 1 depend if 8131 presents. ---- Actually you don't need to change it, it is LinuxBIOS run-time configurable now.
+ sbdn: Real SB device Num. for 8111 =3 or 1 depend if 8131 presents. ---- Actually you don't need to change it, it is coreboot run-time configurable now.
if there is HT-IO board, need to adjust SSDTX_NUM...., and preset pci1234 array. acpi_tables.c will decide to put the SSDT on the RSDT or not according if the HT-IO board is installed
Regarding pci bridge apic and pic
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FAILOVER_IMAGE
default ROM_SECTION_SIZE = FAILOVER_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
if HAVE_FAILOVER_BOOT
end
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
end
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
default HAVE_FAILOVER_BOOT=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00200000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
end
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
end
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD_VENDOR
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
default HAVE_FALLBACK_BOOT=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/32bit/entry32.lds
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /arch/i386/lib/id.lds
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
default HAVE_MP_TABLE=0
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=0
default HAVE_OPTION_TABLE=0
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
default FALLBACK_SIZE = 131072
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
*--------------------------------------------------------------------*/
/* Modified to be a self sufficient plug in so that it can be used
- without reliance on other parts of core Linuxbios
+ without reliance on other parts of core coreboot
(C) 2005 Nick.Barker9@btinternet.com
Used initially for epia-m where there are problems getting the bios
// that simplifies a lot of things ...
// we'll just push all the registers on the stack as longwords,
// and pop to protected mode.
-// second, since this only ever runs as part of linuxbios,
+// second, since this only ever runs as part of coreboot,
// we know all the segment register values -- so we don't save any.
// keep the handler that calls things small. It can do a call to
-// more complex code in linuxbios itself. This helps a lot as we don't
+// more complex code in coreboot itself. This helps a lot as we don't
// have to do address fixup in this little stub, and calls are absolute
// so the handler is relocatable.
void handler_vga(void)
pci_dev_init(dev);
- // code to make vga init run in real mode - does work but against the current Linuxbios philosophy
+ // code to make vga init run in real mode - does work but against the current coreboot philosophy
printk_debug("INSTALL REAL-MODE IDT\n");
setup_realmode_idt();
printk_debug("DO THE VGA BIOS\n");
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/32bit/entry32.lds
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /arch/i386/lib/id.lds
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
default HAVE_FALLBACK_BOOT=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=0
# default HAVE_OPTION_TABLE=0
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 64 * 1024
default FALLBACK_SIZE = 128 * 1024
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FAILOVER_IMAGE
default ROM_SECTION_SIZE = FAILOVER_SIZE
end
##
-## Compute the start location and size size of the LinuxBIOS bootloader.
+## Compute the start location and size size of the coreboot bootloader.
##
default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of LinuxBIOS will start in the boot ROM.
+## Compute where this copy of coreboot will start in the boot ROM.
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can be cached to speed up LinuxBIOS
+## Compute a range of ROM that can be cached to speed up coreboot
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2 (here 64 Kbyte)
end
##
-## Build our 16 bit and 32 bit LinuxBIOS entry code.
+## Build our 16 bit and 32 bit coreboot entry code.
##
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
end
##
-## Build our reset vector (this is where LinuxBIOS is entered).
+## Build our reset vector (this is where coreboot is entered).
##
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
###
-### This is the early phase of LinuxBIOS startup.
+### This is the early phase of coreboot startup.
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
default HAVE_FAILOVER_BOOT=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2891
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = (64*1024)
#65536
default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD = 1
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
if USE_FALLBACK_IMAGE
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
end
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD_VENDOR
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
default HAVE_FALLBACK_BOOT=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=0
default HAVE_OPTION_TABLE=0
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
#default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1234
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 64 * 1024
##
##default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/32bit/entry32.lds
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /arch/i386/lib/id.lds
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
default HAVE_MP_TABLE = 0
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET = 0
default CONFIG_IDE = 1
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
default FALLBACK_SIZE = 131072
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
* It was not possible to read back the PIRQ table. There was no BIOS to ask
* for it, only a bootloader for an embedded OS.
* But with the method described here:
- * http://linuxbios.org/Creating_Valid_IRQ_Tables
+ * http://coreboot.org/Creating_Valid_IRQ_Tables
* it was possible to detect the physical IRQ routing on this board.
*
* This is the physical routing on this board:
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
end
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
end
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
default HAVE_FALLBACK_BOOT=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/32bit/entry32.lds
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /arch/i386/lib/id.lds
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD_VENDOR
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses _RAMBASE
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
###
### Compute the location and size of where this firmware image
-### (linuxBIOS plus bootloader) will live in the boot rom chip.
+### (coreboot plus bootloader) will live in the boot rom chip.
###
default FALLBACK_SIZE=131072
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/32bit/entry32.lds
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /arch/i386/lib/id.lds
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
default HAVE_MP_TABLE=0
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
default FALLBACK_SIZE = 131072
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
default ROM_SIZE = 512 * 1024
default FALLBACK_SIZE = 0x10000
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/32bit/entry32.lds
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /arch/i386/lib/id.lds
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
default HAVE_MP_TABLE=0
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
default FALLBACK_SIZE = 131072
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/32bit/entry32.lds
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /arch/i386/lib/id.lds
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
default HAVE_MP_TABLE=0
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=0
default HAVE_OPTION_TABLE=0
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
default FALLBACK_SIZE = 131072
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
Just wbinvd the stack to clear the cache tags. We don't care where the stack used to be.
2. This file is built as a normal .c -> .o and linked in etc. The stack might be used to return etc.
That means we care about what is in the stack. If we are smart we set the CAR stack to the same location
- as the rest of LinuxBIOS. If that is the case we can just do a wbinvd. The stack will be written into real
+ as the rest of coreboot. If that is the case we can just do a wbinvd. The stack will be written into real
RAM that is now setup and we continue like nothing happened. If the stack is located somewhere other than
where LB would like it, you need to write some code to do a copy from cache to RAM
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/32bit/entry32.lds
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /arch/i386/lib/id.lds
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
default HAVE_MP_TABLE=0
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=0
default HAVE_OPTION_TABLE=0
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
default FALLBACK_SIZE = 131072
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
## Build the objects we have code for in this directory.
##
-addaction linuxbios.a "$(CROSS_COMPILE)ranlib linuxbios.a"
+addaction coreboot.a "$(CROSS_COMPILE)ranlib coreboot.a"
makedefine CFLAGS += -msoft-float
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses CROSS_COMPILE
uses CC
uses HOSTCC
## Board has fixed size RAM
default EMBEDDED_RAM_SIZE=64*1024*1024
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
default _RAMBASE=0x00100000
##
## Exception vectors
default _EXCEPTION_VECTORS=_ROMBASE+0x100
-## linuxBIOS ROM start address
+## coreboot ROM start address
default _ROMSTART=0xfff03000
-## linuxBIOS C code runs at this location in RAM
+## coreboot C code runs at this location in RAM
default _RAMBASE=0x00100000
### End Options.lb
[HOST]
IP 10.0.1.2
FORMAT ELF
-FILE linuxbios.elf
+FILE coreboot.elf
;START 0x200000
LOAD MANUAL ;load code MANUAL or AUTO after reset
DEBUGPORT 2001
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
default ROM_SIZE = 256 * 1024
default ROM_SECTION_SIZE = ROM_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/32bit/entry32.lds
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
default HAVE_MP_TABLE=0
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=0
default HAVE_OPTION_TABLE=1
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
default FALLBACK_SIZE = 131072
static void vga_init(device_t dev)
{
- /* code to make vga init run in real mode - does work but against the current Linuxbios philosophy */
+ /* code to make vga init run in real mode - does work but against the current coreboot philosophy */
printk_debug("INSTALL REAL-MODE IDT\n");
setup_realmode_idt();
printk_debug("DO THE VGA BIOS\n");
*--------------------------------------------------------------------*/
/* Modified to be a self sufficient plug in so that it can be used
- without reliance on other parts of core Linuxbios
+ without reliance on other parts of core coreboot
(C) 2005 Nick.Barker9@btinternet.com
Used initially for epia-m where there are problems getting the bios
// that simplifies a lot of things ...
// we'll just push all the registers on the stack as longwords,
// and pop to protected mode.
-// second, since this only ever runs as part of linuxbios,
+// second, since this only ever runs as part of coreboot,
// we know all the segment register values -- so we don't save any.
// keep the handler that calls things small. It can do a call to
-// more complex code in linuxbios itself. This helps a lot as we don't
+// more complex code in coreboot itself. This helps a lot as we don't
// have to do address fixup in this little stub, and calls are absolute
// so the handler is relocatable.
void handler(void)
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FAILOVER_IMAGE
default ROM_SECTION_SIZE = FAILOVER_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
end
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
default HAVE_FAILOVER_BOOT=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1234
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00100000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FAILOVER_IMAGE
default ROM_SECTION_SIZE = FAILOVER_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
end
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
default HAVE_FAILOVER_BOOT=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00100000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
end
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
end
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
uses MAINBOARD
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
default HAVE_FALLBACK_BOOT=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
#default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
end
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
end
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
uses MAINBOARD
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
default HAVE_FALLBACK_BOOT=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
#default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
default ROM_SIZE = 256 * 1024
default ROM_SECTION_SIZE = ROM_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/32bit/entry32.lds
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
default HAVE_MP_TABLE=0
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=0
default HAVE_OPTION_TABLE=0
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
default FALLBACK_SIZE = 131072
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/32bit/entry32.lds
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /arch/i386/lib/id.lds
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
default HAVE_MP_TABLE=0
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=0
default HAVE_OPTION_TABLE=1
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
default FALLBACK_SIZE = 131072
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/32bit/entry32.lds
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /arch/i386/lib/id.lds
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD_VENDOR
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses _RAMBASE
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
#default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3437
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
###
### Compute the location and size of where this firmware image
-### (linuxBIOS plus bootloader) will live in the boot rom chip.
+### (coreboot plus bootloader) will live in the boot rom chip.
###
default FALLBACK_SIZE=131072
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
## BEGIN BOILERPLATE - DO NOT EDIT
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus payload) will live in the boot rom chip.
+## (coreboot plus payload) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
# The fallback image uses FALLBACK_SIZE bytes at the end of the ROM
default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
else
-# The normal image goes at the beginning of the LinuxBIOS ROM region
+# The normal image goes at the beginning of the coreboot ROM region
# and uses all the remaining space
default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
end
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/32bit/entry32.lds
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if HAVE_FALLBACK_BOOT
if USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/id.lds
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses ROM_SIZE
uses ROM_IMAGE_SIZE
uses FALLBACK_SIZE
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
## These are defined in mainboard Config.lb, don't add here
uses ROM_SECTION_SIZE
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2480
###
-### LinuxBIOS layout values
+### coreboot layout values
###
##
default USE_OPTION_TABLE = 0
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
#ifndef XE7501DEVKIT_BUS_H_INCLUDED
#define XE7501DEVKIT_BUS_H_INCLUDED
-// These were determined by seeing how LinuxBIOS enumerates the various
+// These were determined by seeing how coreboot enumerates the various
// PCI (and PCI-like) buses on the board.
#define PCI_BUS_CHIPSET 0
-// IOAPIC addresses determined by LinuxBIOS enumeration.
+// IOAPIC addresses determined by coreboot enumeration.
// Someday add functions to get APIC IDs and versions from the chips themselves.
#define IOAPIC_ICH3 2
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FAILOVER_IMAGE
default ROM_SECTION_SIZE = FAILOVER_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
if HAVE_FAILOVER_BOOT
end
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
end
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
default HAVE_FAILOVER_BOOT=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00100000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
end
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
end
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD_VENDOR
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
default HAVE_FALLBACK_BOOT=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
end
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
end
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD_VENDOR
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
default HAVE_FALLBACK_BOOT=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
#default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/32bit/entry32.lds
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /arch/i386/lib/id.lds
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
default HAVE_MP_TABLE=0
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=0
default HAVE_OPTION_TABLE=0
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
default FALLBACK_SIZE = 131072
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
dir nvram
dir flash
-addaction linuxbios.a "$(CROSS_COMPILE)ranlib linuxbios.a"
+addaction coreboot.a "$(CROSS_COMPILE)ranlib coreboot.a"
makedefine CFLAGS += -g
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses CROSS_COMPILE
uses CC
uses HOSTCC
default CONFIG_FS_FAT=1
default AUTOBOOT_CMDLINE="hdc1:/vmlinuz"
-# LinuxBIOS must fit into 128KB
+# coreboot must fit into 128KB
default ROM_IMAGE_SIZE=131072
default ROM_SIZE={ROM_IMAGE_SIZE+PAYLOAD_SIZE}
default PAYLOAD_SIZE=262144
## Exception vectors (other than reset vector)
default _EXCEPTION_VECTORS=_RESET+0x100
-## Start of linuxBIOS in the boot rom
+## Start of coreboot in the boot rom
## = _RESET + exeception vector table size
default _ROMSTART=_RESET+0x3100
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
default _RAMBASE=0x00100000
default _RAMSTART=0x00100000
[HOST]
IP 10.0.1.11
;FILE E:\cygnus\root\usr\demo\sp7400\vxworks
-FILE linuxbios.elf
+FILE coreboot.elf
FORMAT ELF
;START 0x403104
LOAD MANUAL ;load code MANUAL or AUTO after reset
CHIPSIZE 0x100000 ;The size of one flash chip in bytes (e.g. Am29LV800BB = 0x100000)
BUSWIDTH 8 ;The width of the flash memory bus in bits (8 | 16 | 32 | 64)
WORKSPACE 0x00000000 ;workspace in SDRAM
-FILE linuxbios.elf
+FILE coreboot.elf
FORMAT ELF
ERASE 0xFFF00000 ;erase sector 0 of flash
ERASE 0xFFF04000 ;erase sector 1 of flash
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses CROSS_COMPILE
uses CC
uses HOSTCC
default CONFIG_FS_FAT=1
default AUTOBOOT_CMDLINE="hdc1:/vmlinuz"
-# LinuxBIOS must fit into 128KB
+# coreboot must fit into 128KB
default ROM_IMAGE_SIZE=131072
default ROM_SIZE={ROM_IMAGE_SIZE+PAYLOAD_SIZE}
default PAYLOAD_SIZE=262144
## Exception vectors (other than reset vector)
default _EXCEPTION_VECTORS=_RESET+0x100
-## Start of linuxBIOS in the boot rom
+## Start of coreboot in the boot rom
## = _RESET + exeception vector table size
default _ROMSTART=_RESET+0x3100
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
default _RAMBASE=0x00100000
default _RAMSTART=0x00100000
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
default LIFT_BSP_APIC_ID = 1
default CONFIG_CHIP_NAME = 1
-# Move the default LinuxBIOS CMOS range off of AMD RTC registers.
+# Move the default coreboot CMOS range off of AMD RTC registers.
default LB_CKS_RANGE_START = 49
default LB_CKS_RANGE_END = 122
default LB_CKS_LOC = 123
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
if USE_FALLBACK_IMAGE
end
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
end
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
default HAVE_FALLBACK_BOOT=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00100000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD = 1
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
end
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
end
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD_VENDOR
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
default HAVE_FALLBACK_BOOT=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x9282
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
end
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
end
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
default HAVE_FALLBACK_BOOT=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x0010
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FAILOVER_IMAGE
default ROM_SECTION_SIZE = FAILOVER_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
end
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
default HAVE_FAILOVER_BOOT=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00100000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/32bit/entry32.lds
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /arch/i386/lib/id.lds
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
default HAVE_MP_TABLE=0
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=0
default HAVE_OPTION_TABLE=0
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
default FALLBACK_SIZE = 131072
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/32bit/entry32.lds
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /arch/i386/lib/id.lds
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
default HAVE_MP_TABLE=0
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=0
default HAVE_OPTION_TABLE=0
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
default FALLBACK_SIZE = 131072
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/32bit/entry32.lds
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /arch/i386/lib/id.lds
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
default HAVE_MP_TABLE=0
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=0
default HAVE_OPTION_TABLE=0
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
default FALLBACK_SIZE = 131072
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
* etc. The stack might be used to return etc. That means we
* care about what is in the stack. If we are smart we set
* the CAR stack to the same location as the rest of
- * LinuxBIOS. If that is the case we can just do a wbinvd.
+ * coreboot. If that is the case we can just do a wbinvd.
* The stack will be written into real RAM that is now setup
* and we continue like nothing happened. If the stack is
* located somewhere other than where LB would like it, you
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD = 1
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
end
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD_VENDOR
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
default HAVE_FALLBACK_BOOT=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x40
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FAILOVER_IMAGE
default ROM_SECTION_SIZE = FAILOVER_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
end
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
default HAVE_FAILOVER_BOOT=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1511
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00100000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can be cached to speed up linuxBIOS,
+## Compute a range of ROM that can be cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/32bit/entry32.lds
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /arch/i386/lib/id.lds
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD_VENDOR
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses _RAMBASE
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6780
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
###
### Compute the location and size of where this firmware image
-### (linuxBIOS plus bootloader) will live in the boot rom chip.
+### (coreboot plus bootloader) will live in the boot rom chip.
###
default FALLBACK_SIZE=131072
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of LinuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE =( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can be cached to speed up linuxBIOS.
+## Compute a range of ROM that can be cached to speed up coreboot.
## execution speed.
## XIP_ROM_SIZE must be a power of 2.
## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/32bit/entry32.lds
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /arch/i386/lib/id.lds
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD_VENDOR
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses _RAMBASE
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6080
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
###
### Compute the location and size of where this firmware image
-### (linuxBIOS plus bootloader) will live in the boot rom chip.
+### (coreboot plus bootloader) will live in the boot rom chip.
###
default FALLBACK_SIZE=131072
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of LinuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE =( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can be cached to speed up linuxBIOS.
+## Compute a range of ROM that can be cached to speed up coreboot.
## execution speed.
## XIP_ROM_SIZE must be a power of 2.
## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/32bit/entry32.lds
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /arch/i386/lib/id.lds
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD_VENDOR
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses _RAMBASE
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6080
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
###
### Compute the location and size of where this firmware image
-### (linuxBIOS plus bootloader) will live in the boot rom chip.
+### (coreboot plus bootloader) will live in the boot rom chip.
###
default FALLBACK_SIZE=131072
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/32bit/entry32.lds
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /arch/i386/lib/id.lds
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD_VENDOR
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses _RAMBASE
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
###
### Compute the location and size of where this firmware image
-### (linuxBIOS plus bootloader) will live in the boot rom chip.
+### (coreboot plus bootloader) will live in the boot rom chip.
###
default FALLBACK_SIZE=131072
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/32bit/entry32.lds
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /arch/i386/lib/id.lds
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD_VENDOR
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses _RAMBASE
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
###
### Compute the location and size of where this firmware image
-### (linuxBIOS plus bootloader) will live in the boot rom chip.
+### (coreboot plus bootloader) will live in the boot rom chip.
###
default FALLBACK_SIZE=131072
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
default ROM_SIZE = 128 * 1024
default FALLBACK_SIZE = 0x10000
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/32bit/entry32.lds
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /arch/i386/lib/id.lds
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
default HAVE_MP_TABLE=0
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
default FALLBACK_SIZE = 131072
## Build the objects we have code for in this directory.
##
-addaction linuxbios.a "$(CROSS_COMPILE)ranlib linuxbios.a"
+addaction coreboot.a "$(CROSS_COMPILE)ranlib coreboot.a"
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses CROSS_COMPILE
uses CC
uses HOSTCC
## Exception vectors (other than reset vector)
default _EXCEPTION_VECTORS=_RESET+0x100
-## Start of linuxBIOS in the boot rom
+## Start of coreboot in the boot rom
## = _RESET + exeception vector table size
default _ROMSTART=_RESET+0x3100
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
default _RAMBASE=0x00100000
default _RAMSTART=0x00100000
CHIPSIZE 0x100000 ;The size of one flash chip in bytes (e.g. Am29LV800BB = 0x100000)
BUSWIDTH 8 ;The width of the flash memory bus in bits (8 | 16 | 32 | 64)
;WORKSPACE 0x00000000 ;workspace in SDRAM
-FILE linuxbios.rom
+FILE coreboot.rom
FORMAT ELF
ERASE 0xFFF00000 ;erase sector 0 of flash
ERASE 0xFFF10000 ;erase sector 1 of flash
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD = 1
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
end
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
default HAVE_FALLBACK_BOOT=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2735
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
#endif
- /*copy and execute linuxbios_ram */
+ /*copy and execute coreboot_ram */
copy_and_run(new_cpu_reset);
/* We will not return */
}
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
end
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
end
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
default HAVE_FALLBACK_BOOT=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2850
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
end
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
end
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
default HAVE_FALLBACK_BOOT=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2875
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
end
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
end
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
default HAVE_FALLBACK_BOOT=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2880
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
end
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
end
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
default HAVE_FALLBACK_BOOT=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2881
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
end
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
end
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
default HAVE_FALLBACK_BOOT=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2882
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
end
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
end
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
default HAVE_FALLBACK_BOOT=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2885
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD = 1
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
end
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
end
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
default HAVE_FALLBACK_BOOT=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2891
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD = 1
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
end
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
end
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
default HAVE_FALLBACK_BOOT=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2892
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FAILOVER_IMAGE
default ROM_SECTION_SIZE = FAILOVER_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
end
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD_VENDOR
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
default HAVE_FAILOVER_BOOT=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2895
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00100000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FAILOVER_IMAGE
default ROM_SECTION_SIZE = FAILOVER_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
end
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
default HAVE_FAILOVER_BOOT=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2912
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00100000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD = 1
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
end
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD_VENDOR
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
default HAVE_FALLBACK_BOOT=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x4880
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD = 1
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
end
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD_VENDOR
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
default HAVE_FALLBACK_BOOT=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x4882
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00002000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/32bit/entry32.lds
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /arch/i386/lib/id.lds
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=0
default HAVE_OPTION_TABLE=1
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
default FALLBACK_SIZE = 131072
/*
- * LinuxBIOS ACPI Table support
+ * coreboot ACPI Table support
* written by Stefan Reinauer <stepan@openbios.org>
* ACPI FADT, FACS, and DSDT table support added by
* Nick Barker <nick.barker9@btinternet.com>, and those portions
// we do this right here because:
// - all the hardware is working, and some VGA bioses seem to need
// that
- // - we need page 0 below for linuxbios tables.
+ // - we need page 0 below for coreboot tables.
printk_debug("INSTALL REAL-MODE IDT\n");
setup_realmode_idt();
*--------------------------------------------------------------------*/
/* Modified to be a self sufficient plug in so that it can be used
- without reliance on other parts of core Linuxbios
+ without reliance on other parts of core coreboot
(C) 2005 Nick.Barker9@btinternet.com
Used initially for epia-m where there are problems getting the bios
// that simplifies a lot of things ...
// we'll just push all the registers on the stack as longwords,
// and pop to protected mode.
-// second, since this only ever runs as part of linuxbios,
+// second, since this only ever runs as part of coreboot,
// we know all the segment register values -- so we don't save any.
// keep the handler that calls things small. It can do a call to
-// more complex code in linuxbios itself. This helps a lot as we don't
+// more complex code in coreboot itself. This helps a lot as we don't
// have to do address fixup in this little stub, and calls are absolute
// so the handler is relocatable.
void handler(void)
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/32bit/entry32.lds
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /arch/i386/lib/id.lds
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
default HAVE_MP_TABLE=0
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=0
default HAVE_OPTION_TABLE=1
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
default FALLBACK_SIZE = 131072
u32 up_planes; // down planes will be [up_planes, planes)
} __attribute__((packed));
-/* be careful with the alignment of sysinfo, bacause sysinfo may be shared by linuxbios_car and linuxbios_ram stage. and linuxbios_ram may be running at 64bit later.*/
+/* be careful with the alignment of sysinfo, bacause sysinfo may be shared by coreboot_car and coreboot_ram stage. and coreboot_ram may be running at 64bit later.*/
#if CONFIG_AMDMCT == 0
//#define MEM_CS_COPY 1
void CALLCONV AmdPCIRead(SBDFO loc, u32 *Value)
{
- /* Use LinuxBIOS PCI functions */
+ /* Use coreboot PCI functions */
*Value = pci_read_config32((loc & 0xFFFFF000), SBDFO_OFF(loc));
}
void CALLCONV AmdPCIWrite(SBDFO loc, u32 *Value)
{
- /* Use LinuxBIOS PCI functions */
+ /* Use coreboot PCI functions */
pci_write_config32((loc & 0xFFFFF000), SBDFO_OFF(loc), *Value);
}
#include "porting.h"
-/* include LinuxBIOS pci functions */
+/* include coreboot pci functions */
#include <device/pci_def.h>
#include <device/pci_ids.h>
/**
* void amd_ht_init(struct sys_info *sysinfo)
*
- * AMD HT init LinuxBIOS wrapper
+ * AMD HT init coreboot wrapper
*
*/
void amd_ht_init(struct sys_info *sysinfo)
train_ram(nodeid, sysinfo, sysinfox);
#else
/* Can copy dqs_timing to ap cache and run from cache?
- * we need linuxbios_ap_car.rom? and treat it as linuxbios_ram.rom for ap ?
+ * we need coreboot_ap_car.rom? and treat it as coreboot_ram.rom for ap ?
*/
copy_and_run_ap_code_in_car(retcall);
// will go back by jump
Set default values for CPU registers
======================================================================*/
- /* NOTE : For LinuxBIOS, we don't need to set mtrr enables here because
+ /* NOTE : For coreboot, we don't need to set mtrr enables here because
they are still enable from cache_as_ram.inc */
addr = 0x250;
/*======================================================================
Set variable MTRR values
======================================================================*/
- /* NOTE: for LinuxBIOS change from 0x200 to 0x204: LinuxBIOS is using
+ /* NOTE: for coreboot change from 0x200 to 0x204: coreboot is using
0x200, 0x201 for [1M, CONFIG_TOP_MEM)
0x202, 0x203 for ROM Caching
*/
outb( P80_CHIPSET_INIT, 0x80);
ChipsetGeodeLinkInit();
#if 0
- /* we hope NEVER to be in linuxbios when S3 resumes
+ /* we hope NEVER to be in coreboot when S3 resumes
if (! IsS3Resume()) */
{
struct acpiinit *aci = acpi_init_table;
}
- /* I have finally seen ram bad enough to cause LinuxBIOS
+ /* I have finally seen ram bad enough to cause coreboot
* to die in mysterious ways, before booting up far
* enough to run a memory tester. This code attempts
* to catch this blatantly bad ram, with a spot check.
#
-# Objects linked with linuxbios
+# Objects linked with coreboot
#
config chip.h
/*
* pci_domain_set_resources creates memory resources describing the
* fixed memory on the system. This is not actually used anywhere
- * except when the linuxbios table is generated.
+ * except when the coreboot table is generated.
*/
static void pci_domain_set_resources(device_t dev)
{
/* these are ENDING addresses, not sizes.
* if there is memory in this slot, then reg will be > rambits.
* So we just take the max, that gives us total.
- * We take the highest one to cover for once and future linuxbios
+ * We take the highest one to cover for once and future coreboot
* bugs. We warn about bugs.
*/
if (reg > rambits)
#else
- /* code to make vga init run in real mode - does work but against the current Linuxbios philosophy */
+ /* code to make vga init run in real mode - does work but against the current coreboot philosophy */
printk_debug("INSTALL REAL-MODE IDT\n");
setup_realmode_idt();
printk_debug("DO THE VGA BIOS\n");
/* these are ENDING addresses, not sizes.
* if there is memory in this slot, then reg will be > rambits.
* So we just take the max, that gives us total.
- * We take the highest one to cover for once and future linuxbios
+ * We take the highest one to cover for once and future coreboot
* bugs. We warn about bugs.
*/
if (reg > rambits)
256 Mb 266Mhz 2 Bank (i.e. double sided)
512 Mb 266Mhz 2 Bank (i.e. double sided)
*/
-/* ported and enhanced from assembler level code in Linuxbios v1 */
+/* ported and enhanced from assembler level code in coreboot v1 */
#include <cpu/x86/mtrr.h>
#include "raminit.h"
#endif
/**
- * LinuxBIOS management part
+ * coreboot management part
* @param[in] dev Info about the PCI device to initialise
*/
static void cs5530_vga_init(device_t dev)
post_code(P80_CHIPSET_INIT);
- /* we hope NEVER to be in linuxbios when S3 resumes
+ /* we hope NEVER to be in coreboot when S3 resumes
if (! IsS3Resume()) */
{
struct acpiinit *aci = acpi_init_table;
byte |= (1<<0); // SATA enable
pci_write_config8(dev, 0x84, byte);
-// wdt and cf9 for later in linuxbios_ram to call hard_reset
+// wdt and cf9 for later in coreboot_ram to call hard_reset
bcm5785_enable_wdt_port_cf9();
bcm5785_enable_msg();
outb(0x80, 0x80);
}
-// See http://openbios.org/pipermail/linuxbios/2004-September/009077.html
+// See http://www.coreboot.org/pipermail/linuxbios/2004-September/009077.html
// for a description of this function.
static int smbus_wait_until_active(void)
{
* MA 02110-1301 USA
*/
/* (C) Copyright 2005 Nick Barker <nick.barker@btinternet.com
- brought into line with the current architecture of LinuxBios */
+ brought into line with the current architecture of coreboot */
#include <arch/io.h>
dest = (CONFIG_LB_MEM_TOPK<<10);
}
#endif
- if((dest < (unsigned char *) 0xf0000) && ((dest+olen)> (unsigned char *)0xf0000)) { //linuxbios tables etc
+ if((dest < (unsigned char *) 0xf0000) && ((dest+olen)> (unsigned char *)0xf0000)) { // coreboot tables etc
dest = (unsigned char *) (CONFIG_LB_MEM_TOPK<<10);
}
#endif
*/
/* RAM-based driver for SMSC LPC47N217 Super I/O chip. */
-/* Based on LinuxBIOS code for SMSC 47B397. */
+/* Based on coreboot code for SMSC 47B397. */
#include <arch/io.h>
#include <device/device.h>
romimage "normal"
option USE_FALLBACK_IMAGE = 0
- option LINUXBIOS_EXTRA_VERSION = ".0Normal"
+ option COREBOOT_EXTRA_VERSION = ".0Normal"
payload /tmp/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
- option LINUXBIOS_EXTRA_VERSION = ".0Fallback"
+ option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload /tmp/filo.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
romimage "normal"
option USE_FALLBACK_IMAGE = 0
- option LINUXBIOS_EXTRA_VERSION = ".0Normal"
+ option COREBOOT_EXTRA_VERSION = ".0Normal"
payload /tmp/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
- option LINUXBIOS_EXTRA_VERSION = ".0Fallback"
+ option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload /tmp/filo.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x17000
option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION=".0-normal"
+ option COREBOOT_EXTRA_VERSION=".0-normal"
payload ../../../../../../filo.elf
end
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x17000
option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION=".0-fallback"
+ option COREBOOT_EXTRA_VERSION=".0-fallback"
payload ../../../../../../filo.elf
end
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x14000
option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION=".0-big"
+ option COREBOOT_EXTRA_VERSION=".0-big"
payload ../../../../../../linux.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=64*1024
- option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+ option COREBOOT_EXTRA_VERSION=".0Fallback"
payload ../payload.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=64*1024
- option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+ option COREBOOT_EXTRA_VERSION=".0Fallback"
payload ../payload.elf
end
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x10000
- option LINUXBIOS_EXTRA_VERSION=".0Normal"
+ option COREBOOT_EXTRA_VERSION=".0Normal"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
# payload ../../../../../lnxieepro100.ebi
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x10000
- option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+ option COREBOOT_EXTRA_VERSION=".0Fallback"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
# payload ../../../../../lnxieepro100.ebia
payload /tmp/filo.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
#romimage "normal"
# option USE_FALLBACK_IMAGE=0
# option ROM_IMAGE_SIZE=0x10000
-# option LINUXBIOS_EXTRA_VERSION=".0Normal"
+# option COREBOOT_EXTRA_VERSION=".0Normal"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
# payload ../../../../../lnxieepro100.ebi
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x10000
- option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+ option COREBOOT_EXTRA_VERSION=".0Fallback"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
# payload ../../../../../lnxieepro100.ebia
# payload /home/ollie/work/filo-0.4.1/filo.elf
end
-#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
-buildrom ./linuxbios.rom ROM_SIZE "fallback"
+#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "fallback"
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION=".0-normal"
+ option COREBOOT_EXTRA_VERSION=".0-normal"
payload __PAYLOAD__
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION=".0-fallback"
+ option COREBOOT_EXTRA_VERSION=".0-fallback"
payload __PAYLOAD__
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
option ROM_IMAGE_SIZE=0x20000
# option ROM_IMAGE_SIZE=0x15800
option XIP_ROM_SIZE=0x40000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
option ROM_IMAGE_SIZE=0x20000
# option ROM_IMAGE_SIZE=0x15800
option XIP_ROM_SIZE=0x40000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=FAILOVER_SIZE
option XIP_ROM_SIZE=FAILOVER_SIZE
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover"
-#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
+#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION=".0-fallback"
+ option COREBOOT_EXTRA_VERSION=".0-fallback"
payload __PAYLOAD__
end
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=FAILOVER_SIZE
option XIP_ROM_SIZE=FAILOVER_SIZE
- option LINUXBIOS_EXTRA_VERSION=".0-failover"
+ option COREBOOT_EXTRA_VERSION=".0-failover"
end
-buildrom ./linuxbios.rom ROM_SIZE "fallback" "failover"
\ No newline at end of file
+buildrom ./coreboot.rom ROM_SIZE "fallback" "failover"
\ No newline at end of file
# option ROM_IMAGE_SIZE=0x20000
# option ROM_IMAGE_SIZE=0x30000
# option XIP_ROM_SIZE=0x40000
-# option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+# option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../payload.elf
#end
option ROM_IMAGE_SIZE=0x3f000
# option ROM_IMAGE_SIZE=0x15800
option XIP_ROM_SIZE=0x40000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
payload ../payload.elf
end
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=FAILOVER_SIZE
option XIP_ROM_SIZE=FAILOVER_SIZE
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
end
#buildrom ./amd-cheetah-fam10.rom ROM_SIZE "normal" "fallback" "failover"
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION=".0-normal"
+ option COREBOOT_EXTRA_VERSION=".0-normal"
payload __PAYLOAD__
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION=".0-fallback"
+ option COREBOOT_EXTRA_VERSION=".0-fallback"
payload __PAYLOAD__
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
uses CONFIG_CHIP_CONFIGURE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
option CONFIG_CHIP_CONFIGURE=1
###
### Compute the location and size of where this firmware image
-### (linuxBIOS plus bootloader) will live in the boot rom chip.
+### (coreboot plus bootloader) will live in the boot rom chip.
###
option FALLBACK_SIZE=ROM_SIZE
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
option _RAMBASE=0x00004000
#
###
### Compute the start location and size size of
-### The linuxBIOS bootloader.
+### The coreboot bootloader.
###
#
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x10000
# option ROM_SECTION_SIZE=0x100000
- option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+ option COREBOOT_EXTRA_VERSION=".0Fallback"
mainboard arima/hdama
# payload ../../../../tg3--ide_disk.zelf
payload ../../../../opteron_phase1_p4_noapic
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION=".0Normal"
+ option COREBOOT_EXTRA_VERSION=".0Normal"
payload ../../../payloads/filo.elf
# payload /etc/hosts
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+ option COREBOOT_EXTRA_VERSION=".0Fallback"
payload ../../../payloads/filo.elf
# payload /etc/hosts
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
option CONFIG_COMPRESSED_PAYLOAD_LZMA=0
-## ROM_SIZE is the total number of bytes allocated for LinuxBIOS use
+## ROM_SIZE is the total number of bytes allocated for coreboot use
## (normal AND fallback images and payloads).
## leave 36k for vsa and 32K for video ROM
#option ROM_SIZE = 1024*256 - 36*1024 - 32 * 1024
#No VGA for now
option ROM_SIZE = 1024*512 - 36*1024
-# ROM_IMAGE_SIZE is the maximum number of bytes allowed for a LinuxBIOS image,
+# ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
## not including any payload.
option ROM_IMAGE_SIZE=64*1024
option MAXIMUM_CONSOLE_LOGLEVEL = 11
romimage "fallback"
option USE_FALLBACK_IMAGE=1
- option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+ option COREBOOT_EXTRA_VERSION=".0Fallback"
payload ../payload.elf
end
romimage "normal"
option USE_FALLBACK_IMAGE = 0
option ROM_IMAGE_SIZE = 64 * 1024
- option LINUXBIOS_EXTRA_VERSION = ".0Normal"
+ option COREBOOT_EXTRA_VERSION = ".0Normal"
payload /tmp/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
option ROM_IMAGE_SIZE = 64 * 1024
- option LINUXBIOS_EXTRA_VERSION = ".0Fallback"
+ option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload /tmp/filo.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
-# buildrom ./linuxbios.rom ROM_SIZE "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
+# buildrom ./coreboot.rom ROM_SIZE "fallback"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION="_Normal"
+ option COREBOOT_EXTRA_VERSION="_Normal"
payload /tmp/filo.elf
end
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION="_Fallback"
+ option COREBOOT_EXTRA_VERSION="_Fallback"
payload /tmp/filo.elf
end
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=FAILOVER_SIZE
option XIP_ROM_SIZE=FAILOVER_SIZE
- option LINUXBIOS_EXTRA_VERSION="_Failover"
+ option COREBOOT_EXTRA_VERSION="_Failover"
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover"
-#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
+#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
option ROM_SIZE = 512 * 1024
option USE_FALLBACK_IMAGE = 0
option ROM_IMAGE_SIZE = 128 * 1024
- option LINUXBIOS_EXTRA_VERSION=".0Normal"
+ option COREBOOT_EXTRA_VERSION=".0Normal"
payload /tmp/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
option ROM_IMAGE_SIZE = 128 * 1024
- option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+ option COREBOOT_EXTRA_VERSION=".0Fallback"
payload /tmp/filo.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
romimage "normal"
option USE_FALLBACK_IMAGE = 0
- option LINUXBIOS_EXTRA_VERSION = ".0Normal"
+ option COREBOOT_EXTRA_VERSION = ".0Normal"
payload /tmp/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
- option LINUXBIOS_EXTRA_VERSION = ".0Fallback"
+ option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload /tmp/filo.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x10000
- option LINUXBIOS_EXTRA_VERSION=".0Normal"
+ option COREBOOT_EXTRA_VERSION=".0Normal"
# payload /etc/hosts
payload /home/amp/filo-0.5/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x10000
- option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+ option COREBOOT_EXTRA_VERSION=".0Fallback"
# payload /etc/hosts
payload /home/amp/filo-0.5/filo.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
romimage "normal"
option USE_FALLBACK_IMAGE = 0
- option LINUXBIOS_EXTRA_VERSION = ".0Normal"
+ option COREBOOT_EXTRA_VERSION = ".0Normal"
payload /tmp/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
- option LINUXBIOS_EXTRA_VERSION = ".0Fallback"
+ option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload /tmp/filo.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
romimage "normal"
option USE_FALLBACK_IMAGE = 0
- option LINUXBIOS_EXTRA_VERSION = ".0Normal"
+ option COREBOOT_EXTRA_VERSION = ".0Normal"
payload /tmp/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
- option LINUXBIOS_EXTRA_VERSION = ".0Fallback"
+ option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload /tmp/filo.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
romimage "normal"
option USE_FALLBACK_IMAGE = 0
- option LINUXBIOS_EXTRA_VERSION = ".0Normal"
+ option COREBOOT_EXTRA_VERSION = ".0Normal"
payload /tmp/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
- option LINUXBIOS_EXTRA_VERSION = ".0Fallback"
+ option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload /tmp/filo.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-## See also: http://linuxbios.org/AXUS_WINTERM_Build_Tutorial
+## See also: http://coreboot.org/AXUS_WINTERM_Build_Tutorial
target tc320
mainboard axus/tc320
romimage "normal"
option USE_FALLBACK_IMAGE = 0
- option LINUXBIOS_EXTRA_VERSION = ".0Normal"
+ option COREBOOT_EXTRA_VERSION = ".0Normal"
payload ../../../../../../../images/etherboot.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
- option LINUXBIOS_EXTRA_VERSION = ".0Fallback"
+ option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload ../../../../../../../images/etherboot.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
romimage "normal"
option USE_FALLBACK_IMAGE = 0
- option LINUXBIOS_EXTRA_VERSION = ".0Normal"
+ option COREBOOT_EXTRA_VERSION = ".0Normal"
payload /tmp/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
- option LINUXBIOS_EXTRA_VERSION = ".0Fallback"
+ option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload /tmp/filo.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-## See also: http://www.linuxbios.org/BCOM_WINNET100_Build_Tutorial
+## See also: http://www.coreboot.org/BCOM_WINNET100_Build_Tutorial
target winnet100
mainboard bcom/winnet100
romimage "normal"
option USE_FALLBACK_IMAGE = 0
option ROM_IMAGE_SIZE = 64 * 1024
- option LINUXBIOS_EXTRA_VERSION = ".0Normal"
+ option COREBOOT_EXTRA_VERSION = ".0Normal"
payload ../../../../../../../images/etherboot.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
option ROM_IMAGE_SIZE = 64 * 1024
- option LINUXBIOS_EXTRA_VERSION = ".0Fallback"
+ option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload ../../../../../../../images/etherboot.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
romimage "normal"
option USE_FALLBACK_IMAGE = 0
- option LINUXBIOS_EXTRA_VERSION = ".0Normal"
+ option COREBOOT_EXTRA_VERSION = ".0Normal"
payload /tmp/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
- option LINUXBIOS_EXTRA_VERSION = ".0Fallback"
+ option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload /tmp/filo.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
# option ROM_IMAGE_SIZE=0x15000
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
# option ROM_IMAGE_SIZE=0x15000
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
# Target build script
if [ $# -lt 1 ]; then
- echo "usage: buildtarget target [path-to-linuxbios]"
+ echo "usage: buildtarget target [path-to-coreboot]"
exit 1
fi
mkdir -p $build_dir
fi
if [ ! -f $config_py ]; then
- echo "No linuxbios config script found. Rebuilding it.."
+ echo "No coreboot config script found. Rebuilding it.."
$PYTHON $yapps2_py $config_g $config_py
fi
romimage "normal"
option USE_FALLBACK_IMAGE = 0
- option LINUXBIOS_EXTRA_VERSION = ".0Normal"
+ option COREBOOT_EXTRA_VERSION = ".0Normal"
payload /tmp/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
- option LINUXBIOS_EXTRA_VERSION = ".0Fallback"
+ option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload /tmp/filo.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x16000
- option LINUXBIOS_EXTRA_VERSION=".0Normal"
+ option COREBOOT_EXTRA_VERSION=".0Normal"
# payload ../../../payloads/filo.elf
payload /tmp/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x16000
- option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+ option COREBOOT_EXTRA_VERSION=".0Fallback"
# payload ../../../payloads/filo.elf
payload /tmp/filo.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x10000
- option LINUXBIOS_EXTRA_VERSION=".0Normal"
+ option COREBOOT_EXTRA_VERSION=".0Normal"
payload /etc/hosts
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x10000
- option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+ option COREBOOT_EXTRA_VERSION=".0Fallback"
payload /etc/hosts
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
# option ROM_IMAGE_SIZE=32 * 1024 # 0x8000
option ROM_IMAGE_SIZE=128 * 1024 # 0x10000
# option ROM_IMAGE_SIZE=512 * 1024 # 0x10000
- option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+ option COREBOOT_EXTRA_VERSION=".0Fallback"
payload __PAYLOAD__
end
-buildrom ./linuxbios.rom ROM_SIZE "fallback"
+buildrom ./coreboot.rom ROM_SIZE "fallback"
#romimage "normal"
# option USE_FALLBACK_IMAGE=0
# option ROM_IMAGE_SIZE=0x10000
-# option LINUXBIOS_EXTRA_VERSION=".0Normal"
+# option COREBOOT_EXTRA_VERSION=".0Normal"
# payload /etc/hosts
#end
# option ROM_IMAGE_SIZE=32 * 1024 # 0x8000
option ROM_IMAGE_SIZE=128 * 1024 # 0x10000
# option ROM_IMAGE_SIZE=512 * 1024 # 0x10000
- option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+ option COREBOOT_EXTRA_VERSION=".0Fallback"
payload ../../filo.elf
# payload ../../eepro100--ide_disk.zelf
end
-buildrom ./linuxbios.rom ROM_SIZE "fallback"
+buildrom ./coreboot.rom ROM_SIZE "fallback"
option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
-## ROM_SIZE is the total number of bytes allocated for LinuxBIOS use
+## ROM_SIZE is the total number of bytes allocated for coreboot use
## (normal AND fallback images and payloads).
## leave 36k for vsa
##
option ROM_SIZE = 1024*1024 - 36 * 1024
-## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a LinuxBIOS image,
+## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
## not including any payload.
option ROM_IMAGE_SIZE=64*1024
option MAXIMUM_CONSOLE_LOGLEVEL = 11
romimage "fallback"
option USE_FALLBACK_IMAGE=1
- option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+ option COREBOOT_EXTRA_VERSION=".0Fallback"
payload ../payload.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "fallback"
+buildrom ./coreboot.rom ROM_SIZE "fallback"
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x10000
- option LINUXBIOS_EXTRA_VERSION=".0Normal"
+ option COREBOOT_EXTRA_VERSION=".0Normal"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
# payload ../../../../../lnxieepro100.ebi
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x10000
- option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+ option COREBOOT_EXTRA_VERSION=".0Fallback"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
# payload ../../../../../lnxieepro100.ebia
payload /home/hamish/work/etherboot/eb-5.2.6-lne100.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
## Board has fixed size RAM
option EMBEDDED_RAM_SIZE=64*1024*1024
- ## LinuxBIOS C code runs at this location in RAM
+ ## Coreboot C code runs at this location in RAM
option _RAMBASE=0x00100000
##
## Exception vectors
option _EXCEPTION_VECTORS=_ROMBASE+0x100
- ## linuxBIOS ROM start address
+ ## coreboot ROM start address
option _ROMSTART=0xfff03000
- ## linuxBIOS C code runs at this location in RAM
+ ## coreboot C code runs at this location in RAM
option _RAMBASE=0x00100000
end
-buildrom ./linuxbios.rom ROM_SIZE "normal"
+buildrom ./coreboot.rom ROM_SIZE "normal"
romimage "image"
option ROM_IMAGE_SIZE=0x10000
- option LINUXBIOS_EXTRA_VERSION="-OpenBIOS"
+ option COREBOOT_EXTRA_VERSION="-OpenBIOS"
payload __PAYLOAD__
end
romimage "image"
option ROM_IMAGE_SIZE=0x10000
- option LINUXBIOS_EXTRA_VERSION="-OpenBIOS"
+ option COREBOOT_EXTRA_VERSION="-OpenBIOS"
payload /tmp/olpcpayload.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "image"
+buildrom ./coreboot.rom ROM_SIZE "image"
romimage "image"
option ROM_IMAGE_SIZE=0x10000
- option LINUXBIOS_EXTRA_VERSION="-GRUB2"
+ option COREBOOT_EXTRA_VERSION="-GRUB2"
payload /home/stepan/core.img
end
romimage "normal"
option USE_FALLBACK_IMAGE = 0
- option LINUXBIOS_EXTRA_VERSION = ".0Normal"
+ option COREBOOT_EXTRA_VERSION = ".0Normal"
payload /tmp/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
- option LINUXBIOS_EXTRA_VERSION = ".0Fallback"
+ option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload /tmp/filo.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x28000
option XIP_ROM_SIZE=0x40000
- option LINUXBIOS_EXTRA_VERSION=".0-Normal"
+ option COREBOOT_EXTRA_VERSION=".0-Normal"
payload __PAYLOAD__
end
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x40000
- option LINUXBIOS_EXTRA_VERSION=".0-Fallback"
+ option COREBOOT_EXTRA_VERSION=".0-Fallback"
payload __PAYLOAD__
end
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=FAILOVER_SIZE
option XIP_ROM_SIZE=FAILOVER_SIZE
- option LINUXBIOS_EXTRA_VERSION=".0-Failover"
+ option COREBOOT_EXTRA_VERSION=".0-Failover"
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
option USE_FAILOVER_IMAGE=0
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x40000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
payload ../../../../payloads/filo_uda1.elf
end
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x40000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
payload ../../../../payloads/filo_uda1.elf
end
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=FAILOVER_SIZE
option XIP_ROM_SIZE=FAILOVER_SIZE
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
end
-# buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
- buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover"
+# buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
+ buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
## How to append VGA bios?
-cat 6330VGA.rom ga_2761gxdk/linuxbios.rom > ga_2761gxdk.bin
+cat 6330VGA.rom ga_2761gxdk/coreboot.rom > ga_2761gxdk.bin
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x40000
- option LINUXBIOS_EXTRA_VERSION=".0-Normal"
+ option COREBOOT_EXTRA_VERSION=".0-Normal"
payload __PAYLOAD__
end
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x40000
- option LINUXBIOS_EXTRA_VERSION=".0-Fallback"
+ option COREBOOT_EXTRA_VERSION=".0-Fallback"
payload __PAYLOAD__
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
option ROM_IMAGE_SIZE=0x20000
# option ROM_IMAGE_SIZE=0x15800
option XIP_ROM_SIZE=0x40000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
option ROM_IMAGE_SIZE=0x20000
# option ROM_IMAGE_SIZE=0x15800
option XIP_ROM_SIZE=0x40000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=FAILOVER_SIZE
option XIP_ROM_SIZE=FAILOVER_SIZE
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
end
-#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover"
+#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
# option ROM_IMAGE_SIZE=0x15800
# option ROM_IMAGE_SIZE=0x13800
option XIP_ROM_SIZE=0x40000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=FAILOVER_SIZE
option XIP_ROM_SIZE=FAILOVER_SIZE
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
end
-buildrom ./linuxbios.rom ROM_SIZE "fallback" "failover"
-#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "fallback" "failover"
+#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
#
###
### Compute the start location and size size of
-### The linuxBIOS bootloader.
+### The coreboot bootloader.
###
#
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION=".0Normal"
+ option COREBOOT_EXTRA_VERSION=".0Normal"
# payload ../../filo.elf
payload ../../../payloads/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+ option COREBOOT_EXTRA_VERSION=".0Fallback"
# payload ../../filo.elf
payload ../../../payloads/filo.elf
# use this to test a build if you don't have the etherboot
# payload /etc/hosts
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION=".0-normal"
+ option COREBOOT_EXTRA_VERSION=".0-normal"
payload __PAYLOAD__
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION=".0-fallback"
+ option COREBOOT_EXTRA_VERSION=".0-fallback"
payload __PAYLOAD__
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
###
### Compute the start location and size size of
-### The linuxBIOS bootloader.
+### The coreboot bootloader.
###
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION=".0Normal"
+ option COREBOOT_EXTRA_VERSION=".0Normal"
# payload ../../filo.elf
payload ../../../payloads/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+ option COREBOOT_EXTRA_VERSION=".0Fallback"
# payload ../../filo.elf
payload ../../../payloads/filo.elf
# use this to test a build if you don't have the etherboot
# payload /etc/hosts
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
option ROM_SIZE=256*1024
###
### Compute the location and size of where this firmware image
-### (linuxBIOS plus bootloader) will live in the boot rom chip.
+### (coreboot plus bootloader) will live in the boot rom chip.
###
option FALLBACK_SIZE=128*1024
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=64*1024
- option LINUXBIOS_EXTRA_VERSION=".0-Normal"
+ option COREBOOT_EXTRA_VERSION=".0-Normal"
payload __PAYLOAD__
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=64*1024
- option LINUXBIOS_EXTRA_VERSION=".0-Fallback"
+ option COREBOOT_EXTRA_VERSION=".0-Fallback"
payload __PAYLOAD__
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
romimage "image"
option ROM_IMAGE_SIZE=64*1024
- option LINUXBIOS_EXTRA_VERSION="-filo"
+ option COREBOOT_EXTRA_VERSION="-filo"
payload ../../filo.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "image"
+buildrom ./coreboot.rom ROM_SIZE "image"
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=64*1024
- option LINUXBIOS_EXTRA_VERSION=".0Fallback"
- payload /opt/linuxbios-SVN/filo.elf
+ option COREBOOT_EXTRA_VERSION=".0Fallback"
+ payload /opt/coreboot-SVN/filo.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "fallback"
+buildrom ./coreboot.rom ROM_SIZE "fallback"
#"normal"
target xe7501devkit
mainboard intel/xe7501devkit
-## ROM_SIZE is the total number of bytes allocated for LinuxBIOS use
+## ROM_SIZE is the total number of bytes allocated for coreboot use
## (normal AND fallback images and payloads).
option ROM_SIZE = 192*1024
-## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a LinuxBIOS image,
+## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
## not including any payload.
option ROM_IMAGE_SIZE = 0x1B000
romimage "normal"
option USE_FALLBACK_IMAGE=0
-# option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+# option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../../../../../memtest86/memtest
# payload ../../../../../../../etherboot/src/bin/e1000.zelf
payload ../../../../../../../etherboot/src/bin/e1000--filo.zelf
# Thus no support for fallback boot.
#romimage "fallback"
# option USE_FALLBACK_IMAGE=1
-# option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+# option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../../../../../memtest86/memtest
# payload ../../../../../../../etherboot/src/bin/e1000.zelf
# payload ../../../../../../../etherboot/src/bin/e1000--filo.zelf
#end
-buildrom ./linuxbios.rom ROM_SIZE "normal"
+buildrom ./coreboot.rom ROM_SIZE "normal"
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x17000
- option LINUXBIOS_EXTRA_VERSION=".0-normal"
+ option COREBOOT_EXTRA_VERSION=".0-normal"
payload __PAYLOAD__
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x17000
- option LINUXBIOS_EXTRA_VERSION=".0-fallback"
+ option COREBOOT_EXTRA_VERSION=".0-fallback"
payload __PAYLOAD__
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
# option ROM_IMAGE_SIZE=0x15800
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
# option ROM_IMAGE_SIZE=0x15800
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=FAILOVER_SIZE
option XIP_ROM_SIZE=FAILOVER_SIZE
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover"
-#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
+#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
#
###
### Compute the location and size of where this firmware image
-### (linuxBIOS plus bootloader) will live in the boot rom chip.
+### (coreboot plus bootloader) will live in the boot rom chip.
###
#option FALLBACK_SIZE=524288
#option FALLBACK_SIZE=98304
option FALLBACK_SIZE=131072
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
option ROM_IMAGE_SIZE=65536
###
-### Compute where this copy of linuxBIOS will start in the boot rom
+### Compute where this copy of coreboot will start in the boot rom
###
#
###
option TTYS0_BAUD=115200
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
#
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
option _RAMBASE=0x004000
##
#
###
### Compute the start location and size size of
-### The linuxBIOS bootloader.
+### The coreboot bootloader.
###
option CONFIG_ROM_PAYLOAD = 1
# option ROM_SIZE = 512*1024-48*1024
# 48K for SCSI FW and 48K for ATI ROM
# option ROM_SIZE = 512*1024-48*1024-48*1024
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
option USE_FALLBACK_IMAGE=0
option ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
option ROM_SECTION_OFFSET= 0
end
romimage "fallback"
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
option USE_FALLBACK_IMAGE=1
option ROM_SECTION_SIZE = FALLBACK_SIZE
option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE)
# payload /usr/src/filo-0.4.2/filo.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
#
###
### Compute the location and size of where this firmware image
-### (linuxBIOS plus bootloader) will live in the boot rom chip.
+### (coreboot plus bootloader) will live in the boot rom chip.
###
#option FALLBACK_SIZE=524288
#option FALLBACK_SIZE=98304
option FALLBACK_SIZE=131072
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
option ROM_IMAGE_SIZE=65536
###
-### Compute where this copy of linuxBIOS will start in the boot rom
+### Compute where this copy of coreboot will start in the boot rom
###
#
###
option TTYS0_BAUD=115200
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
#
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
option _RAMBASE=0x004000
##
#
###
### Compute the start location and size size of
-### The linuxBIOS bootloader.
+### The coreboot bootloader.
###
option CONFIG_ROM_PAYLOAD = 1
# option ROM_SIZE = 512*1024-48*1024
# 48K for SCSI FW and 48K for ATI ROM
# option ROM_SIZE = 512*1024-48*1024-48*1024
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
option USE_FALLBACK_IMAGE=0
option ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
option ROM_SECTION_OFFSET= 0
end
romimage "fallback"
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
option USE_FALLBACK_IMAGE=1
option ROM_SECTION_SIZE = FALLBACK_SIZE
option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE)
# payload /usr/src/filo-0.4.2/filo.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x16000
- option LINUXBIOS_EXTRA_VERSION=".0Normal"
+ option COREBOOT_EXTRA_VERSION=".0Normal"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
# payload ../../../../../lnxieepro100.ebi
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x16000
- option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+ option COREBOOT_EXTRA_VERSION=".0Fallback"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
# payload ../../../../../lnxieepro100.ebia
payload /tmp/filo.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
## Exception vectors (other than reset vector)
option _EXCEPTION_VECTORS=_RESET+0x100
- ## Start of linuxBIOS in the boot rom
+ ## Start of coreboot in the boot rom
## = _RESET + exeception vector table size
option _ROMSTART=_RESET+0x3100
- ## LinuxBIOS C code runs at this location in RAM
+ ## Coreboot C code runs at this location in RAM
option _RAMBASE=0x00100000
option _RAMSTART=0x00100000
end
-buildrom ./linuxbios.rom ROM_SIZE "normal"
+buildrom ./coreboot.rom ROM_SIZE "normal"
## Exception vectors (other than reset vector)
option _EXCEPTION_VECTORS=_RESET+0x100
- ## Start of linuxBIOS in the boot rom
+ ## Start of coreboot in the boot rom
## = _RESET + exeception vector table size
option _ROMSTART=_RESET+0x3100
- ## LinuxBIOS C code runs at this location in RAM
+ ## Coreboot C code runs at this location in RAM
option _RAMBASE=0x00100000
option _RAMSTART=0x00100000
option CONFIG_SANDPOINT_ALTIMUS=1
end
-buildrom ./linuxbios.rom ROM_SIZE "normal"
+buildrom ./coreboot.rom ROM_SIZE "normal"
## Exception vectors (other than reset vector)
option _EXCEPTION_VECTORS=_RESET+0x100
- ## Start of linuxBIOS in the boot rom
+ ## Start of coreboot in the boot rom
## = _RESET + exeception vector table size
option _ROMSTART=_RESET+0x3100
- ## LinuxBIOS C code runs at this location in RAM
+ ## Coreboot C code runs at this location in RAM
option _RAMBASE=0x00100000
option _RAMSTART=0x00100000
mainboard motorola/sandpoint
end
-buildrom ./linuxbios.rom ROM_SIZE "normal"
+buildrom ./coreboot.rom ROM_SIZE "normal"
romimage "normal"
option USE_FALLBACK_IMAGE = 0
- option LINUXBIOS_EXTRA_VERSION = ".0Normal"
+ option COREBOOT_EXTRA_VERSION = ".0Normal"
payload /tmp/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
- option LINUXBIOS_EXTRA_VERSION = ".0Fallback"
+ option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload /tmp/filo.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
option USE_FALLBACK_IMAGE = 0
option ROM_IMAGE_SIZE = 128 * 1024
option XIP_ROM_SIZE = 256 * 1024
- option LINUXBIOS_EXTRA_VERSION = ".0Normal"
+ option COREBOOT_EXTRA_VERSION = ".0Normal"
payload __PAYLOAD__
end
option USE_FALLBACK_IMAGE = 1
option ROM_IMAGE_SIZE = 128 * 1024
option XIP_ROM_SIZE = 256 * 1024
- option LINUXBIOS_EXTRA_VERSION = ".0Fallback"
+ option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload __PAYLOAD__
end
option USE_FALLBACK_IMAGE = 0
option ROM_IMAGE_SIZE = FAILOVER_SIZE
option XIP_ROM_SIZE = FAILOVER_SIZE
- option LINUXBIOS_EXTRA_VERSION = ".0Failover"
+ option COREBOOT_EXTRA_VERSION = ".0Failover"
end
-# buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover"
+# buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
option USE_FALLBACK_IMAGE = 0
option ROM_IMAGE_SIZE = 128 * 1024
option XIP_ROM_SIZE = 256 * 1024
- option LINUXBIOS_EXTRA_VERSION = ".0Normal"
+ option COREBOOT_EXTRA_VERSION = ".0Normal"
payload /tmp/filo.elf
end
option USE_FALLBACK_IMAGE = 1
option ROM_IMAGE_SIZE = 128 * 1024
option XIP_ROM_SIZE = 256 * 1024
- option LINUXBIOS_EXTRA_VERSION = ".0Fallback"
+ option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload /tmp/filo.elf
end
option USE_FALLBACK_IMAGE = 0
option ROM_IMAGE_SIZE = FAILOVER_SIZE
option XIP_ROM_SIZE = FAILOVER_SIZE
- option LINUXBIOS_EXTRA_VERSION = ".0Failover"
+ option COREBOOT_EXTRA_VERSION = ".0Failover"
end
-# buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover"
+# buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE = 96 * 1024
- option LINUXBIOS_EXTRA_VERSION=".0-normal"
+ option COREBOOT_EXTRA_VERSION=".0-normal"
payload __PAYLOAD__
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE = 96 * 1024
- option LINUXBIOS_EXTRA_VERSION=".0-fallback"
+ option COREBOOT_EXTRA_VERSION=".0-fallback"
payload __PAYLOAD__
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
option ROM_IMAGE_SIZE=0x20000
# option ROM_IMAGE_SIZE=0x15800
option XIP_ROM_SIZE=0x40000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
option ROM_IMAGE_SIZE=0x20000
# option ROM_IMAGE_SIZE=0x15800
option XIP_ROM_SIZE=0x40000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE = 96 * 1024
- option LINUXBIOS_EXTRA_VERSION=".0-normal"
+ option COREBOOT_EXTRA_VERSION=".0-normal"
payload __PAYLOAD__
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE = 96 * 1024
- option LINUXBIOS_EXTRA_VERSION=".0-fallback"
+ option COREBOOT_EXTRA_VERSION=".0-fallback"
payload __PAYLOAD__
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
option ROM_IMAGE_SIZE=0x20000
# option ROM_IMAGE_SIZE=0x15800
option XIP_ROM_SIZE=0x40000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
option ROM_IMAGE_SIZE=0x20000
# option ROM_IMAGE_SIZE=0x15800
option XIP_ROM_SIZE=0x40000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
option FALLBACK_SIZE=131072
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
option _RAMBASE=0x00004000
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION="-Khepri-Normal"
+ option COREBOOT_EXTRA_VERSION="-Khepri-Normal"
payload ../../../payloads/tg3--ide_disk.zelf
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION="-Khepri-Fallback"
+ option COREBOOT_EXTRA_VERSION="-Khepri-Fallback"
payload ../../../payloads/tg3--ide_disk.zelf
end
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x40000
- option LINUXBIOS_EXTRA_VERSION=".0-Normal"
+ option COREBOOT_EXTRA_VERSION=".0-Normal"
payload __PAYLOAD__
end
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x40000
- option LINUXBIOS_EXTRA_VERSION=".0-Fallback"
+ option COREBOOT_EXTRA_VERSION=".0-Fallback"
payload __PAYLOAD__
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
option ROM_IMAGE_SIZE=0x20000
# option ROM_IMAGE_SIZE=0x15800
option XIP_ROM_SIZE=0x40000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
option ROM_IMAGE_SIZE=0x20000
# option ROM_IMAGE_SIZE=0x15800
option XIP_ROM_SIZE=0x40000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=FAILOVER_SIZE
option XIP_ROM_SIZE=FAILOVER_SIZE
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
end
-#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover"
+#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
# option ROM_IMAGE_SIZE=0x15800
# option ROM_IMAGE_SIZE=0x13800
option XIP_ROM_SIZE=0x40000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=FAILOVER_SIZE
option XIP_ROM_SIZE=FAILOVER_SIZE
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
end
-buildrom ./linuxbios.rom ROM_SIZE "fallback" "failover"
-#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "fallback" "failover"
+#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
target btest
mainboard olpc/btest
-# Don't let LinuxBIOS compress the payload
+# Don't let coreboot compress the payload
#option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
#option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
#option CONFIG_PRECOMPRESSED_PAYLOAD=0
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=32*1024
- option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+ option COREBOOT_EXTRA_VERSION=".0Fallback"
payload /tmp/olpcpayload.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "fallback"
+buildrom ./coreboot.rom ROM_SIZE "fallback"
target rev_a_1M
mainboard olpc/rev_a
-# Don't let LinuxBIOS compress the payload
+# Don't let coreboot compress the payload
# option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
#option CONFIG_PRECOMPRESSED_PAYLOAD=1
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=32*1024
- option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+ option COREBOOT_EXTRA_VERSION=".0Fallback"
payload /tmp/olpcpayload.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "fallback"
+buildrom ./coreboot.rom ROM_SIZE "fallback"
target rev_a_1M
mainboard olpc/rev_a
-# Don't let LinuxBIOS compress the payload
+# Don't let coreboot compress the payload
#option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
#option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
#option CONFIG_PRECOMPRESSED_PAYLOAD=0
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=32*1024
- option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+ option COREBOOT_EXTRA_VERSION=".0Fallback"
payload /tmp/olpcpayload.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "fallback"
+buildrom ./coreboot.rom ROM_SIZE "fallback"
#romimage "normal"
# option USE_FALLBACK_IMAGE=0
# option ROM_IMAGE_SIZE=0x10000
-# option LINUXBIOS_EXTRA_VERSION=".0Normal"
+# option COREBOOT_EXTRA_VERSION=".0Normal"
## payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
## payload ../../../../tg3--ide_disk.zelf
## payload ../../../../../lnxieepro100.ebi
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x10000
- option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+ option COREBOOT_EXTRA_VERSION=".0Fallback"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
# payload ../../../../../lnxieepro100.ebia
payload /tmp/olpc
end
-buildrom ./linuxbios.rom ROM_SIZE "fallback"
-#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "fallback"
+#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=32*1024
- option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+ option COREBOOT_EXTRA_VERSION=".0Fallback"
payload /tmp/olpcpayload.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "fallback"
+buildrom ./coreboot.rom ROM_SIZE "fallback"
option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
-## ROM_SIZE is the total number of bytes allocated for LinuxBIOS use
+## ROM_SIZE is the total number of bytes allocated for coreboot use
## (normal AND fallback images and payloads). Leave 36k for VSA.
option ROM_SIZE = (512 * 1024) - (36 * 1024)
-## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a LinuxBIOS image,
+## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
## not including any payload.
option ROM_IMAGE_SIZE = (64 * 1024)
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
- option LINUXBIOS_EXTRA_VERSION = ".0Fallback"
+ option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload ../payload.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "fallback"
+buildrom ./coreboot.rom ROM_SIZE "fallback"
option ROM_IMAGE_SIZE=0x20000
# option ROM_IMAGE_SIZE=0x17800
option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
option ROM_IMAGE_SIZE=0x20000
# option ROM_IMAGE_SIZE=0x17800
option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
option USE_FAILOVER_IMAGE=0
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x18000
- option LINUXBIOS_EXTRA_VERSION=".0-normal"
+ option COREBOOT_EXTRA_VERSION=".0-normal"
payload __PAYLOAD__
end
option USE_FAILOVER_IMAGE=0
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x18000
- option LINUXBIOS_EXTRA_VERSION=".0-fallback"
+ option COREBOOT_EXTRA_VERSION=".0-fallback"
payload __PAYLOAD__
end
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=FAILOVER_SIZE
option XIP_ROM_SIZE=FAILOVER_SIZE
- option LINUXBIOS_EXTRA_VERSION=".0-failover"
+ option COREBOOT_EXTRA_VERSION=".0-failover"
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
option ROM_IMAGE_SIZE=0x20000
# option ROM_IMAGE_SIZE=0x15800
option XIP_ROM_SIZE=0x40000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
option ROM_IMAGE_SIZE=0x20000
# option ROM_IMAGE_SIZE=0x15800
option XIP_ROM_SIZE=0x40000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=FAILOVER_SIZE
option XIP_ROM_SIZE=FAILOVER_SIZE
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
end
-#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover"
+#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
# option ROM_IMAGE_SIZE=0x15800
# option ROM_IMAGE_SIZE=0x13800
option XIP_ROM_SIZE=0x40000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=FAILOVER_SIZE
option XIP_ROM_SIZE=FAILOVER_SIZE
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
end
-buildrom ./linuxbios.rom ROM_SIZE "fallback" "failover"
-#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "fallback" "failover"
+#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
option USE_FALLBACK_IMAGE=1
# option ROM_IMAGE_SIZE=32 * 1024 # 0x8000
option ROM_IMAGE_SIZE=128 * 1024 # 0x10000
- option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+ option COREBOOT_EXTRA_VERSION=".0Fallback"
payload __PAYLOAD__
end
-buildrom ./linuxbios.rom ROM_SIZE "fallback"
+buildrom ./coreboot.rom ROM_SIZE "fallback"
#romimage "normal"
# option USE_FALLBACK_IMAGE=0
# option ROM_IMAGE_SIZE=0x10000
-# option LINUXBIOS_EXTRA_VERSION=".0-Normal"
+# option COREBOOT_EXTRA_VERSION=".0-Normal"
# payload /etc/hosts
#end
# option ROM_IMAGE_SIZE=48 * 1024 # 0x8000
# option ROM_IMAGE_SIZE=64 * 1024 # 0x10000
# option ROM_IMAGE_SIZE=512 * 1024 # 0x10000
-# option LINUXBIOS_EXTRA_VERSION=".0-Fallback"
- option LINUXBIOS_EXTRA_VERSION=".0"
+# option COREBOOT_EXTRA_VERSION=".0-Fallback"
+ option COREBOOT_EXTRA_VERSION=".0"
payload /home/stepan/filo-ts5300.elf
end
## Exception vectors (other than reset vector)
option _EXCEPTION_VECTORS=_RESET+0x100
- ## Start of linuxBIOS in the boot rom
+ ## Start of coreboot in the boot rom
## = _RESET + exeception vector table size
option _ROMSTART=_RESET+0x3100
- ## LinuxBIOS C code runs at this location in RAM
+ ## Coreboot C code runs at this location in RAM
option _RAMBASE=0x00100000
option _RAMSTART=0x00100000
end
-buildrom ./linuxbios.rom ROM_SIZE "normal"
+buildrom ./coreboot.rom ROM_SIZE "normal"
romimage "normal"
option USE_FALLBACK_IMAGE = 0
- option LINUXBIOS_EXTRA_VERSION = ".0Normal"
+ option COREBOOT_EXTRA_VERSION = ".0Normal"
payload /tmp/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
- option LINUXBIOS_EXTRA_VERSION = ".0Fallback"
+ option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload /tmp/filo.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x11800
option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x11800
option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
TYANMB=s2735
cd "$TYANMB"
make
-#cat ../fwx.rom ../atix.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom"
-#cat ../fwx.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom"
-cat ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom"
-cp -f $TYANMB"_linuxbios.rom" /home/yhlu/
+#cat ../fwx.rom ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
+#cat ../fwx.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
+cat ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
+cp -f $TYANMB"_coreboot.rom" /home/yhlu/
# option ROM_IMAGE_SIZE=0x13c00
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
# option ROM_IMAGE_SIZE=0x13c00
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
TYANMB=s2850
cd "$TYANMB"
make
-cat ../atix.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom"
-#cat ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom"
-#cp -f $TYANMB"_linuxbios.rom" /home/yhlu/
+cat ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
+#cat ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
+#cp -f $TYANMB"_coreboot.rom" /home/yhlu/
# option ROM_IMAGE_SIZE=0x17800
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
# option ROM_IMAGE_SIZE=0x17800
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
TYANMB=s2875
cd "$TYANMB"
make
-cat ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom"
-cp -f $TYANMB"_linuxbios.rom" /home/yhlu/
+cat ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
+cp -f $TYANMB"_coreboot.rom" /home/yhlu/
option ROM_IMAGE_SIZE=0x20000
# option ROM_IMAGE_SIZE=0x17800
option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
option ROM_IMAGE_SIZE=0x20000
# option ROM_IMAGE_SIZE=0x17800
option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
TYANMB=s2880
cd "$TYANMB"
make
-#cat ../fwx.rom ../atix.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom"
-#cat ../fwx.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom"
-cat ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom"
-cp -f $TYANMB"_linuxbios.rom" /home/yhlu/
+#cat ../fwx.rom ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
+#cat ../fwx.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
+cat ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
+cp -f $TYANMB"_coreboot.rom" /home/yhlu/
# option ROM_IMAGE_SIZE=0x16000
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
# option ROM_IMAGE_SIZE=0x16000
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
TYANMB=s2881
cd "$TYANMB"
make
-#cat ../fwx.rom ../atix.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom"
-cat ../fwx.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom"
-#cat ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom"
-cp -f $TYANMB"_linuxbios.rom" /home/yhlu/
+#cat ../fwx.rom ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
+cat ../fwx.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
+#cat ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
+cp -f $TYANMB"_coreboot.rom" /home/yhlu/
# option ROM_IMAGE_SIZE=0x16000
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
# option ROM_IMAGE_SIZE=0x16000
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
TYANMB=s2882
cd "$TYANMB"
make
-#cat ../fwx.rom ../atix.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom"
-#cat ../fwx.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom"
-cat ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom"
-cp -f $TYANMB"_linuxbios.rom" /home/yhlu/
+#cat ../fwx.rom ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
+#cat ../fwx.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
+cat ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
+cp -f $TYANMB"_coreboot.rom" /home/yhlu/
# option ROM_IMAGE_SIZE=0x16200
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
# option ROM_IMAGE_SIZE=0x16200
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
TYANMB=s2885
cd "$TYANMB"
make
-cat ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom"
-cp -f $TYANMB"_linuxbios.rom" /home/yhlu/
+cat ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
+cp -f $TYANMB"_coreboot.rom" /home/yhlu/
# option ROM_IMAGE_SIZE=0x16000
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
# option ROM_IMAGE_SIZE=0x16000
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
# option ROM_IMAGE_SIZE=0x13000
option ROM_IMAGE_SIZE=0x15800
option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
# option ROM_IMAGE_SIZE=0x13000
option ROM_IMAGE_SIZE=0x15800
option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
option ROM_IMAGE_SIZE=0x20000
# option ROM_IMAGE_SIZE=0x17800
option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
option ROM_IMAGE_SIZE=0x20000
# option ROM_IMAGE_SIZE=0x17800
option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
option ROM_IMAGE_SIZE=0x20000
# option ROM_IMAGE_SIZE=0x17800
option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
option ROM_IMAGE_SIZE=0x20000
# option ROM_IMAGE_SIZE=0x17800
option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=FAILOVER_SIZE
option XIP_ROM_SIZE=FAILOVER_SIZE
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover"
-#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
+#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x40000
- option LINUXBIOS_EXTRA_VERSION=".0-Normal"
+ option COREBOOT_EXTRA_VERSION=".0-Normal"
payload __PAYLOAD__
end
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x40000
- option LINUXBIOS_EXTRA_VERSION=".0-Fallback"
+ option COREBOOT_EXTRA_VERSION=".0-Fallback"
payload __PAYLOAD__
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
option ROM_IMAGE_SIZE=0x20000
# option ROM_IMAGE_SIZE=0x15800
option XIP_ROM_SIZE=0x40000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
option ROM_IMAGE_SIZE=0x20000
# option ROM_IMAGE_SIZE=0x15800
option XIP_ROM_SIZE=0x40000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=FAILOVER_SIZE
option XIP_ROM_SIZE=FAILOVER_SIZE
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
end
-#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover"
+#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
# option ROM_IMAGE_SIZE=0x15800
# option ROM_IMAGE_SIZE=0x13800
option XIP_ROM_SIZE=0x40000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=FAILOVER_SIZE
option XIP_ROM_SIZE=FAILOVER_SIZE
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
end
-buildrom ./linuxbios.rom ROM_SIZE "fallback" "failover"
-#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "fallback" "failover"
+#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
# option ROM_IMAGE_SIZE=0x19c00
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
# option ROM_IMAGE_SIZE=0x19c00
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
TYANMB=s4880
cd "$TYANMB"
make
-#cat ../fwx.rom ../atix.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom"
-cat ../fwx.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom"
-#cat ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom"
-cp -f $TYANMB"_linuxbios.rom" /home/yhlu/
+#cat ../fwx.rom ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
+cat ../fwx.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
+#cat ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
+cp -f $TYANMB"_coreboot.rom" /home/yhlu/
# option ROM_IMAGE_SIZE=0x16200
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
# option ROM_IMAGE_SIZE=0x16200
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
TYANMB=s4882
cd "$TYANMB"
make
-#cat ../fwx.rom ../atix.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom"
-cat ../fwx.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom"
-#cat ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom"
-cp -f $TYANMB"_linuxbios.rom" /home/yhlu/
+#cat ../fwx.rom ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
+cat ../fwx.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
+#cat ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
+cp -f $TYANMB"_coreboot.rom" /home/yhlu/
###
### Compute the location and size of where this firmware image
-### (linuxBIOS plus bootloader) will live in the boot rom chip.
+### (coreboot plus bootloader) will live in the boot rom chip.
###
option FALLBACK_SIZE=131072
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
option _RAMBASE=0x00004000
#
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=64*1024
- option LINUXBIOS_EXTRA_VERSION=".0-Normal"
+ option COREBOOT_EXTRA_VERSION=".0-Normal"
payload __PAYLOAD__
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=64*1024
- option LINUXBIOS_EXTRA_VERSION=".0-Fallback"
+ option COREBOOT_EXTRA_VERSION=".0-Fallback"
payload __PAYLOAD__
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
###
### Compute the location and size of where this firmware image
-### (linuxBIOS plus bootloader) will live in the boot rom chip.
+### (coreboot plus bootloader) will live in the boot rom chip.
###
option FALLBACK_SIZE=131072
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
option _RAMBASE=0x00004000
#
###
### Compute the start location and size size of
-### The linuxBIOS bootloader.
+### The coreboot bootloader.
###
#
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x10000
- option LINUXBIOS_EXTRA_VERSION=".0Normal"
+ option COREBOOT_EXTRA_VERSION=".0Normal"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
payload ../../../../../lnxieepro100.ebi
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x10000
- option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+ option COREBOOT_EXTRA_VERSION=".0Fallback"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
payload ../../../../../lnxieepro100.ebi
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
###
### Compute the location and size of where this firmware image
-### (linuxBIOS plus bootloader) will live in the boot rom chip.
+### (coreboot plus bootloader) will live in the boot rom chip.
###
option FALLBACK_SIZE=131072
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
option _RAMBASE=0x00004000
#
###
### Compute the start location and size size of
-### The linuxBIOS bootloader.
+### The coreboot bootloader.
###
#
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x10000
- option LINUXBIOS_EXTRA_VERSION=".0Normal"
+ option COREBOOT_EXTRA_VERSION=".0Normal"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
payload ../../../../../lnxieepro100.ebi
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x10000
- option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+ option COREBOOT_EXTRA_VERSION=".0Fallback"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
payload ../../../../../lnxieepro100.ebi
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
###
### Compute the location and size of where this firmware image
-### (linuxBIOS plus bootloader) will live in the boot rom chip.
+### (coreboot plus bootloader) will live in the boot rom chip.
###
option FALLBACK_SIZE=131072
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
option _RAMBASE=0x00004000
#
###
### Compute the start location and size size of
-### The linuxBIOS bootloader.
+### The coreboot bootloader.
###
#
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x10000
- option LINUXBIOS_EXTRA_VERSION=".0Normal"
+ option COREBOOT_EXTRA_VERSION=".0Normal"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
# payload ../../../../../lnxieepro100.ebi
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x10000
- option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+ option COREBOOT_EXTRA_VERSION=".0Fallback"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
# payload ../../../../../lnxieepro100.ebi
payload ../../../../../../filo.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
###
### Compute the location and size of where this firmware image
-### (linuxBIOS plus bootloader) will live in the boot rom chip.
+### (coreboot plus bootloader) will live in the boot rom chip.
###
option FALLBACK_SIZE=131072
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
option _RAMBASE=0x00004000
#
option USE_FALLBACK_IMAGE=0
#option ROM_IMAGE_SIZE=128*1024
option ROM_IMAGE_SIZE=64*1024
- option LINUXBIOS_EXTRA_VERSION=".0-Normal"
+ option COREBOOT_EXTRA_VERSION=".0-Normal"
payload $(HOME)/svn/payload.elf
end
option USE_FALLBACK_IMAGE=1
#option ROM_IMAGE_SIZE=128*1024
option ROM_IMAGE_SIZE=60*1024
- option LINUXBIOS_EXTRA_VERSION=".0-Fallback"
+ option COREBOOT_EXTRA_VERSION=".0-Fallback"
payload $(HOME)/svn/payload.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
###
### Compute the location and size of where this firmware image
-### (linuxBIOS plus bootloader) will live in the boot rom chip.
+### (coreboot plus bootloader) will live in the boot rom chip.
###
option FALLBACK_SIZE=0x18000
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
option _RAMBASE=0x00004000
###
### Compute the start location and size size of
-### The linuxBIOS bootloader.
+### The coreboot bootloader.
###
#
option ROM_IMAGE_SIZE=0xc000
option ROM_SECTION_OFFSET=0x10000
option ROM_SECTION_SIZE=0x18000
- option LINUXBIOS_EXTRA_VERSION=".0-Normal"
+ option COREBOOT_EXTRA_VERSION=".0-Normal"
payload $(HOME)/svn/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0xc000
- option LINUXBIOS_EXTRA_VERSION=".0-Fallback"
+ option COREBOOT_EXTRA_VERSION=".0-Fallback"
payload $(HOME)/svn/filo.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x10000
- option LINUXBIOS_EXTRA_VERSION=".0Normal"
+ option COREBOOT_EXTRA_VERSION=".0Normal"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
payload ../../../../../lnxieepro100.ebi
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x10000
- option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+ option COREBOOT_EXTRA_VERSION=".0Fallback"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
payload ../../../../../lnxieepro100.ebi
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=64*1024
- option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+ option COREBOOT_EXTRA_VERSION=".0Fallback"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
payload /tmp/linux.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "fallback"
+buildrom ./coreboot.rom ROM_SIZE "fallback"
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x10000
- option LINUXBIOS_EXTRA_VERSION=".0Normal"
+ option COREBOOT_EXTRA_VERSION=".0Normal"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
# payload ../../../../../lnxieepro100.ebi
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x10000
- option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+ option COREBOOT_EXTRA_VERSION=".0Fallback"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
# payload ../../../../../lnxieepro100.ebi
payload /tmp/filo.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x10000
- option LINUXBIOS_EXTRA_VERSION=".0Normal"
+ option COREBOOT_EXTRA_VERSION=".0Normal"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
# payload ../../../../../lnxieepro100.ebi
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x10000
- option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+ option COREBOOT_EXTRA_VERSION=".0Fallback"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
# payload ../../../../../lnxieepro100.ebi
payload /tmp/filo.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x10000
- option LINUXBIOS_EXTRA_VERSION=".0Normal"
+ option COREBOOT_EXTRA_VERSION=".0Normal"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
# payload ../../../../../lnxieepro100.ebi
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x10000
- option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+ option COREBOOT_EXTRA_VERSION=".0Fallback"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
# payload ../../../../../lnxieepro100.ebi
payload /etc/hosts
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Boch's bios related issues. Thanks!
I also got tips from Eric W. Biederman, as well as other members of the
-LinuxBIOS mailing list.
+coreboot mailing list.
the bochs mainline.
thus when designing an patch for rombios.c both needs of
- linuxbios as well as bochs needed to be taken into
+ coreboot as well as bochs needed to be taken into
consideration.
- there are motherboard specific code in loader.s. until this issue
-1) Are you familar with LinuxBIOS?
+1) Are you familar with coreboot?
no : abort
yes: go to next step.
make
-9) use the resulting elf "payload" file with LinuxBIOS as you would
+9) use the resulting elf "payload" file with coreboot as you would
have used any other elf file. For example put it on the same
- EERPOM as LinuxBIOS is, or use EtherBOOT to load the payload
+ EERPOM as coreboot is, or use EtherBOOT to load the payload
file from hdd or network.
ADLO
- A project to combine LinuxBIOS and BOCHS BIOS to add support
+ A project to combine coreboot and BOCHS BIOS to add support
for booting legacy applications, such as Microsoft Windows.
==========================================
Boot Overvew:
ADLO requires an boot loader with ELF support.
- In our case it is either LinuxBIOS or EtherBOOT.
+ In our case it is either coreboot or EtherBOOT.
Sample execution paths:
-LinuxBIOS -> ADLO -> LILO -> LINUX
+coreboot -> ADLO -> LILO -> LINUX
-LinuxBIOS -> EtherBOOT -> ADLO -> LILO -> LINUX
+coreboot -> EtherBOOT -> ADLO -> LILO -> LINUX
Then it can start any real mode application.
In our case it could be LILO or GRUB, but
select device to boot
set memory for Int15/EAX=E820
enable LBA
- copy LinuxBIOS table [TODO]
+ copy coreboot table [TODO]
-shadow :
enable/write/read
-copy:
Environment overview
ADLO is an ELF file and thus can be loaded either directly from 1)
-LinuxBIOS, or 2) via EtherBOOT, or 3) via EtherBOOT+ AA patch for FS
+coreboot, or 2) via EtherBOOT, or 3) via EtherBOOT+ AA patch for FS
support.
1)
-Both LinuxBIOS and ADLO are on the same EEPROM chip. From end-user
+Both coreboot and ADLO are on the same EEPROM chip. From end-user
viewpoint it is probably the most similar to the bios classic.
(computer boots up and just loads whatever is in MBR).
ADLO requires an boot loader with ELF support.
In our case it is:
- -LinuxBIOS
- -LinuxBIOS and EtherBOOT
- -LinuxBIOS and EtherBOOT + AA polled I/O patch (w/ FS support).
+ -coreboot
+ -coreboot and EtherBOOT
+ -coreboot and EtherBOOT + AA polled I/O patch (w/ FS support).
- As little as LinuxBIOS only is required to get ADLO
+ As little as coreboot only is required to get ADLO
up and running.
For development purposes it is recommended full set of
- LinuxBIOS + EtherBOOT and boot via DHCP/TFTP.
+ coreboot + EtherBOOT and boot via DHCP/TFTP.
------------------------------------------
fix bios to properly handle reboot
setup PIRQ table for P6STMT mbo.
- have it extract from linuxbios somehow..
+ have it extract from coreboot somehow..
find it in ram and copy...
hack gcc to support 16 bit real mode.
//#define BX_PCIBIOS 1
#define BX_APM 0
-#define LINUXBIOS 1
+#define COREBOOT 1
#define BX_USE_ATADRV 1
//#define BX_ELTORITO_BOOT 1
//--------------------------------------------------------------------------
// keyboard_init
//--------------------------------------------------------------------------
-// this file is based on LinuxBIOS implementation of keyboard.c
+// this file is based on coreboot implementation of keyboard.c
// could convert to #asm to gain space
void
keyboard_init()
{
-#ifndef LINUXBIOS
+#ifndef COREBOOT
Bit16u max;
/* ------------------- Flush buffers ------------------------*/
;*****************************************************
; A) setup GDT, so that we do not depend on program
; that loaded us for GDT.
-; Ex: LinuxBIOS and EtherBOOT use different GDT's.
+; Ex: coreboot and EtherBOOT use different GDT's.
;-----------------------------------------------------
; 0)
nop
nop
;*****************************************************
-; X) copy -- LinuxBIOS table into safe place.
+; X) copy -- coreboot table into safe place.
;; TODO.
;; Q1 : what is the size of table.
; 119mb = 0x77 00 00 00
; (this is for 128mb of ram)
; (FIXME: this value is currently hard coded)
-; (it should be being passed from LinuxBIOS )
+; (it should be being passed from coreboot )
; for WinFast 6300
; 07 70 = 0770
#!/bin/bash
#
-# LinuxBIOS autobuild
+# coreboot autobuild
#
-# This script builds LinuxBIOS images for all available targets.
+# This script builds coreboot images for all available targets.
#
# (C) 2004 by Stefan Reinauer <stepan@openbios.org>
# (C) 2006 by coresystems GmbH <info@coresystems.de>
ABUILD_VERSION="0.4"
# Where shall we place all the build trees?
-TARGET=$( pwd )/linuxbios-builds
+TARGET=$( pwd )/coreboot-builds
XMLFILE=$( pwd )/abuild.xml
# path to payload. Should be more generic
# Lines of error context to be printed in FAILURE case
CONTEXT=5
-TESTSUBMISSION="http://qa.linuxbios.org/deployment/send.php"
+TESTSUBMISSION="http://qa.coreboot.org/deployment/send.php"
# One might want to adjust these in case of cross compiling
MAKE="make"
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x17000
- option LINUXBIOS_EXTRA_VERSION=".0-normal"
+ option COREBOOT_EXTRA_VERSION=".0-normal"
payload __PAYLOAD__
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x17000
- option LINUXBIOS_EXTRA_VERSION=".0-fallback"
+ option COREBOOT_EXTRA_VERSION=".0-fallback"
payload __PAYLOAD__
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
EOF
else
cat <<EOF
romimage "only"
- option LINUXBIOS_EXTRA_VERSION=".0"
+ option COREBOOT_EXTRA_VERSION=".0"
payload __PAYLOAD__
end
-buildrom ./linuxbios.rom ROM_SIZE "only"
+buildrom ./coreboot.rom ROM_SIZE "only"
EOF
fi
) > $TARGET/Config-${VENDOR}_${MAINBOARD}.lb
fi
# image does not exist. we silently skip the patch.
- if [ ! -r "$TARGET/${VENDOR}_${MAINBOARD}/linuxbios.rom" ]; then
+ if [ ! -r "$TARGET/${VENDOR}_${MAINBOARD}/coreboot.rom" ]; then
return 0
fi
printf "Submitting image for board $VENDOR $MAINBOARD to test system...\n"
- curl -f -F "romfile=@$TARGET/${VENDOR}_${MAINBOARD}/linuxbios.rom" \
+ curl -f -F "romfile=@$TARGET/${VENDOR}_${MAINBOARD}/coreboot.rom" \
-F "mode=abuild" -F "mainboard=${VENDOR}_${MAINBOARD}" -F "submit=Upload" \
- "http://qa.linuxbios.org/deployment/send.php"
+ "http://qa.coreboot.org/deployment/send.php"
printf "\n"
return 0
printf " [-x|--xml] write xml log file \n"
printf " (defaults to $XMLFILE)\n"
printf " [-T|--test] submit image(s) to automated test system\n"
- printf " [lbroot] absolute path to LinuxBIOS sources\n"
+ printf " [lbroot] absolute path to coreboot sources\n"
printf " (defaults to $LBROOT)\n\n"
}
{
cat << EOF
-LinuxBIOS autobuild v$ABUILD_VERSION ($ABUILD_DATE)
+coreboot autobuild v$ABUILD_VERSION ($ABUILD_DATE)
Copyright (C) 2004 by Stefan Reinauer <stepan@openbios.org>
-Copyright (C) 2006 by coresystems GmbH <info@coresystems.de>
+Copyright (C) 2006-2008 by coresystems GmbH <info@coresystems.de>
This program is free software; you may redistribute it under the terms
of the GNU General Public License. This program has absolutely no
.TH ABUILD 1 "October 24, 2006"
.SH NAME
-abuild \- build LinuxBIOS images for all available targets
+abuild \- build coreboot images for all available targets
.SH SYNOPSIS
.B abuild
\fR[\fB\-abxVh\fR] [\fB\-t\fR vendor/board] [\fB\-p\fR dir]
[LBROOT]
.SH DESCRIPTION
.B abuild
-is a utility used to easily build LinuxBIOS images for all available targets.
+is a utility used to easily build coreboot images for all available targets.
.SH OPTIONS
The
.B "[LBROOT]"
parameter tells
.B abuild
-where the root directory of the LinuxBIOS build tree resides. Per default
+where the root directory of the coreboot build tree resides. Per default
this is
.B "../.."
as the
.B abuild
script resides in
-.BR "[LBROOT]/utils/abuild" .
+.BR "[CBROOT]/utils/abuild" .
.TP
.B "\-a, \-\-all"
Build previously succeeded ports as well.
.B "\-T, \-\-test"
Submit generated image(s) to the automated test system.
The results of the tests will be made available at
-.B http://qa.linuxbios.org/log_manual.php
+.B http://qa.coreboot.org/log_manual.php
.TP
.B "\-v, \-\-verbose"
More verbose output.
.B "\-V, \-\-version"
Show version information and exit.
.SH BUGS
-Please report any bugs at http://tracker.linuxbios.org/.
+Please report any bugs at http://tracker.coreboot.org/.
.SH LICENCE
.B abuild
is covered by the GNU General Public License (GPL), version 2 or later.
-# LinuxBIOS codebase analysis tool
+# Coreboot codebase analysis tool
#
# This makefile collects source usage information for all working targets.
#
analysis.dat: analysis.txt
@ echo Writing gnuplot data file \($@\).
@ echo -e > $@ "# gnuplot dataset auto-generated $(shell date)" \
- "\nset title \"LinuxBIOS Codebase Analysis\"" \
+ "\nset title \"Coreboot Codebase Analysis\"" \
"\nset style data boxes" \
"\nset style fill solid .5" \
$(foreach target, $(TARGETS), "\n"set label \"$(target)\" at $(words $(labels))$(eval labels += $(target)),-145 rotate front) \
void usage()
{
fprintf(stderr, "Usage: buildrom <input> <output> <payload> ");
- fprintf(stderr, " <linuxbios-size> <total-size>\n");
+ fprintf(stderr, " <coreboot-size> <total-size>\n");
exit(1);
}
if (fstat(infd, &inbuf) < 0)
fatal("stat of infile");
if (inbuf.st_size > size) {
- fprintf(stderr, "linuxbios image is %d bytes; only %d allowed\n",
+ fprintf(stderr, "coreboot image is %d bytes; only %d allowed\n",
(int)inbuf.st_size, size);
- fatal("Linuxbios input file larger than allowed size!\n");
+ fatal("Coreboot input file larger than allowed size!\n");
}
if (fstat(payloadfd, &payloadbuf) < 0)
fatal("stat of infile");
if (payloadbuf.st_size > (romsize - size)){
- fprintf(stderr, "ERROR: payload (%d) + linuxbios (%d) - Size is %d bytes larger than ROM size (%d).\n",
+ fprintf(stderr, "ERROR: payload (%d) + coreboot (%d) - Size is %d bytes larger than ROM size (%d).\n",
payloadbuf.st_size, size,
payloadbuf.st_size+size-romsize,
romsize);
exit(1);
}
- printf("Payload: %d LinuxBIOS: %d ROM size: %d Left space: %d\n",
+ printf("Payload: %d coreboot: %d ROM size: %d Left space: %d\n",
payloadbuf.st_size, size, romsize,
romsize-payloadbuf.st_size-size);
-lbtdump is a utility to dump the LinuxBIOS table
+lbtdump is a utility to dump the coreboot table
to a human readable form.
This needs to be run as root (or setuid) on a system
-running LinuxBIOS.
+running coreboot.
head->table_checksum);
continue;
}
- fprintf(stdout, "Found LinuxBIOS table at: %08lx\n", addr);
+ fprintf(stdout, "Found coreboot table at: %08lx\n", addr);
return head;
};
rec = (struct lb_record *)(((char *)head) + head->header_bytes);
last = (struct lb_record *)(((char *)rec) + head->table_bytes);
- printf("LinuxBIOS header(%d) checksum: %04x table(%d) checksum: %04x entries: %d\n",
+ printf("Coreboot header(%d) checksum: %04x table(%d) checksum: %04x entries: %d\n",
head->header_bytes, head->header_checksum,
head->table_bytes, head->table_checksum, head->table_entries);
print_lb_records(rec, last, addr + head->header_bytes);
# -----------------------------------------------------------------------------
class romimage:
- """A rom image is the ultimate goal of linuxbios"""
+ """A rom image is the ultimate goal of coreboot"""
def __init__ (self, name):
# name of this rom image
self.name = name
writemakefileheader(file, makefilepath)
# main rule
- file.write("\nall: linuxbios.rom\n\n")
+ file.write("\nall: coreboot.rom\n\n")
file.write(".PHONY: all\n\n")
#file.write("include cpuflags\n")
# Putting "include cpuflags" in the Makefile has the problem that the
for genfile in ['Makefile',
'nsuperio.c',
'static.c',
- 'LinuxBIOSDoc.config' ]:
+ 'corebootDoc.config' ]:
file.write("GENERATED += %s\n" % genfile)
file.write("GENERATED += %s\n" % image.getincludefilename())
file.write("\n\n")
file.write("include Makefile.settings\n\n")
for i, o in romimages.items():
- file.write("%s/linuxbios.rom:\n" % o.getname())
+ file.write("%s/coreboot.rom:\n" % o.getname())
file.write("\tif (cd %s; \\\n" % o.getname())
- file.write("\t\tmake linuxbios.rom)\\\n")
+ file.write("\t\tmake coreboot.rom)\\\n")
file.write("\tthen true; else exit 1; fi;\n\n")
file.write("clean: ")
for i in romimages.keys():
for i in buildroms:
file.write("%s:" % i.name)
for j in i.roms:
- file.write(" %s/linuxbios.rom " % j)
+ file.write(" %s/coreboot.rom " % j)
file.write("\n")
file.write("\t cat ")
for j in i.roms:
- file.write(" %s/linuxbios.rom " % j)
+ file.write(" %s/coreboot.rom " % j)
file.write("> %s\n\n" %i.name)
for i in romimages.keys():
file.write(" %s-clean" % i)
for i, o in romimages.items():
- file.write(" %s/linuxbios.rom" % o.getname())
+ file.write(" %s/coreboot.rom" % o.getname())
file.write("\n\n")
writemakefilefooter(file, makefilepath)
if __name__=='__main__':
from sys import argv
if (len(argv) < 3):
- fatal("Args: <file> <path to linuxbios>")
+ fatal("Args: <file> <path to coreboot>")
top_config_file = os.path.abspath(sys.argv[1])
indent="yes" />
<xsl:template match="/">
-This is an automatically generated list of '''LinuxBIOS compile-time options'''.
+This is an automatically generated list of '''coreboot compile-time options'''.
Last update: <xsl:value-of select="//creationdate"/>.
<xsl:template match="/">
<html>
<head>
-<title>LinuxBIOS Options</title>
+<title>Coreboot Options</title>
</head>
<body>
-<h2>LinuxBIOS Options</h2>
-<p>This is an automatically generated list of LinuxBIOS compile time
+<h2>Coreboot Options</h2>
+<p>This is an automatically generated list of coreboot compile time
options. Created at <xsl:value-of select="//creationdate"/>.</p>
<table border="1">
<tr bgcolor="#0975a7">
-I would like to contribute the following to the LinuxBIOS wiki in case
+I would like to contribute the following to the coreboot wiki in case
it's useable:
1. I have written a rather small Python script to convert the Options.lb
input = prepInput(input)
output = parseInput(input)
- print "mkOptionList.py: LinuxBIOS option list generator"
+ print "mkOptionList.py: coreboot option list generator"
print " input file : ", inFilename
print " output file: ", outFilename
is a C compiler which produces binaries which do not rely on RAM, but
instead only use CPU registers.
.PP
-It is prominently used in the LinuxBIOS project to compile C code which
-needs to run before the (Linux)BIOS has initialized the RAM, but can be
+It is prominently used in the coreboot project to compile C code which
+needs to run before the firmware has initialized the RAM, but can be
used for other purposes, too.
.SH OPTIONS
.TP
projects / coreboot.git / commitdiff