1 # Sample config file for
3 # This will make a target directory of ./dk8s2
9 option HAVE_HARD_RESET=1
11 option HAVE_OPTION_TABLE=1
12 option HAVE_MP_TABLE=1
13 option ROM_SIZE=1024*1024
15 option HAVE_FALLBACK_BOOT=1
17 #option CONFIG_LSI_SCSI_FW_FIXUP=1
22 ### Build code to export a programmable irq routing table
24 option HAVE_PIRQ_TABLE=1
25 option IRQ_SLOT_COUNT=12
28 ### Build code for SMP support
29 ### Only worry about 2 micro processors
32 option CONFIG_MAX_CPUS=2
33 #option CONFIG_LOGICAL_CPUS=2
34 option CONFIG_MAX_PHYSICAL_CPUS=2
37 ### Build code to setup a generic IOAPIC
39 option CONFIG_IOAPIC=1
42 ### MEMORY_HOLE instructs earlymtrr.inc to
43 ### enable caching from 0-640KB and to disable
44 ### caching from 640KB-1MB using fixed MTRRs
46 ### Enabling this option breaks SMP because secondary
47 ### CPU identification depends on only variable MTRRs
53 ### Clean up the motherboard id strings
55 option MAINBOARD_PART_NUMBER="DK8S2"
56 option MAINBOARD_VENDOR="IWILL"
59 ### Compute the location and size of where this firmware image
60 ### (coreboot plus bootloader) will live in the boot rom chip.
62 #option FALLBACK_SIZE=524288
63 #option FALLBACK_SIZE=98304
64 option FALLBACK_SIZE=131072
66 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
67 option ROM_IMAGE_SIZE=65536
71 ### Compute where this copy of coreboot will start in the boot rom
76 ## We do use compressed image
77 #option CONFIG_COMPRESS=1
79 option CONFIG_CONSOLE_SERIAL8250=1
80 option TTYS0_BAUD=115200
83 ### Select the coreboot loglevel
85 ## EMERG 1 system is unusable
86 ## ALERT 2 action must be taken immediately
87 ## CRIT 3 critical conditions
88 ## ERR 4 error conditions
89 ## WARNING 5 warning conditions
90 ## NOTICE 6 normal but significant condition
91 ## INFO 7 informational
92 ## DEBUG 8 debug-level messages
93 ## SPEW 9 Way too many details
95 ## Request this level of debugging output
96 option DEFAULT_CONSOLE_LOGLEVEL=7
97 ## At a maximum only compile in this level of debugging
98 option MAXIMUM_CONSOLE_LOGLEVEL=7
104 ## Coreboot C code runs at this location in RAM
105 option _RAMBASE=0x004000
110 option STACK_SIZE=0x8000
115 option HEAP_SIZE=0xe000
119 ### Compute the start location and size size of
120 ### The coreboot bootloader.
122 option CONFIG_ROM_PAYLOAD = 1
128 # option ROM_SIZE = 512*1024-48*1024
129 # 48K for SCSI FW and 48K for ATI ROM
130 # option ROM_SIZE = 512*1024-48*1024-48*1024
131 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
132 option USE_FALLBACK_IMAGE=0
133 option ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
134 option ROM_SECTION_OFFSET= 0
136 option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
137 option CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
138 option _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
140 # option XIP_ROM_SIZE = FALLBACK_SIZE
141 option XIP_ROM_SIZE = 65536
143 option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
145 payload /usr/src/filo-0.4.1_btext/filo.elf
146 # payload /usr/src/filo-0.4.2/filo.elf
150 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
151 option USE_FALLBACK_IMAGE=1
152 option ROM_SECTION_SIZE = FALLBACK_SIZE
153 option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE)
155 option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
156 option CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
157 option _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
159 # option XIP_ROM_SIZE = FALLBACK_SIZE
160 option XIP_ROM_SIZE = 65536
161 option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
163 payload ../../../payloads/filo.elf
164 # payload /usr/src/filo-0.4.2/filo.elf
167 buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"