2 ## Compute the location and size of where this firmware image
3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
6 default ROM_SECTION_SIZE = FALLBACK_SIZE
7 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
9 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
10 default ROM_SECTION_OFFSET = 0
14 ## Compute the start location and size size of
15 ## The linuxBIOS bootloader.
17 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
18 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
21 ## Compute where this copy of linuxBIOS will start in the boot rom
23 default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
26 ## Compute a range of ROM that can cached to speed up linuxBIOS,
29 ## XIP_ROM_SIZE must be a power of 2.
30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
32 default XIP_ROM_SIZE=65536
33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
36 ## Set all of the defaults for an x86 architecture
42 ## Build the objects we have code for in this directory.
46 if HAVE_MP_TABLE object mptable.o end
47 if HAVE_PIRQ_TABLE object irq_tables.o end
55 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
56 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
62 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
63 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
64 action "perl -e 's/.rodata/.rom.data/g' -pi $@"
65 action "perl -e 's/.text/.section .rom.text/g' -pi $@"
74 depends "$(MAINBOARD)/failover.c ./romcc"
75 action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
78 makerule ./failover.inc
79 depends "$(MAINBOARD)/failover.c ./romcc"
80 action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
84 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
85 action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
88 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
89 action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
95 ## Build our 16 bit and 32 bit linuxBIOS entry code
98 mainboardinit cpu/x86/16bit/entry16.inc
99 ldscript /cpu/x86/16bit/entry16.lds
102 mainboardinit cpu/x86/32bit/entry32.inc
106 ldscript /cpu/x86/32bit/entry32.lds
110 ldscript /cpu/amd/car/cache_as_ram.lds
115 ## Build our reset vector (This is where linuxBIOS is entered)
117 if USE_FALLBACK_IMAGE
118 mainboardinit cpu/x86/16bit/reset16.inc
119 ldscript /cpu/x86/16bit/reset16.lds
121 mainboardinit cpu/x86/32bit/reset32.inc
122 ldscript /cpu/x86/32bit/reset32.lds
127 ### Should this be in the northbridge code?
128 mainboardinit arch/i386/lib/cpu_reset.inc
132 ## Include an id string (For safe flashing)
134 mainboardinit arch/i386/lib/id.inc
135 ldscript /arch/i386/lib/id.lds
139 ## Setup Cache-As-Ram
141 mainboardinit cpu/amd/car/cache_as_ram.inc
145 ### This is the early phase of linuxBIOS startup
146 ### Things are delicate and we test to see if we should
147 ### failover to another image.
149 if USE_FALLBACK_IMAGE
151 ldscript /arch/i386/lib/failover.lds
153 ldscript /arch/i386/lib/failover.lds
154 mainboardinit ./failover.inc
159 ### O.k. We aren't just an intermediary anymore!
170 mainboardinit ./auto.inc
178 mainboardinit cpu/x86/fpu/enable_fpu.inc
179 mainboardinit cpu/x86/mmx/enable_mmx.inc
180 mainboardinit cpu/x86/sse/enable_sse.inc
181 mainboardinit ./auto.inc
182 mainboardinit cpu/x86/sse/disable_sse.inc
183 mainboardinit cpu/x86/mmx/disable_mmx.inc
187 ## Include the secondary Configuration files
192 chip northbridge/amd/amdk8/root_complex
193 device apic_cluster 0 on
194 chip cpu/amd/socket_940
199 device pci_domain 0 on
200 chip northbridge/amd/amdk8
201 device pci 18.0 on end # LDT 0
202 device pci 18.0 on # LDT 1
203 chip southbridge/amd/amd8131
204 device pci 0.0 on end
205 device pci 0.1 on end
206 device pci 1.0 on end
207 device pci 1.1 on end
209 chip southbridge/amd/amd8111
211 device pci 0.0 on end
212 device pci 0.1 on end
213 device pci 0.2 on end
214 device pci 1.0 off end
215 chip drivers/pci/onboard
216 device pci 5.0 on end # ATI Rage XL
217 register "rom_address" = "0xfff80000"
221 chip superio/nsc/pc87366
222 device pnp 2e.0 off # Floppy
227 device pnp 2e.1 off # Parallel Port
231 device pnp 2e.2 off # Com 2
235 device pnp 2e.3 on # Com 1
239 device pnp 2e.4 off end # SWC
240 device pnp 2e.5 off end # Mouse
241 device pnp 2e.6 on # Keyboard
246 device pnp 2e.7 off end # GPIO
247 device pnp 2e.8 off end # ACB
248 device pnp 2e.9 off end # FSCM
249 device pnp 2e.a off end # WDT
252 device pci 1.1 on end
253 device pci 1.2 on end
254 device pci 1.3 on end
255 device pci 1.5 off end
256 device pci 1.6 off end
257 register "ide0_enable" = "1"
258 register "ide1_enable" = "1"
260 end # device pci 18.0
261 device pci 18.0 on end # LDT2
262 device pci 18.1 on end
263 device pci 18.2 on end
264 device pci 18.3 on end