src/mainboard/agami/aruma/Config.lb

   1 ##
   2 ## Compute the location and size of where this firmware image
   3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
   4 ##
   5 if USE_FALLBACK_IMAGE
   6         default ROM_SECTION_SIZE   = FALLBACK_SIZE
   7         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
   8 else
   9         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
  10         default ROM_SECTION_OFFSET = 0
  11 end
  12
  13 ##
  14 ## Compute the start location and size size of
  15 ## The linuxBIOS bootloader.
  16 ##
  17 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  18 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  19
  20 ##
  21 ## Compute where this copy of linuxBIOS will start in the boot rom
  22 ##
  23 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
  24
  25 ##
  26 ## Compute a range of ROM that can cached to speed up linuxBIOS,
  27 ## execution speed.
  28 ##
  29 ## XIP_ROM_SIZE must be a power of 2.
  30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  31 ##
  32 default XIP_ROM_SIZE=65536
  33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
  34
  35 arch i386 end
  36
  37 ##
  38 ## Build the objects we have code for in this directory.
  39 ##
  40
  41 driver mainboard.o
  42 if HAVE_MP_TABLE object mptable.o end
  43 if HAVE_PIRQ_TABLE object irq_tables.o end
  44
  45 #needed by irq_tables and mptable and acpi_tables
  46 #object get_bus_conf.o
  47
  48 if HAVE_ACPI_TABLES
  49         object acpi_tables_static.o
  50         object fadt.o
  51
  52         object dsdt.o
  53
  54 #       makerule dsdt.c
  55 #               depends "$(MAINBOARD)/dx/dsdt_lb.dsl"
  56 #               action  "iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
  57 #               action  "mv dsdt_lb.hex dsdt.c"
  58 #       end
  59 #       object ./dsdt.o
  60 #
  61 #       makerule ssdt.c
  62 #               depends "$(MAINBOARD)/ssdt_lb_x.dsl"
  63 #               action  "iasl -tc $(MAINBOARD)/ssdt_lb_x.dsl"
  64 #               action  "perl -pi -e 's/AmlCode/AmlCode_ssdt/g' ssdt_lb_x.hex"
  65 #               action  "mv ssdt_lb_x.hex ssdt.c"
  66 #       end
  67 #       object ./ssdt.o
  68 #
  69 #       if ACPI_SSDTX_NUM
  70 #               makerule ssdt2.c
  71 #                       depends "$(MAINBOARD)/dx/pci2.asl"
  72 #                       action  "iasl -tc $(MAINBOARD)/dx/pci2.asl"
  73 #                       action  "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
  74 #                       action  "mv pci2.hex ssdt2.c"
  75 #               end
  76 #               object ./ssdt2.o
  77 #               makerule ssdt3.c
  78 #                       depends "$(MAINBOARD)/dx/pci3.asl"
  79 #                       action  "iasl -tc $(MAINBOARD)/dx/pci3.asl"
  80 #                       action  "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex"
  81 #                       action  "mv pci3.hex ssdt3.c"
  82 #               end
  83 #               object ./ssdt3.o
  84 #               makerule ssdt4.c
  85 #                       depends "$(MAINBOARD)/dx/pci4.asl"
  86 #                       action  "iasl -tc $(MAINBOARD)/dx/pci4.asl"
  87 #                       action  "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex"
  88 #                       action  "mv pci4.hex ssdt4.c"
  89 #               end
  90 #               object ./ssdt4.o
  91 #
  92 #       end
  93 end
  94
  95
  96
  97 #object reset.o
  98
  99 # FIXME: This should be solved generically.
 100 #object vgabios.o
 101 #driver atiragexl.o
 102
 103 if USE_DCACHE_RAM
 104
 105         if CONFIG_USE_INIT
 106                 # compile cache_as_ram.c to auto.o
 107                 makerule ./cache_as_ram_auto.o
 108                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
 109                         action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o cache_as_ram_auto.o"
 110                 end
 111
 112         else
 113                 #compile cache_as_ram.c to auto.inc
 114                 makerule ./cache_as_ram_auto.inc
 115                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
 116                         action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
 117                         action "perl -e 's/.rodata/.rom.data/g' -pi $@"
 118                         action "perl -e 's/.text/.section .rom.text/g' -pi $@"
 119                 end
 120
 121         end
 122 else
 123
 124         ##
 125         ## Romcc output
 126         ##
 127         makerule ./failover.E
 128                 depends "$(MAINBOARD)/failover.c ./romcc"
 129                 action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 130         end
 131
 132         makerule ./failover.inc
 133                 depends "$(MAINBOARD)/failover.c ./romcc"
 134                 action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 135         end
 136
 137         makerule ./auto.E
 138                 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
 139                 action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 140         end
 141         makerule ./auto.inc
 142                 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
 143                 action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 144         end
 145
 146 end
 147 ##
 148 ## Build our 16 bit and 32 bit linuxBIOS entry code
 149 ##
 150
 151 mainboardinit cpu/x86/16bit/entry16.inc
 152 ldscript /cpu/x86/16bit/entry16.lds
 153
 154 mainboardinit cpu/x86/32bit/entry32.inc
 155 if USE_DCACHE_RAM
 156         if CONFIG_USE_INIT
 157                 ldscript /cpu/x86/32bit/entry32.lds
 158         end
 159
 160         if CONFIG_USE_INIT
 161                 ldscript /cpu/amd/car/cache_as_ram.lds
 162         end
 163 end
 164
 165 ##
 166 ## Build our reset vector (This is where linuxBIOS is entered)
 167 ##
 168 if USE_FALLBACK_IMAGE
 169         mainboardinit cpu/x86/16bit/reset16.inc
 170         ldscript /cpu/x86/16bit/reset16.lds
 171 else
 172         mainboardinit cpu/x86/32bit/reset32.inc
 173         ldscript /cpu/x86/32bit/reset32.lds
 174 end
 175
 176 if USE_DCACHE_RAM
 177 else
 178         ### Should this be in the northbridge code?
 179         mainboardinit arch/i386/lib/cpu_reset.inc
 180 end
 181
 182 ##
 183 ## Include an id string (For safe flashing)
 184 ##
 185 mainboardinit arch/i386/lib/id.inc
 186 ldscript /arch/i386/lib/id.lds
 187
 188 if USE_DCACHE_RAM
 189         ##
 190         ## Setup Cache-As-Ram
 191         ##
 192         mainboardinit cpu/amd/car/cache_as_ram.inc
 193 end
 194
 195 ###
 196 ### This is the early phase of linuxBIOS startup
 197 ### Things are delicate and we test to see if we should
 198 ### failover to another image.
 199 ###
 200 if USE_FALLBACK_IMAGE
 201         if USE_DCACHE_RAM
 202                 ldscript /arch/i386/lib/failover.lds
 203         else
 204                 ldscript /arch/i386/lib/failover.lds
 205                 mainboardinit ./failover.inc
 206         end
 207 end
 208
 209 ###
 210 ### O.k. We aren't just an intermediary anymore!
 211 ###
 212
 213 ##
 214 ## Setup RAM
 215 ##
 216 if USE_DCACHE_RAM
 217
 218         if CONFIG_USE_INIT
 219                 initobject cache_as_ram_auto.o
 220         else
 221                 mainboardinit ./cache_as_ram_auto.inc
 222         end
 223
 224 else
 225
 226         ##
 227         ## Setup RAM
 228         ##
 229         mainboardinit cpu/x86/fpu/enable_fpu.inc
 230         mainboardinit cpu/x86/mmx/enable_mmx.inc
 231         mainboardinit cpu/x86/sse/enable_sse.inc
 232         mainboardinit ./auto.inc
 233         mainboardinit cpu/x86/sse/disable_sse.inc
 234         mainboardinit cpu/x86/mmx/disable_mmx.inc
 235
 236 end
 237
 238 ##
 239 ## Include the secondary Configuration files
 240 ##
 241
 242 dir /pc80
 243
 244 config chip.h
 245
 246 # config for agami/aruma
 247 chip northbridge/amd/amdk8/root_complex
 248         device apic_cluster 0 on
 249                 chip cpu/amd/socket_940
 250                         device apic 0 on end
 251                 end
 252         end
 253         device pci_domain 0 on
 254             chip northbridge/amd/amdk8
 255                 device pci 18.0 on end #  device pci 18.0
 256                 device pci 18.0 on
 257                         #  devices on link 1, link 1 == LDT 1
 258                         chip southbridge/amd/amd8131
 259                                 # the on/off keyword is mandatory
 260                                 device pci 0.0 on end
 261                                 device pci 0.1 on end
 262                                 device pci 1.0 on end
 263                                 device pci 1.1 on end
 264                         end # 8131
 265                         chip southbridge/amd/amd8111
 266                                 # this "device pci 0.0" is the parent the next one
 267                                 # PCI bridge
 268                                 device pci 0.0 on
 269                                         device pci 0.0 on end
 270                                         device pci 0.1 on end
 271                                         device pci 0.2 off end
 272                                         device pci 1.0 off end
 273                                         #chip drivers/ati/ragexl
 274                                         chip drivers/pci/onboard
 275                                                 device pci 4.0 on end
 276                                                 register "rom_address" = "0xfff80000"
 277                                         end
 278                                 end
 279                                 device pci 1.0 on
 280                                         chip superio/winbond/w83627hf
 281                                                device pnp 2e.0 on #  Floppy
 282                                                         io 0x60 = 0x3f0
 283                                                         irq 0x70 = 6
 284                                                         drq 0x74 = 2
 285                                                 end
 286                                                 device pnp 2e.1 off #  Parallel Port
 287                                                         io 0x60 = 0x378
 288                                                         irq 0x70 = 7
 289                                                 end
 290                                                 device pnp 2e.2 on #  Com1
 291                                                         io 0x60 = 0x3f8
 292                                                         irq 0x70 = 4
 293                                                 end
 294                                                 device pnp 2e.3 on #  Com2
 295                                                         io 0x60 = 0x2f8
 296                                                         irq 0x70 = 3
 297                                                 end
 298                                                 device pnp 2e.5 on #  Keyboard
 299                                                         io 0x60 = 0x60
 300                                                         io 0x62 = 0x64
 301                                                         irq 0x70 = 1
 302                                                         irq 0x72 = 12
 303                                                 end
 304                                                 device pnp 2e.6 off #  CIR
 305                                                         io 0x60 = 0x100
 306                                                 end
 307                                                 device pnp 2e.7 off # GAME_MIDI_GIPO1
 308                                                         io 0x60 = 0x201
 309                                                         io 0x62 = 0x330
 310                                                         irq 0x70 = 9
 311                                                 end
 312                                                 device pnp 2e.8 off end # GPIO2
 313                                                 device pnp 2e.9 off end # GPIO3
 314                                                 device pnp 2e.a off end #  ACPI
 315                                                 device pnp 2e.b on #  HW Monitor
 316                                                         io 0x60 = 0x290
 317                                                         irq 0x70 = 5
 318                                                 end
 319                                         end
 320                                 end
 321                                 device pci 1.1 on end
 322                                 device pci 1.2 on end
 323                                 device pci 1.3 on
 324                                         chip drivers/i2c/i2cmux2 # pca9545 smbus mux
 325                                                 device i2c 71 on     #pca9545 channel0
 326                                                         chip drivers/i2c/adm1026
 327                                                                 device i2c 2d on end
 328                                                         end
 329                                                 end
 330                                                 device i2c 71 on     #pca9545 channel1
 331                                                         chip drivers/generic/generic # fan board / pstray behind another mux
 332                                                                 device i2c 2d on end
 333                                                         end
 334                                                 end
 335                                         end
 336                                         chip drivers/i2c/i2cmux2 # pca9543 smbus mux
 337                                                 device i2c 73 on     #pca9543 channel0
 338                                                         chip drivers/generic/generic #dimm 0-0-0
 339                                                                 device i2c 50 on end
 340                                                         end
 341                                                         chip drivers/generic/generic #dimm 0-0-1
 342                                                                 device i2c 51 on end
 343                                                         end
 344                                                         chip drivers/generic/generic #dimm 0-1-0
 345                                                                 device i2c 52 on end
 346                                                         end
 347                                                         chip drivers/generic/generic #dimm 0-1-1
 348                                                                 device i2c 53 on end
 349                                                         end
 350                                                 end
 351
 352                                                 device i2c 73 on     #pca9543 channel1
 353                                                         chip drivers/generic/generic #dimm 1-0-0
 354                                                                 device i2c 50 on end
 355                                                         end
 356                                                         chip drivers/generic/generic #dimm 1-0-1
 357                                                                 device i2c 51 on end
 358                                                         end
 359                                                         chip drivers/generic/generic #dimm 1-1-0
 360                                                                 device i2c 52 on end
 361                                                         end
 362                                                         chip drivers/generic/generic #dimm 1-1-1
 363                                                                 device i2c 53 on end
 364                                                         end
 365                                                 end
 366                                         end # chip end
 367                                         chip drivers/generic/generic # ICS950405AF
 368                                                 device i2c 69 on end
 369                                         end
 370                                 end
 371                                 device pci 1.5 off end
 372                                 device pci 1.6 on end
 373                                 register "ide0_enable" = "1"
 374                                 register "ide1_enable" = "1"
 375                         end # 8111
 376                 end # LDT1
 377                 device pci 18.0 on end # LDT2
 378                 device pci 18.1 on end
 379                 device pci 18.2 on end
 380                 device pci 18.3 on end
 381             end
 382
 383                 chip northbridge/amd/amdk8
 384                         device pci 19.0 on end # LDT0
 385                         device pci 19.0 on end # LDT1
 386                         device pci 19.0 on # LDT2
 387                                 chip southbridge/amd/amd8131
 388                                         # the on/off keyword is mandatory
 389                                         device pci 0.0 on end
 390                                         device pci 0.1 on end
 391                                         device pci 1.0 on end
 392                                         device pci 1.1 on end
 393                                 end
 394                                 chip southbridge/amd/amd8131
 395                                         # the on/off keyword is mandatory
 396                                         device pci 0.0 on end
 397                                         device pci 0.1 on end
 398                                         device pci 1.0 on end
 399                                         device pci 1.1 on end
 400                                 end
 401                         end # LDT2
 402                         device pci 19.1 on end
 403                         device pci 19.2 on end
 404                         device pci 19.3 on end
 405                 end
 406
 407                 chip northbridge/amd/amdk8
 408                         device pci 1a.0 on end
 409                         device pci 1a.0 on end
 410                         device pci 1a.0 on # LDT2
 411                                 chip southbridge/amd/amd8131
 412                                         # the on/off keyword is mandatory
 413                                         device pci 0.0 on end
 414                                         device pci 0.1 on end
 415                                         device pci 1.0 on end
 416                                         device pci 1.1 on end
 417                                 end
 418                                 chip southbridge/amd/amd8131
 419                                         # the on/off keyword is mandatory
 420                                         device pci 0.0 on end
 421                                         device pci 0.1 on end
 422                                         device pci 1.0 on end
 423                                         device pci 1.1 on end
 424                                 end
 425
 426                         end # LDT2
 427                         device pci 1a.1 on end
 428                         device pci 1a.2 on end
 429                         device pci 1a.3 on end
 430                 end
 431
 432                 chip northbridge/amd/amdk8
 433                         device pci 1b.0 on end
 434                         device pci 1b.0 on # LDT1
 435                                 chip southbridge/amd/amd8131
 436                                         # the on/off keyword is mandatory
 437                                         device pci 0.0 on end
 438                                         device pci 0.1 on end
 439                                         device pci 1.0 on end
 440                                         device pci 1.1 on end
 441                                 end
 442                                 chip southbridge/amd/amd8131
 443                                         # the on/off keyword is mandatory
 444                                         device pci 0.0 on end
 445                                         device pci 0.1 on end
 446                                         device pci 1.0 on end
 447                                         device pci 1.1 on end
 448                                 end
 449
 450                         end
 451                         device pci 1b.0 on end
 452                         device pci 1b.1 on end
 453                         device pci 1b.2 on end
 454                         device pci 1b.3 on end
 455                 end
 456
 457
 458         end
 459 end
 460