3 uses USE_FALLBACK_IMAGE
4 uses HAVE_FALLBACK_BOOT
9 uses CONFIG_MAX_PHYSICAL_CPUS
10 uses CONFIG_LOGICAL_CPUS
18 uses ROM_SECTION_OFFSET
19 uses CONFIG_ROM_PAYLOAD
20 uses CONFIG_ROM_PAYLOAD_START
21 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
22 uses CONFIG_PRECOMPRESSED_PAYLOAD
30 uses LB_CKS_RANGE_START
33 uses MAINBOARD_PART_NUMBER
36 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
37 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
38 uses COREBOOT_EXTRA_VERSION
43 uses DEFAULT_CONSOLE_LOGLEVEL
44 uses MAXIMUM_CONSOLE_LOGLEVEL
45 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
46 uses CONFIG_CONSOLE_SERIAL8250
55 uses CONFIG_CONSOLE_VGA
56 uses CONFIG_PCI_ROM_RUN
57 uses HW_MEM_HOLE_SIZEK
59 uses HT_CHAIN_UNITID_BASE
60 uses HT_CHAIN_END_UNITID_BASE
61 uses SB_HT_CHAIN_ON_BUS0
62 uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
74 ## ROM_SIZE is the size of boot ROM that this board will use.
76 default ROM_SIZE=524288
79 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
81 #default FALLBACK_SIZE=131072
83 default FALLBACK_SIZE=0x40000
86 ## Build code for the fallback boot
88 default HAVE_FALLBACK_BOOT=1
91 ## Build code to reset the motherboard from coreboot
93 default HAVE_HARD_RESET=1
96 ## Build code to export a programmable irq routing table
98 default HAVE_PIRQ_TABLE=1
99 default IRQ_SLOT_COUNT=9
102 ## Build code to export an x86 MP table
103 ## Useful for specifying IRQ routing values
105 default HAVE_MP_TABLE=1
108 ## Build code to export a CMOS option table
110 default HAVE_OPTION_TABLE=1
113 ## Move the default coreboot cmos range off of AMD RTC registers
115 default LB_CKS_RANGE_START=49
116 default LB_CKS_RANGE_END=122
117 default LB_CKS_LOC=123
120 ## Build code for SMP support
121 ## Only worry about 2 micro processors
124 default CONFIG_MAX_CPUS=4
125 default CONFIG_MAX_PHYSICAL_CPUS=2
126 default CONFIG_LOGICAL_CPUS=1
129 default CONFIG_CHIP_NAME=1
131 ##HT Unit ID offset, default is 1, the typical one
132 default HT_CHAIN_UNITID_BASE=0x0a
134 ##real SB Unit ID, default is 0x20, mean dont touch it at last
135 default HT_CHAIN_END_UNITID_BASE=0x06
137 #make the SB HT chain on bus 0, default is not (0)
138 default SB_HT_CHAIN_ON_BUS0=0
140 ##only offset for SB chain?, default is yes(1)
141 #default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
144 default HW_MEM_HOLE_SIZEK=0x100000
147 #default CONFIG_CONSOLE_VGA=1
148 #default CONFIG_PCI_ROM_RUN=1
152 ## enable CACHE_AS_RAM specifics
154 default USE_DCACHE_RAM=1
155 default DCACHE_RAM_BASE=0xcf000
156 default DCACHE_RAM_SIZE=0x1000
157 default CONFIG_USE_INIT=0
160 ## Build code to setup a generic IOAPIC
162 default CONFIG_IOAPIC=1
165 ## Clean up the motherboard id strings
167 default MAINBOARD_PART_NUMBER="s2881"
168 default MAINBOARD_VENDOR="Tyan"
169 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
170 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2881
173 ### coreboot layout values
176 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
177 default ROM_IMAGE_SIZE = 65536
180 ## Use a small 8K stack
182 default STACK_SIZE=0x2000
185 ## Use a small 16K heap
187 default HEAP_SIZE=0x4000
190 ## Only use the option table in a normal image
192 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
195 ## Coreboot C code runs at this location in RAM
197 default _RAMBASE=0x00004000
200 ## Load the payload from the ROM
202 default CONFIG_ROM_PAYLOAD = 1
205 ### Defaults of options that you may want to override in the target config file
209 ## The default compiler
211 default CC="$(CROSS_COMPILE)gcc -m32"
215 ## Disable the gdb stub by default
217 default CONFIG_GDB_STUB=0
220 ## The Serial Console
223 # To Enable the Serial Console
224 default CONFIG_CONSOLE_SERIAL8250=1
226 ## Select the serial console baud rate
227 default TTYS0_BAUD=115200
228 #default TTYS0_BAUD=57600
229 #default TTYS0_BAUD=38400
230 #default TTYS0_BAUD=19200
231 #default TTYS0_BAUD=9600
232 #default TTYS0_BAUD=4800
233 #default TTYS0_BAUD=2400
234 #default TTYS0_BAUD=1200
236 # Select the serial console base port
237 default TTYS0_BASE=0x3f8
239 # Select the serial protocol
240 # This defaults to 8 data bits, 1 stop bit, and no parity
241 default TTYS0_LCS=0x3
244 ### Select the coreboot loglevel
246 ## EMERG 1 system is unusable
247 ## ALERT 2 action must be taken immediately
248 ## CRIT 3 critical conditions
249 ## ERR 4 error conditions
250 ## WARNING 5 warning conditions
251 ## NOTICE 6 normal but significant condition
252 ## INFO 7 informational
253 ## DEBUG 8 debug-level messages
254 ## SPEW 9 Way too many details
256 ## Request this level of debugging output
257 default DEFAULT_CONSOLE_LOGLEVEL=8
258 ## At a maximum only compile in this level of debugging
259 default MAXIMUM_CONSOLE_LOGLEVEL=8
262 ## Select power on after power fail setting
263 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"