src/mainboard/tyan/s2875/Config.lb

   1 ##
   2 ## Compute the location and size of where this firmware image
   3 ## (coreboot plus bootloader) will live in the boot rom chip.
   4 ##
   5 if USE_FALLBACK_IMAGE
   6         default ROM_SECTION_SIZE   = FALLBACK_SIZE
   7         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
   8 else
   9         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
  10         default ROM_SECTION_OFFSET = 0
  11 end
  12
  13 ##
  14 ## Compute the start location and size size of
  15 ## The coreboot bootloader.
  16 ##
  17 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  18 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  19
  20 ##
  21 ## Compute where this copy of coreboot will start in the boot rom
  22 ##
  23 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
  24
  25 ##
  26 ## Compute a range of ROM that can cached to speed up coreboot,
  27 ## execution speed.
  28 ##
  29 ## XIP_ROM_SIZE must be a power of 2.
  30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  31 ##
  32 default XIP_ROM_SIZE=65536
  33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
  34
  35 arch i386 end
  36
  37 ##
  38 ## Build the objects we have code for in this directory.
  39 ##
  40
  41 driver mainboard.o
  42
  43 #dir /drivers/si/3114
  44
  45 if HAVE_MP_TABLE object mptable.o end
  46 if HAVE_PIRQ_TABLE object irq_tables.o end
  47
  48 if USE_DCACHE_RAM
  49
  50 if CONFIG_USE_INIT
  51
  52 makerule ./auto.o
  53         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  54         action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
  55 end
  56
  57 else
  58
  59 makerule ./auto.inc
  60         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  61         action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
  62         action "perl -e 's/.rodata/.rom.data/g' -pi $@"
  63         action "perl -e 's/.text/.section .rom.text/g' -pi $@"
  64 end
  65
  66 end
  67 else
  68
  69 ##
  70 ## Romcc output
  71 ##
  72 makerule ./failover.E
  73         depends "$(MAINBOARD)/failover.c ./romcc"
  74         action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  75 end
  76
  77 makerule ./failover.inc
  78         depends "$(MAINBOARD)/failover.c ./romcc"
  79         action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  80 end
  81
  82 makerule ./auto.E
  83         depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
  84         action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  85 end
  86 makerule ./auto.inc
  87         depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
  88         action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  89 end
  90
  91 end
  92 ##
  93 ## Build our 16 bit and 32 bit coreboot entry code
  94 ##
  95 if USE_FALLBACK_IMAGE
  96         mainboardinit cpu/x86/16bit/entry16.inc
  97         ldscript /cpu/x86/16bit/entry16.lds
  98 end
  99
 100 mainboardinit cpu/x86/32bit/entry32.inc
 101
 102 if USE_DCACHE_RAM
 103         if CONFIG_USE_INIT
 104                 ldscript /cpu/x86/32bit/entry32.lds
 105         end
 106
 107         if CONFIG_USE_INIT
 108                 ldscript      /cpu/amd/car/cache_as_ram.lds
 109         end
 110 end
 111
 112 ##
 113 ## Build our reset vector (This is where coreboot is entered)
 114 ##
 115 if USE_FALLBACK_IMAGE
 116         mainboardinit cpu/x86/16bit/reset16.inc
 117         ldscript /cpu/x86/16bit/reset16.lds
 118 else
 119         mainboardinit cpu/x86/32bit/reset32.inc
 120         ldscript /cpu/x86/32bit/reset32.lds
 121 end
 122
 123 if USE_DCACHE_RAM
 124 else
 125 ### Should this be in the northbridge code?
 126 mainboardinit arch/i386/lib/cpu_reset.inc
 127 end
 128
 129 ##
 130 ## Include an id string (For safe flashing)
 131 ##
 132 mainboardinit arch/i386/lib/id.inc
 133 ldscript /arch/i386/lib/id.lds
 134
 135 if USE_DCACHE_RAM
 136 ##
 137 ## Setup Cache-As-Ram
 138 ##
 139 mainboardinit cpu/amd/car/cache_as_ram.inc
 140 end
 141
 142 ###
 143 ### This is the early phase of coreboot startup
 144 ### Things are delicate and we test to see if we should
 145 ### failover to another image.
 146 ###
 147 if USE_FALLBACK_IMAGE
 148 if USE_DCACHE_RAM
 149        ldscript /arch/i386/lib/failover.lds
 150 else
 151        ldscript /arch/i386/lib/failover.lds
 152         mainboardinit ./failover.inc
 153 end
 154 end
 155
 156 ###
 157 ### O.k. We aren't just an intermediary anymore!
 158 ###
 159
 160 ##
 161 ## Setup RAM
 162 ##
 163 if USE_DCACHE_RAM
 164
 165 if CONFIG_USE_INIT
 166 initobject auto.o
 167 else
 168 mainboardinit ./auto.inc
 169 end
 170
 171 else
 172
 173 ##
 174 ## Setup RAM
 175 ##
 176 mainboardinit cpu/x86/fpu/enable_fpu.inc
 177 mainboardinit cpu/x86/mmx/enable_mmx.inc
 178 mainboardinit cpu/x86/sse/enable_sse.inc
 179 mainboardinit ./auto.inc
 180 mainboardinit cpu/x86/sse/disable_sse.inc
 181 mainboardinit cpu/x86/mmx/disable_mmx.inc
 182
 183 end
 184
 185 ##
 186 ## Include the secondary Configuration files
 187 ##
 188 if CONFIG_CHIP_NAME
 189         config chip.h
 190 end
 191
 192 # sample config for tyan/s2875
 193 chip northbridge/amd/amdk8/root_complex
 194         device apic_cluster 0 on
 195                 chip cpu/amd/socket_940
 196                         device apic 0 on end
 197                 end
 198         end
 199         device pci_domain 0 on
 200                 chip northbridge/amd/amdk8
 201                         device pci 18.0 on #  northbridge
 202                                 #  devices on link 0, link 0 == LDT 0
 203                                 chip southbridge/amd/amd8151
 204                                         # the on/off keyword is mandatory
 205                                         device pci 0.0 on end
 206                                         device pci 1.0 on end
 207                                 end
 208                                 chip southbridge/amd/amd8111
 209                                         # this "device pci 0.0" is the parent the next one
 210                                         # PCI bridge
 211                                         device pci 0.0 on
 212                                                 device pci 0.0 on end
 213                                                 device pci 0.1 on end
 214                                                 device pci 0.2 off end
 215                                                 device pci 1.0 off end
 216                                                 chip drivers/pci/onboard
 217                                                         device pci 5.0 on end
 218                                                         register "rom_address" = "0xfff80000"
 219                                                 end
 220                                         end
 221                                         device pci 1.0 on
 222                                                 chip superio/winbond/w83627hf
 223                                                         device pnp 2e.0 on #  Floppy
 224                                                                 io 0x60 = 0x3f0
 225                                                                 irq 0x70 = 6
 226                                                                 drq 0x74 = 2
 227                                                         end
 228                                                         device pnp 2e.1 off #  Parallel Port
 229                                                                 io 0x60 = 0x378
 230                                                                 irq 0x70 = 7
 231                                                         end
 232                                                         device pnp 2e.2 on #  Com1
 233                                                                 io 0x60 = 0x3f8
 234                                                                 irq 0x70 = 4
 235                                                         end
 236                                                         device pnp 2e.3 off #  Com2
 237                                                                 io 0x60 = 0x2f8
 238                                                                 irq 0x70 = 3
 239                                                         end
 240                                                         device pnp 2e.5 on #  Keyboard
 241                                                                 io 0x60 = 0x60
 242                                                                 io 0x62 = 0x64
 243                                                                 irq 0x70 = 1
 244                                                                 irq 0x72 = 12
 245                                                         end
 246                                                         device pnp 2e.6 off #  CIR
 247                                                                 io 0x60 = 0x100
 248                                                         end
 249                                                         device pnp 2e.7 off #  GAME_MIDI_GIPO1
 250                                                                 io 0x60 = 0x220
 251                                                                 io 0x62 = 0x300
 252                                                                 irq 0x70 = 9
 253                                                         end
 254                                                         device pnp 2e.8 off end #  GPIO2
 255                                                         device pnp 2e.9 off end #  GPIO3
 256                                                         device pnp 2e.a off end #  ACPI
 257                                                         device pnp 2e.b on #  HW Monitor
 258                                                                 io 0x60 = 0x290
 259                                                                 irq 0x70 = 5
 260                                                         end
 261                                                 end
 262                                         end
 263                                         device pci 1.1 on end
 264                                         device pci 1.2 on end
 265                                         device pci 1.3 on end
 266                                         device pci 1.5 on end
 267                                         device pci 1.6 off end
 268                                         register "ide0_enable" = "1"
 269                                         register "ide1_enable" = "1"
 270                                 end
 271                         end #  device pci 18.0
 272
 273                         device pci 18.0 on end
 274                         device pci 18.0 on end
 275
 276                         device pci 18.1 on end
 277                         device pci 18.2 on end
 278                         device pci 18.3 on end
 279                 end
 280         end
 281 end
 282