3 * by yinghai.lu@amd.com
6 #if USE_FALLBACK_IMAGE == 1
8 static void bcm5785_enable_rom(void)
15 /* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */
16 /* Locate the BCM 5785 SB PCI Main */
17 addr = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); // 0x0201?
19 /* Set the 4MB enable bit bit */
20 byte = pci_read_config8(addr, 0x41);
22 pci_write_config8(addr, 0x41, byte);
25 static void bcm5785_enable_lpc(void)
31 dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0);
34 byte = pci_read_config8(dev, 0x44);
37 pci_write_config8(dev, 0x44, byte);
40 byte = pci_read_config8(dev, 0x48);
41 /* superio port 0x2e/4e enable */
43 pci_write_config8(dev, 0x48, byte);
45 #endif /* USE_FALLBACK_IMAGE == 1 */
48 static void bcm5785_enable_wdt_port_cf9(void)
54 dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
56 dword_old = pci_read_config32(dev, 0x4c);
57 dword = dword_old | (1<<4); //enable Timer Func
58 if(dword != dword_old ) {
59 pci_write_config32(dev, 0x4c, dword);
62 dword_old = pci_read_config32(dev, 0x6c);
63 dword = dword_old | (1<<9); //unhide Timer Func in pci space
64 if(dword != dword_old ) {
65 pci_write_config32(dev, 0x6c, dword);
68 dev = pci_locate_device(PCI_ID(0x1166, 0x0238), 0);
71 pci_write_config8(dev, 0x40, (1<<2));
74 static unsigned get_sbdn(unsigned bus)
79 * There can only be one 8111 on a hypertransport chain/bus.
81 dev = pci_locate_device_on_bus(
82 PCI_ID(0x1166, 0x0036),
85 return (dev>>15) & 0x1f;
91 static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
110 static void ldtstop_sb(void)
116 static void hard_reset(void)
118 bcm5785_enable_wdt_port_cf9();
127 static void soft_reset(void)
129 bcm5785_enable_wdt_port_cf9();
134 // outb(0x02, 0x0cf9);
141 static void bcm5785_enable_msg(void)
148 dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
150 byte = pci_read_config8(dev, 0x42);
151 byte = (1<<1); //enable a20
152 pci_write_config8(dev, 0x42, byte);
154 dword_old = pci_read_config32(dev, 0x6c);
155 // bit 5: enable A20 Message
156 // bit 4: enable interrupt messages
157 // bit 3: enable reset init message
158 // bit 2: enable keyboard init message
159 // bit 1: enable upsteam messages
160 // bit 0: enable shutdowm message to init generation
161 dword = dword_old | (1<<5) | (1<<3) | (1<<2) | (1<<1) | (1<<0); // bit 1 and bit 4 must be set, otherwise interrupt msg will not be delivered to the processor
162 if(dword != dword_old ) {
163 pci_write_config32(dev, 0x6c, dword);
168 static void bcm5785_early_setup(void)
176 // enable device on bcm5785 at first
177 dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
178 dword = pci_read_config32(dev, 0x64);
179 dword |= (1<<15) | (1<<11) | (1<<3); // ioapci enable
180 dword |= (1<<8); // USB enable
181 dword |= /* (1<<27)|*/(1<<14); // IDE enable
182 pci_write_config32(dev, 0x64, dword);
184 byte = pci_read_config8(dev, 0x84);
185 byte |= (1<<0); // SATA enable
186 pci_write_config8(dev, 0x84, byte);
188 // wdt and cf9 for later in coreboot_ram to call hard_reset
189 bcm5785_enable_wdt_port_cf9();
191 bcm5785_enable_msg();
197 byte = pci_read_config8(dev, 0x4e);
198 byte |= (1<<4); //enable IDE ext regs
199 pci_write_config8(dev, 0x4e, byte);
202 dev = pci_locate_device(PCI_ID(0x1166, 0x0214), 0);
203 byte = pci_read_config8(dev, 0x48);
204 byte &= ~1; // disable pri channel
205 pci_write_config8(dev, 0x48, byte);
206 pci_write_config8(dev, 0xb0, 0x01);
207 pci_write_config8(dev, 0xb2, 0x02);
208 byte = pci_read_config8(dev, 0x06);
209 byte |= (1<<4); // so b0, b2 can not be changed from now
210 pci_write_config8(dev, 0x06, byte);
211 byte = pci_read_config8(dev, 0x49);
212 byte |= 1; // enable second channel
213 pci_write_config8(dev, 0x49, byte);
217 dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0);
219 byte = pci_read_config8(dev, 0x40);
220 byte |= (1<<3)|(1<<2); // LPC Retry, LPC to PCI DMA enable
221 pci_write_config8(dev, 0x40, byte);
223 pci_write_config32(dev, 0x60, 0x0000ffff); // LPC Memory hole start and end
227 pci_write_config8(dev, 0x90, 0x40);
228 pci_write_config8(dev, 0x92, 0x06);
229 pci_write_config8(dev, 0x9c, 0x7c); //PHY timinig register
230 pci_write_config8(dev, 0xa4, 0x02); //mask reg - low/full speed func
231 pci_write_config8(dev, 0xa5, 0x02); //mask reg - low/full speed func
232 pci_write_config8(dev, 0xa6, 0x00); //mask reg - high speed func
233 pci_write_config8(dev, 0xb4, 0x40);