5 uses USE_FALLBACK_IMAGE
6 uses HAVE_FALLBACK_BOOT
11 uses CONFIG_MAX_PHYSICAL_CPUS
12 uses CONFIG_LOGICAL_CPUS
20 uses ROM_SECTION_OFFSET
21 uses CONFIG_ROM_PAYLOAD
22 uses CONFIG_ROM_PAYLOAD_START
23 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
24 uses CONFIG_PRECOMPRESSED_PAYLOAD
32 uses LB_CKS_RANGE_START
36 uses MAINBOARD_PART_NUMBER
38 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
39 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
40 uses COREBOOT_EXTRA_VERSION
48 uses DEFAULT_CONSOLE_LOGLEVEL
49 uses MAXIMUM_CONSOLE_LOGLEVEL
50 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
51 uses CONFIG_CONSOLE_SERIAL8250
54 uses CONFIG_CONSOLE_VGA
55 uses CONFIG_PCI_ROM_RUN
58 uses HT_CHAIN_UNITID_BASE
59 uses HT_CHAIN_END_UNITID_BASE
60 uses SB_HT_CHAIN_ON_BUS0
61 uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
68 uses CONFIG_USE_PRINTK_IN_CAR
73 uses ENABLE_APIC_EXT_ID
77 uses HW_MEM_HOLE_SIZEK
78 uses CONFIG_PCI_64BIT_PREF_MEM
86 ## ROM_SIZE is the size of boot ROM that this board will use.
88 default ROM_SIZE=524288
91 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
93 #default FALLBACK_SIZE=131072
95 default FALLBACK_SIZE=0x40000
102 default CONFIG_CHIP_NAME=1
106 ## Build code for the fallback boot
108 default HAVE_FALLBACK_BOOT=1
111 ## Use hard_reset for rebooting, it uses reg. 0xcf9 in the amd8111.
113 default HAVE_HARD_RESET=1
116 ## set memory hole size
118 default HW_MEM_HOLE_SIZEK=0x300000
119 #default HW_MEM_HOLE_SIZEK=0x200000
122 ## Build code to export a programmable irq routing table
124 default HAVE_PIRQ_TABLE=1
125 default IRQ_SLOT_COUNT=23
128 ## Build code to export an x86 MP table
129 ## Useful for specifying IRQ routing values
131 default HAVE_MP_TABLE=1
132 default HAVE_ACPI_TABLES=1
135 default ACPI_SSDTX_NUM=3
138 ## Build code to export a CMOS option table
140 default HAVE_OPTION_TABLE=1
143 ## Move the default coreboot cmos range off of AMD RTC registers
145 default LB_CKS_RANGE_START=49
146 default LB_CKS_RANGE_END=122
147 default LB_CKS_LOC=123
150 ## Build code for SMP support
153 default CONFIG_MAX_CPUS=8
154 default CONFIG_MAX_PHYSICAL_CPUS=4
155 default CONFIG_LOGICAL_CPUS=1
156 #default ALLOW_HT_OVERCLOCKING=1
158 default ENABLE_APIC_EXT_ID=1
159 default APIC_ID_OFFSET=0x10
160 default LIFT_BSP_APIC_ID=1 # SDE was 0
163 #default HT_CHAIN_UNITID_BASE=0xa
166 #default HT_CHAIN_END_UNITID_BASE=0x6
168 #make the SB HT chain on bus 0
169 #default SB_HT_CHAIN_ON_BUS0=1
171 #allow capable device use that above 4G
172 #default CONFIG_PCI_64BIT_PREF_MEM=1
175 ## enable CACHE_AS_RAM specifics
177 default USE_DCACHE_RAM=1
178 default DCACHE_RAM_BASE=0xcc000
179 default DCACHE_RAM_SIZE=0x4000
180 default CONFIG_USE_INIT=0
181 #default CONFIG_USE_INIT=1
182 #default CONFIG_USE_PRINTK_IN_CAR=1
185 ## Build code to setup a generic IOAPIC
187 default CONFIG_IOAPIC=1
190 ## Clean up the motherboard id strings
192 default MAINBOARD_PART_NUMBER="ARUMA"
193 default MAINBOARD_VENDOR="AGAMI"
194 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
195 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x36c0
199 ### coreboot layout values
202 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
203 default ROM_IMAGE_SIZE = 65536
206 ## Use a small 8K stack
208 default STACK_SIZE=0x2000
213 default HEAP_SIZE=0x8000
216 ## Only use the option table in a normal image
218 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
221 ## Coreboot C code runs at this location in RAM
223 default _RAMBASE=0x00004000
226 ## Load the payload from the ROM
228 default CONFIG_ROM_PAYLOAD = 1
231 ### Defaults of options that you may want to override in the target config file
235 ## The default compiler
237 default CC="$(CROSS_COMPILE)gcc -m32"
241 ## The Serial Console
244 # To Enable the Serial Console
245 default CONFIG_CONSOLE_SERIAL8250=1
247 ## Select the serial console baud rate
248 #default TTYS0_BAUD=115200
249 #default TTYS0_BAUD=57600
250 #default TTYS0_BAUD=38400
251 #default TTYS0_BAUD=19200
252 default TTYS0_BAUD=9600
253 #default TTYS0_BAUD=4800
254 #default TTYS0_BAUD=2400
255 #default TTYS0_BAUD=1200
257 # Select the serial console base port
258 default TTYS0_BASE=0x3f8
260 # Select the serial protocol
261 # This defaults to 8 data bits, 1 stop bit, and no parity
262 default TTYS0_LCS=0x3
265 ### Select the coreboot loglevel
267 ## EMERG 1 system is unusable
268 ## ALERT 2 action must be taken immediately
269 ## CRIT 3 critical conditions
270 ## ERR 4 error conditions
271 ## WARNING 5 warning conditions
272 ## NOTICE 6 normal but significant condition
273 ## INFO 7 informational
274 ## DEBUG 8 debug-level messages
275 ## SPEW 9 Way too many details
278 ## These values can be overwritten by corebootv2/targets/agami/aruma/Config.lb
279 ## Request this level of debugging output
280 default DEFAULT_CONSOLE_LOGLEVEL=8
281 ## At a maximum only compile in this level of debugging
282 default MAXIMUM_CONSOLE_LOGLEVEL=8
285 ## Select power on after power fail setting
286 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
289 default CONFIG_CONSOLE_VGA=1
290 default CONFIG_PCI_ROM_RUN=1
291 #default CONFIG_CONSOLE_VGA=0
292 #default CONFIG_PCI_ROM_RUN=0