2 ## Compute the location and size of where this firmware image
3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
6 default ROM_SECTION_SIZE = FALLBACK_SIZE
7 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
9 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
10 default ROM_SECTION_OFFSET = 0
14 ## Compute the start location and size size of
15 ## The linuxBIOS bootloader.
17 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
18 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
19 default CONFIG_ROM_PAYLOAD = 1
22 ## Compute where this copy of linuxBIOS will start in the boot rom
24 default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
27 ## Compute a range of ROM that can cached to speed up linuxBIOS,
30 ## XIP_ROM_SIZE must be a power of 2.
31 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
33 default XIP_ROM_SIZE=65536
34 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
40 ## Build the objects we have code for in this directory.
44 if HAVE_MP_TABLE object mptable.o end
45 if HAVE_PIRQ_TABLE object irq_tables.o end
51 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
52 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
58 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
59 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
60 action "perl -e 's/.rodata/.rom.data/g' -pi $@"
61 action "perl -e 's/.text/.section .rom.text/g' -pi $@"
70 depends "$(MAINBOARD)/failover.c ./romcc"
71 action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
74 makerule ./failover.inc
75 depends "$(MAINBOARD)/failover.c ./romcc"
76 action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
80 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
81 action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
85 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
86 action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
92 mainboardinit cpu/x86/fpu/enable_fpu.inc
93 mainboardinit cpu/x86/mmx/enable_mmx.inc
94 mainboardinit cpu/x86/sse/enable_sse.inc
95 mainboardinit ./auto.inc
96 mainboardinit cpu/x86/sse/disable_sse.inc
97 mainboardinit cpu/x86/mmx/disable_mmx.inc
98 mainboardinit arch/i386/lib/jmp_auto_out.inc
103 ## Build our 16 bit and 32 bit linuxBIOS entry code
105 if USE_FALLBACK_IMAGE
106 mainboardinit cpu/x86/16bit/entry16.inc
107 ldscript /cpu/x86/16bit/entry16.lds
110 mainboardinit cpu/x86/32bit/entry32.inc
114 ldscript /cpu/x86/32bit/entry32.lds
118 ldscript /cpu/amd/car/cache_as_ram.lds
124 ## Build our reset vector (This is where linuxBIOS is entered)
126 if USE_FALLBACK_IMAGE
127 mainboardinit cpu/x86/16bit/reset16.inc
128 ldscript /cpu/x86/16bit/reset16.lds
130 mainboardinit cpu/x86/32bit/reset32.inc
131 ldscript /cpu/x86/32bit/reset32.lds
136 ### Should this be in the northbridge code?
137 mainboardinit arch/i386/lib/cpu_reset.inc
141 ## Include an id string (For safe flashing)
143 mainboardinit arch/i386/lib/id.inc
144 ldscript /arch/i386/lib/id.lds
149 ## Setup Cache-As-Ram
151 mainboardinit cpu/amd/car/cache_as_ram.inc
155 ### This is the early phase of linuxBIOS startup
156 ### Things are delicate and we test to see if we should
157 ### failover to another image.
159 if USE_FALLBACK_IMAGE
161 ldscript /arch/i386/lib/failover.lds
163 ldscript /arch/i386/lib/failover.lds
164 mainboardinit ./failover.inc
176 mainboardinit ./auto.inc
182 mainboardinit arch/i386/lib/jmp_auto.inc
187 ## Include the secondary Configuration files
193 # sample config for tyan/s4880
194 chip northbridge/amd/amdk8/root_complex
195 device apic_cluster 0 on
196 chip cpu/amd/socket_940
201 device pci_domain 0 on
202 chip northbridge/amd/amdk8
203 device pci 18.0 on end # LDT0
204 device pci 18.0 on end # LDT1
205 device pci 18.0 on # northbridge
206 # devices on link 2, link 2 == LDT 2
207 chip southbridge/amd/amd8131
208 # the on/off keyword is mandatory
210 # chip drivers/lsi/53c1030
211 # device pci 4.0 on end
212 # device pci 4.1 on end
213 # register "fw_address" = "0xfff8c000"
215 chip drivers/pci/onboard
216 device pci 9.0 on end
217 device pci 9.1 on end
220 device pci 0.1 on end
221 device pci 1.0 on end
222 device pci 1.1 on end
224 chip southbridge/amd/amd8111
225 # this "device pci 0.0" is the parent the next one
228 device pci 0.0 on end
229 device pci 0.1 on end
230 device pci 0.2 off end
231 device pci 1.0 off end
232 chip drivers/pci/onboard
233 device pci 6.0 on end
234 register "rom_address" = "0xfff80000"
238 chip superio/winbond/w83627hf
239 device pnp 2e.0 on # Floppy
244 device pnp 2e.1 off # Parallel Port
248 device pnp 2e.2 on # Com1
252 device pnp 2e.3 off # Com2
256 device pnp 2e.5 on # Keyboard
262 device pnp 2e.6 off # CIR
265 device pnp 2e.7 off # GAME_MIDI_GIPO1
270 device pnp 2e.8 off end # GPIO2
271 device pnp 2e.9 off end # GPIO3
272 device pnp 2e.a off end # ACPI
273 device pnp 2e.b on # HW Monitor
279 device pci 1.1 on end
280 device pci 1.2 on end
281 device pci 1.3 on end
282 device pci 1.5 off end
283 device pci 1.6 off end
284 register "ide0_enable" = "1"
285 register "ide1_enable" = "1"
287 end # device pci 18.0
289 device pci 18.1 on end
290 device pci 18.2 on end
291 device pci 18.3 on end