3 uses USE_FALLBACK_IMAGE
4 uses HAVE_FALLBACK_BOOT
8 uses CONFIG_LOGICAL_CPUS
17 uses ROM_SECTION_OFFSET
18 uses CONFIG_ROM_PAYLOAD
19 uses CONFIG_ROM_PAYLOAD_START
20 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
21 uses CONFIG_PRECOMPRESSED_PAYLOAD
29 uses LB_CKS_RANGE_START
33 uses MAINBOARD_PART_NUMBER
35 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
36 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
37 uses COREBOOT_EXTRA_VERSION
38 uses CONFIG_UDELAY_TSC
39 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
42 uses CONFIG_CONSOLE_SERIAL8250
46 uses DEFAULT_CONSOLE_LOGLEVEL
47 uses MAXIMUM_CONSOLE_LOGLEVEL
48 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
49 uses CONFIG_CONSOLE_BTEXT
61 ## ROM_SIZE is the size of boot ROM that this board will use.
63 default ROM_SIZE=1048576
66 ## Build code for the fallback boot
68 default HAVE_FALLBACK_BOOT=1
71 ## Delay timer options
74 default CONFIG_UDELAY_TSC=1
75 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
78 ## Build code to reset the motherboard from coreboot
80 default HAVE_HARD_RESET=1
83 ## Build code to export a programmable irq routing table
85 default HAVE_PIRQ_TABLE=1
86 default IRQ_SLOT_COUNT=16
89 ## Build code to export an x86 MP table
90 ## Useful for specifying IRQ routing values
92 default HAVE_MP_TABLE=1
95 ## Build code to export a CMOS option table
97 default HAVE_OPTION_TABLE=1
100 ## Move the default coreboot cmos range off of AMD RTC registers
102 default LB_CKS_RANGE_START=49
103 default LB_CKS_RANGE_END=122
104 default LB_CKS_LOC=123
107 ## Build code for SMP support
108 ## Only worry about 2 micro processors
111 default CONFIG_MAX_CPUS=4
112 default CONFIG_LOGICAL_CPUS=0
115 ## Build code to setup a generic IOAPIC
117 default CONFIG_IOAPIC=1
120 ## Clean up the motherboard id strings
122 default MAINBOARD_PART_NUMBER="X6DHE_g"
123 default MAINBOARD_VENDOR= "Supermicro"
124 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9
125 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6080
128 ### coreboot layout values
131 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
132 default ROM_IMAGE_SIZE = 65536
135 ## Use a small 8K stack
137 default STACK_SIZE=0x2000
140 ## Use a small 32K heap
142 default HEAP_SIZE=0x8000
146 ### Compute the location and size of where this firmware image
147 ### (coreboot plus bootloader) will live in the boot rom chip.
149 default FALLBACK_SIZE=131072
152 ## Coreboot C code runs at this location in RAM
154 default _RAMBASE=0x00004000
157 ## Load the payload from the ROM
159 default CONFIG_ROM_PAYLOAD=1
163 ### Defaults of options that you may want to override in the target config file
167 ## The default compiler
169 default CC="$(CROSS_COMPILE)gcc -m32"
173 ## Disable the gdb stub by default
175 default CONFIG_GDB_STUB=0
178 ## The Serial Console
181 # To Enable the Serial Console
182 default CONFIG_CONSOLE_SERIAL8250=1
184 ## Select the serial console baud rate
185 default TTYS0_BAUD=115200
186 #default TTYS0_BAUD=57600
187 #default TTYS0_BAUD=38400
188 #default TTYS0_BAUD=19200
189 #default TTYS0_BAUD=9600
190 #default TTYS0_BAUD=4800
191 #default TTYS0_BAUD=2400
192 #default TTYS0_BAUD=1200
194 # Select the serial console base port
195 default TTYS0_BASE=0x3f8
197 # Select the serial protocol
198 # This defaults to 8 data bits, 1 stop bit, and no parity
199 default TTYS0_LCS=0x3
202 ### Select the coreboot loglevel
204 ## EMERG 1 system is unusable
205 ## ALERT 2 action must be taken immediately
206 ## CRIT 3 critical conditions
207 ## ERR 4 error conditions
208 ## WARNING 5 warning conditions
209 ## NOTICE 6 normal but significant condition
210 ## INFO 7 informational
211 ## DEBUG 8 debug-level messages
212 ## SPEW 9 Way too many details
214 ## Request this level of debugging output
215 default DEFAULT_CONSOLE_LOGLEVEL=8
216 ## At a maximum only compile in this level of debugging
217 default MAXIMUM_CONSOLE_LOGLEVEL=8
220 ## Select power on after power fail setting
221 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
224 ## Don't enable the btext console
226 default CONFIG_CONSOLE_BTEXT=0