2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2006 AMD
5 ## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
7 ## Copyright (C) 2006 MSI
8 ## Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
10 ## This program is free software; you can redistribute it and/or modify
11 ## it under the terms of the GNU General Public License as published by
12 ## the Free Software Foundation; either version 2 of the License, or
13 ## (at your option) any later version.
15 ## This program is distributed in the hope that it will be useful,
16 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ## GNU General Public License for more details.
20 ## You should have received a copy of the GNU General Public License
21 ## along with this program; if not, write to the Free Software
22 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
27 uses USE_FALLBACK_IMAGE
28 uses HAVE_FALLBACK_BOOT
31 uses HAVE_OPTION_TABLE
33 uses CONFIG_MAX_PHYSICAL_CPUS
34 uses CONFIG_LOGICAL_CPUS
42 uses ROM_SECTION_OFFSET
43 uses CONFIG_ROM_PAYLOAD
44 uses CONFIG_ROM_PAYLOAD_START
52 uses LB_CKS_RANGE_START
56 uses MAINBOARD_PART_NUMBER
58 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
59 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
60 uses COREBOOT_EXTRA_VERSION
70 uses DEFAULT_CONSOLE_LOGLEVEL
71 uses MAXIMUM_CONSOLE_LOGLEVEL
72 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
73 uses CONFIG_CONSOLE_SERIAL8250
77 uses CONFIG_CONSOLE_VGA
78 uses CONFIG_PCI_ROM_RUN
79 #bx_b001- uses K8_HW_MEM_HOLE_SIZEK
80 uses K8_HT_FREQ_1G_SUPPORT
85 uses DCACHE_RAM_GLOBAL_VAR_SIZE
88 uses ENABLE_APIC_EXT_ID
92 uses HT_CHAIN_UNITID_BASE
93 uses HT_CHAIN_END_UNITID_BASE
94 #bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0
95 uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
97 uses SB_HT_CHAIN_ON_BUS0
100 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
101 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
102 uses CONFIG_PRECOMPRESSED_PAYLOAD
104 ## ROM_SIZE is the size of boot ROM that this board will use.
106 default ROM_SIZE=524288
109 #bx- default ROM_SIZE=1048576
112 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
114 #default FALLBACK_SIZE=131072
116 default FALLBACK_SIZE=0x40000
123 ## Build code for the fallback boot
125 default HAVE_FALLBACK_BOOT=1
128 ## Build code to reset the motherboard from coreboot
130 default HAVE_HARD_RESET=1
133 ## Build code to export a programmable irq routing table
135 default HAVE_PIRQ_TABLE=1
136 default IRQ_SLOT_COUNT=11
139 ## Build code to export an x86 MP table
140 ## Useful for specifying IRQ routing values
142 default HAVE_MP_TABLE=1
145 ## Build code to export a CMOS option table
147 default HAVE_OPTION_TABLE=1
150 ## Move the default coreboot cmos range off of AMD RTC registers
152 default LB_CKS_RANGE_START=49
153 default LB_CKS_RANGE_END=122
154 default LB_CKS_LOC=123
157 ## Build code for SMP support
158 ## Only worry about 2 micro processors
161 default CONFIG_MAX_CPUS=4
162 default CONFIG_MAX_PHYSICAL_CPUS=2
163 default CONFIG_LOGICAL_CPUS=1
166 #default CONFIG_CHIP_NAME=1
169 #bx_b001- default K8_HW_MEM_HOLE_SIZEK=0x100000
171 #Opteron K8 1G HT Support
172 default K8_HT_FREQ_1G_SUPPORT=1
174 ##HT Unit ID offset, default is 1, the typical one
175 default HT_CHAIN_UNITID_BASE=0x0
177 ##real SB Unit ID, default is 0x20, mean dont touch it at last
178 #default HT_CHAIN_END_UNITID_BASE=0x0
180 #make the SB HT chain on bus 0, default is not (0)
181 #bx_b001- default K8_SB_HT_CHAIN_ON_BUS0=2
183 ##bx_b005+ make the SB HT chain on bus 0
184 default SB_HT_CHAIN_ON_BUS0=1
186 ##only offset for SB chain?, default is yes(1)
187 default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
190 default CONFIG_CONSOLE_VGA=1
191 default CONFIG_PCI_ROM_RUN=1
194 ## enable CACHE_AS_RAM specifics
196 default USE_DCACHE_RAM=1
197 default DCACHE_RAM_BASE=0xcc000
198 default DCACHE_RAM_SIZE=0x4000
199 default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
200 default CONFIG_USE_INIT=0
202 default ENABLE_APIC_EXT_ID=1
203 default APIC_ID_OFFSET=0x10
204 default LIFT_BSP_APIC_ID=0
208 ## Build code to setup a generic IOAPIC
210 default CONFIG_IOAPIC=1
213 ## Clean up the motherboard id strings
215 default MAINBOARD_PART_NUMBER="ms9282"
216 default MAINBOARD_VENDOR="MSI"
217 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1462
218 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x9282
221 ### coreboot layout values
224 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
225 default ROM_IMAGE_SIZE = 65536
228 ## Use a small 8K stack
230 default STACK_SIZE=0x2000
233 ## Use a small 16K heap
235 default HEAP_SIZE=0x4000
238 ## Only use the option table in a normal image
240 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
243 ## Coreboot C code runs at this location in RAM
245 default _RAMBASE=0x00004000
248 ## Load the payload from the ROM
250 default CONFIG_ROM_PAYLOAD = 1
253 ### Defaults of options that you may want to override in the target config file
257 ## The default compiler
259 default CC="$(CROSS_COMPILE)gcc -m32"
263 ## Disable the gdb stub by default
265 default CONFIG_GDB_STUB=0
268 ## The Serial Console
271 # To Enable the Serial Console
272 default CONFIG_CONSOLE_SERIAL8250=1
274 ## Select the serial console baud rate
275 default TTYS0_BAUD=115200
276 #default TTYS0_BAUD=57600
277 #default TTYS0_BAUD=38400
278 #default TTYS0_BAUD=19200
279 #default TTYS0_BAUD=9600
280 #default TTYS0_BAUD=4800
281 #default TTYS0_BAUD=2400
282 #default TTYS0_BAUD=1200
284 # Select the serial console base port
285 default TTYS0_BASE=0x3f8
287 # Select the serial protocol
288 # This defaults to 8 data bits, 1 stop bit, and no parity
289 default TTYS0_LCS=0x3
292 ### Select the coreboot loglevel
294 ## EMERG 1 system is unusable
295 ## ALERT 2 action must be taken immediately
296 ## CRIT 3 critical conditions
297 ## ERR 4 error conditions
298 ## WARNING 5 warning conditions
299 ## NOTICE 6 normal but significant condition
300 ## INFO 7 informational
301 ## DEBUG 8 debug-level messages
302 ## SPEW 9 Way too many details
304 ## Request this level of debugging output
305 default DEFAULT_CONSOLE_LOGLEVEL=8
306 ## At a maximum only compile in this level of debugging
307 default MAXIMUM_CONSOLE_LOGLEVEL=8
310 ## Select power on after power fail setting
311 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"