3 uses USE_FALLBACK_IMAGE
4 uses HAVE_FALLBACK_BOOT
9 uses CONFIG_MAX_PHYSICAL_CPUS
10 uses CONFIG_LOGICAL_CPUS
18 uses ROM_SECTION_OFFSET
19 uses CONFIG_ROM_PAYLOAD
20 uses CONFIG_ROM_PAYLOAD_START
21 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
22 uses CONFIG_PRECOMPRESSED_PAYLOAD
30 uses LB_CKS_RANGE_START
33 uses MAINBOARD_PART_NUMBER
36 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
37 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
38 uses COREBOOT_EXTRA_VERSION
48 uses DEFAULT_CONSOLE_LOGLEVEL
49 uses MAXIMUM_CONSOLE_LOGLEVEL
50 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
51 uses CONFIG_CONSOLE_SERIAL8250
52 uses CONFIG_CONSOLE_BTEXT
56 uses CONFIG_CONSOLE_VGA
57 uses CONFIG_PCI_ROM_RUN
58 uses HW_MEM_HOLE_SIZEK
65 uses ENABLE_APIC_EXT_ID
69 uses CONFIG_PCI_64BIT_PREF_MEM
71 uses HT_CHAIN_UNITID_BASE
72 uses HT_CHAIN_END_UNITID_BASE
73 uses SB_HT_CHAIN_ON_BUS0
74 uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
76 uses CONFIG_LB_MEM_TOPK
79 ## ROM_SIZE is the size of boot ROM that this board will use.
81 default ROM_SIZE=524288
84 #default ROM_SIZE=1048576
88 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
90 #default FALLBACK_SIZE=131072
92 default FALLBACK_SIZE=0x40000
99 ## Build code for the fallback boot
101 default HAVE_FALLBACK_BOOT=1
104 ## Build code to reset the motherboard from coreboot
106 default HAVE_HARD_RESET=1
109 ## Build code to export a programmable irq routing table
111 default HAVE_PIRQ_TABLE=1
112 default IRQ_SLOT_COUNT=11
115 ## Build code to export an x86 MP table
116 ## Useful for specifying IRQ routing values
118 default HAVE_MP_TABLE=1
121 ## Build code to export a CMOS option table
123 default HAVE_OPTION_TABLE=1
126 ## Move the default coreboot cmos range off of AMD RTC registers
128 default LB_CKS_RANGE_START=49
129 default LB_CKS_RANGE_END=122
130 default LB_CKS_LOC=123
133 ## Build code for SMP support
134 ## Only worry about 2 micro processors
137 default CONFIG_MAX_CPUS=4
138 default CONFIG_MAX_PHYSICAL_CPUS=2
139 default CONFIG_LOGICAL_CPUS=1
142 default HW_MEM_HOLE_SIZEK=0x100000
144 ##HT Unit ID offset, default is 1, the typical one
145 default HT_CHAIN_UNITID_BASE=0x0
147 ##real SB Unit ID, default is 0x20, mean dont touch it at last
148 #default HT_CHAIN_END_UNITID_BASE=0x0
150 #make the SB HT chain on bus 0, default is not (0)
151 default SB_HT_CHAIN_ON_BUS0=2
153 ##only offset for SB chain?, default is yes(1)
154 #default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
157 #default CONFIG_CONSOLE_BTEXT=1
160 default CONFIG_CONSOLE_VGA=1
161 default CONFIG_PCI_ROM_RUN=1
164 ## enable CACHE_AS_RAM specifics
166 default USE_DCACHE_RAM=1
167 default DCACHE_RAM_BASE=0xcf000
168 default DCACHE_RAM_SIZE=0x1000
169 default CONFIG_USE_INIT=0
171 default ENABLE_APIC_EXT_ID=0
172 default APIC_ID_OFFSET=0x10
173 default LIFT_BSP_APIC_ID=0
176 #default CONFIG_PCI_64BIT_PREF_MEM=1
179 ## Build code to setup a generic IOAPIC
181 default CONFIG_IOAPIC=1
184 ## Clean up the motherboard id strings
186 default MAINBOARD_PART_NUMBER="s2891"
187 default MAINBOARD_VENDOR="Tyan"
188 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
189 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2891
192 ### coreboot layout values
195 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
196 default ROM_IMAGE_SIZE = 65536
199 ## Use a small 8K stack
201 default STACK_SIZE=0x2000
204 ## Use a small 16K heap
206 default HEAP_SIZE=0x4000
209 ## Only use the option table in a normal image
211 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
214 ## Coreboot C code runs at this location in RAM
216 default _RAMBASE=0x00004000
219 ## Load the payload from the ROM
221 default CONFIG_ROM_PAYLOAD = 1
224 ### Defaults of options that you may want to override in the target config file
228 ## The default compiler
230 default CC="$(CROSS_COMPILE)gcc -m32"
234 ## Disable the gdb stub by default
236 default CONFIG_GDB_STUB=0
239 ## The Serial Console
242 # To Enable the Serial Console
243 default CONFIG_CONSOLE_SERIAL8250=1
245 ## Select the serial console baud rate
246 default TTYS0_BAUD=115200
247 #default TTYS0_BAUD=57600
248 #default TTYS0_BAUD=38400
249 #default TTYS0_BAUD=19200
250 #default TTYS0_BAUD=9600
251 #default TTYS0_BAUD=4800
252 #default TTYS0_BAUD=2400
253 #default TTYS0_BAUD=1200
255 # Select the serial console base port
256 default TTYS0_BASE=0x3f8
258 # Select the serial protocol
259 # This defaults to 8 data bits, 1 stop bit, and no parity
260 default TTYS0_LCS=0x3
263 ### Select the coreboot loglevel
265 ## EMERG 1 system is unusable
266 ## ALERT 2 action must be taken immediately
267 ## CRIT 3 critical conditions
268 ## ERR 4 error conditions
269 ## WARNING 5 warning conditions
270 ## NOTICE 6 normal but significant condition
271 ## INFO 7 informational
272 ## DEBUG 8 debug-level messages
273 ## SPEW 9 Way too many details
275 ## Request this level of debugging output
276 default DEFAULT_CONSOLE_LOGLEVEL=8
277 ## At a maximum only compile in this level of debugging
278 default MAXIMUM_CONSOLE_LOGLEVEL=8
281 ## Select power on after power fail setting
282 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"