10 uses HAVE_OPTION_TABLE
11 uses CONFIG_SANDPOINT_ALTIMUS
13 uses DEFAULT_CONSOLE_LOGLEVEL
15 uses CONFIG_CHIP_CONFIGURE
17 uses CONFIG_CONSOLE_SERIAL8250
20 uses CONFIG_FS_PAYLOAD
22 uses CONFIG_FS_ISO9660
24 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
25 uses CONFIG_PRECOMPRESSED_PAYLOAD
31 uses _EXCEPTION_VECTORS
41 uses MAINBOARD_PART_NUMBER
42 uses COREBOOT_EXTRA_VERSION
51 default ISA_IO_BASE=0xfe000000
52 default ISA_MEM_BASE=0xfd000000
53 default PCIC0_CFGADDR=0xfec00000
54 default PCIC0_CFGDATA=0xfee00000
55 default PNP_CFGADDR=0x15c
56 default PNP_CFGDATA=0x15d
57 default _IO_BASE=ISA_IO_BASE
60 ## use a cross compiler
61 #default CROSS_COMPILE="powerpc-eabi-"
62 #default CROSS_COMPILE="ppc_74xx-"
64 ## Use stage 1 initialization code
65 default CONFIG_USE_INIT=1
67 ## Use static configuration
68 default CONFIG_CHIP_CONFIGURE=1
70 ## We don't use compressed image
71 default CONFIG_COMPRESS=0
73 ## Turn off POST codes
76 ## Enable serial console
77 default DEFAULT_CONSOLE_LOGLEVEL=8
78 default CONFIG_CONSOLE_SERIAL8250=1
79 default TTYS0_BASE=0x3f8
81 ## Load payload using filo
83 default CONFIG_FS_PAYLOAD=1
84 default CONFIG_FS_EXT2=1
85 default CONFIG_FS_ISO9660=1
86 default CONFIG_FS_FAT=1
87 default AUTOBOOT_CMDLINE="hdc1:/vmlinuz"
89 # coreboot must fit into 128KB
90 default ROM_IMAGE_SIZE=131072
91 default ROM_SIZE={ROM_IMAGE_SIZE+PAYLOAD_SIZE}
92 default PAYLOAD_SIZE=262144
94 # Set stack and heap sizes (stage 2)
95 default STACK_SIZE=0x10000
96 default HEAP_SIZE=0x10000
98 # Sandpoint Demo Board
100 default _ROMBASE=0xfff00000
102 ## Sandpoint reset vector
103 default _RESET=_ROMBASE+0x100
105 ## Exception vectors (other than reset vector)
106 default _EXCEPTION_VECTORS=_RESET+0x100
108 ## Start of coreboot in the boot rom
109 ## = _RESET + exeception vector table size
110 default _ROMSTART=_RESET+0x3100
112 ## Coreboot C code runs at this location in RAM
113 default _RAMBASE=0x00100000
114 default _RAMSTART=0x00100000