2 # This file is part of the coreboot project.
4 # Copyright (C) 2007 Advanced Micro Devices, Inc.
6 # This program is free software; you can redistribute it and/or modify
7 # it under the terms of the GNU General Public License as published by
8 # the Free Software Foundation; version 2 of the License.
10 # This program is distributed in the hope that it will be useful,
11 # but WITHOUT ANY WARRANTY; without even the implied warranty of
12 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 # GNU General Public License for more details.
15 # You should have received a copy of the GNU General Public License
16 # along with this program; if not, write to the Free Software
17 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 ## Compute the location and size of where this firmware image
22 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
25 default ROM_SECTION_SIZE = FAILOVER_SIZE
26 default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
29 default ROM_SECTION_SIZE = FALLBACK_SIZE
30 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
32 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
33 default ROM_SECTION_OFFSET = 0
38 ## Compute the start location and size size of
39 ## The linuxBIOS bootloader.
41 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
42 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
45 ## Compute where this copy of linuxBIOS will start in the boot rom
47 default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
50 ## Compute a range of ROM that can cached to speed up linuxBIOS,
53 ## XIP_ROM_SIZE must be a power of 2.
54 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
56 default XIP_ROM_SIZE=65536
59 default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
62 default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
64 default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
71 ## Build the objects we have code for in this directory.
77 #needed by irq_tables and mptable and acpi_tables
92 depends "$(MAINBOARD)/dx/dsdt_lb.dsl"
93 action "iasl -p $(PWD)/dsdt_lb -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
94 action "mv dsdt_lb.hex dsdt.c"
98 #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
102 depends "$(MAINBOARD)/dx/pci2.asl"
103 action "iasl -p $(PWD)/pci2 -tc $(MAINBOARD)/dx/pci2.asl"
104 action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
105 action "mv pci2.hex ssdt2.c"
109 depends "$(MAINBOARD)/dx/pci3.asl"
110 action "iasl -p $(PWD)/pci3 -tc $(MAINBOARD)/dx/pci3.asl"
111 action "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex"
112 action "mv pci3.hex ssdt3.c"
116 depends "$(MAINBOARD)/dx/pci4.asl"
117 action "iasl -p $(PWD)/pci4 -tc $(MAINBOARD)/dx/pci4.asl"
118 action "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex"
119 action "mv pci4.hex ssdt4.c"
123 depends "$(MAINBOARD)/dx/pci5.asl"
124 action "iasl -p $(PWD)/pci5 -tc $(MAINBOARD)/dx/pci5.asl"
125 action "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex"
126 action "mv pci5.hex ssdt5.c"
133 makedefine CACHE_AS_RAM_AUTO_C:=cache_as_ram_auto.c
136 # compile cache_as_ram.c to auto.o
137 makerule ./cache_as_ram_auto.o
138 depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h"
139 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
143 #compile cache_as_ram.c to auto.inc
144 makerule ./cache_as_ram_auto.inc
145 depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h"
146 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
147 action "perl -e 's/.rodata/.rom.data/g' -pi $@"
148 action "perl -e 's/.text/.section .rom.text/g' -pi $@"
154 if USE_FAILOVER_IMAGE
156 if CONFIG_AP_CODE_IN_CAR
157 makerule ./apc_auto.o
158 depends "$(MAINBOARD)/apc_auto.c option_table.h"
159 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
161 ldscript /arch/i386/init/ldscript_apc.lb
166 ## Build our 16 bit and 32 bit linuxBIOS entry code
169 if HAVE_FAILOVER_BOOT
170 if USE_FAILOVER_IMAGE
171 mainboardinit cpu/x86/16bit/entry16.inc
172 ldscript /cpu/x86/16bit/entry16.lds
175 if USE_FALLBACK_IMAGE
176 mainboardinit cpu/x86/16bit/entry16.inc
177 ldscript /cpu/x86/16bit/entry16.lds
181 mainboardinit cpu/x86/32bit/entry32.inc
184 ldscript /cpu/x86/32bit/entry32.lds
188 ldscript /cpu/amd/car/cache_as_ram.lds
193 ## Build our reset vector (This is where linuxBIOS is entered)
195 if HAVE_FAILOVER_BOOT
196 if USE_FAILOVER_IMAGE
197 mainboardinit cpu/x86/16bit/reset16.inc
198 ldscript /cpu/x86/16bit/reset16.lds
200 mainboardinit cpu/x86/32bit/reset32.inc
201 ldscript /cpu/x86/32bit/reset32.lds
204 if USE_FALLBACK_IMAGE
205 mainboardinit cpu/x86/16bit/reset16.inc
206 ldscript /cpu/x86/16bit/reset16.lds
208 mainboardinit cpu/x86/32bit/reset32.inc
209 ldscript /cpu/x86/32bit/reset32.lds
215 ## Include an id string (For safe flashing)
217 mainboardinit arch/i386/lib/id.inc
218 ldscript /arch/i386/lib/id.lds
222 ## Setup Cache-As-Ram
224 mainboardinit cpu/amd/car/cache_as_ram.inc
228 ### This is the early phase of linuxBIOS startup
229 ### Things are delicate and we test to see if we should
230 ### failover to another image.
232 if HAVE_FAILOVER_BOOT
233 if USE_FAILOVER_IMAGE
235 ldscript /arch/i386/lib/failover_failover.lds
239 if USE_FALLBACK_IMAGE
241 ldscript /arch/i386/lib/failover.lds
247 ### O.k. We aren't just an intermediary anymore!
256 initobject cache_as_ram_auto.o
258 mainboardinit ./cache_as_ram_auto.inc
264 ## Include the secondary Configuration files
270 dir /southbridge/amd/amd8151
272 # sample config for amd/serengeti_cheetah_fam10
273 chip northbridge/amd/amdfam10/root_complex
274 device apic_cluster 0 on
275 chip cpu/amd/socket_F_1207 #L1 and DDR2
279 device pci_domain 0 on
280 chip northbridge/amd/amdfam10
281 device pci 18.0 on # northbridge
282 # devices on link 0, link 0 == LDT 0
283 chip southbridge/amd/amd8132
284 # the on/off keyword is mandatory
285 device pci 0.0 on end
286 device pci 0.1 on end
287 device pci 1.0 on end
288 device pci 1.1 on end
290 chip southbridge/amd/amd8111
291 # this "device pci 0.0" is the parent the next one
294 device pci 0.0 on end
295 device pci 0.1 on end
296 device pci 0.2 off end
297 device pci 1.0 off end
300 chip superio/winbond/w83627hf
301 device pnp 2e.0 off # Floppy
306 device pnp 2e.1 off # Parallel Port
310 device pnp 2e.2 on # Com1
314 device pnp 2e.3 off # Com2
318 device pnp 2e.5 on # Keyboard
324 device pnp 2e.6 off # CIR
327 device pnp 2e.7 off # GAME_MIDI_GIPO1
332 device pnp 2e.8 off end # GPIO2
333 device pnp 2e.9 off end # GPIO3
334 device pnp 2e.a off end # ACPI
335 device pnp 2e.b on # HW Monitor
341 device pci 1.1 on end
342 device pci 1.2 on end
344 chip drivers/i2c/i2cmux2 # pca9556 smbus mux
345 chip drivers/i2c/i2cmux2 # pca9556 smbus mux
346 device i2c 18 on #0 pca9516 1
347 chip drivers/generic/generic #dimm 0-0-0
350 chip drivers/generic/generic #dimm 0-0-1
353 chip drivers/generic/generic #dimm 0-1-0
356 chip drivers/generic/generic #dimm 0-1-1
360 device i2c 18 on #1 pca9516 2
361 chip drivers/generic/generic #dimm 1-0-0
364 chip drivers/generic/generic #dimm 1-0-1
367 chip drivers/generic/generic #dimm 1-1-0
370 chip drivers/generic/generic #dimm 1-1-1
377 device pci 1.5 off end
378 device pci 1.6 off end
379 register "ide0_enable" = "1"
380 register "ide1_enable" = "1"
382 end # device pci 18.0
384 device pci 18.0 on end
385 device pci 18.0 on end
386 device pci 18.1 on end
387 device pci 18.2 on end
388 device pci 18.3 on end
389 device pci 18.4 on end
390 # device pci 00.5 on end
393 #for node 32 to node 63
394 # device pci_domain 0 on
395 # chip northbridge/amd/amdfam10
396 # device pci 00.0 on end# northbridge
397 # device pci 00.0 on end
398 # device pci 00.0 on end
399 # device pci 00.0 on end
400 # device pci 00.1 on end
401 # device pci 00.2 on end
402 # device pci 00.3 on end
403 # device pci 00.4 on end
404 # device pci 00.5 on end
408 # chip drivers/generic/debug
409 # device pnp 0.0 off end # chip name
410 # device pnp 0.1 on end # pci_regs_all
411 # device pnp 0.2 off end # mem
412 # device pnp 0.3 off end # cpuid
413 # device pnp 0.4 off end # smbus_regs_all
414 # device pnp 0.5 off end # dual core msr
415 # device pnp 0.6 off end # cache size
416 # device pnp 0.7 off end # tsc
417 # device pnp 0.8 off end # hard reset
418 # device pnp 0.9 off end # mcp55
419 # device pnp 0.a on end # GH ext table