2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2006 AMD
5 ## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
7 ## Copyright (C) 2006 MSI
8 ## Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
10 ## This program is free software; you can redistribute it and/or modify
11 ## it under the terms of the GNU General Public License as published by
12 ## the Free Software Foundation; either version 2 of the License, or
13 ## (at your option) any later version.
15 ## This program is distributed in the hope that it will be useful,
16 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ## GNU General Public License for more details.
20 ## You should have received a copy of the GNU General Public License
21 ## along with this program; if not, write to the Free Software
22 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
26 ## Compute the location and size of where this firmware image
27 ## (coreboot plus bootloader) will live in the boot rom chip.
30 default ROM_SECTION_SIZE = FALLBACK_SIZE
31 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
33 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
34 default ROM_SECTION_OFFSET = 0
38 ## Compute the start location and size size of
39 ## The coreboot bootloader.
41 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
42 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
43 default CONFIG_ROM_PAYLOAD = 1
46 ## Compute where this copy of coreboot will start in the boot rom
48 default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
51 ## Compute a range of ROM that can cached to speed up coreboot,
54 ## XIP_ROM_SIZE must be a power of 2.
55 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
57 default XIP_ROM_SIZE=65536
58 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
64 ## Build the objects we have code for in this directory.
69 #dir /drivers/ati/ragexl
70 #needed by irq_tables and mptable and acpi_tables
74 if HAVE_MP_TABLE object mptable.o end
75 if HAVE_PIRQ_TABLE object irq_tables.o end
83 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
84 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
90 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
91 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
92 action "perl -e 's/.rodata/.rom.data/g' -pi $@"
93 action "perl -e 's/.text/.section .rom.text/g' -pi $@"
102 makerule ./failover.E
103 depends "$(MAINBOARD)/failover.c ./romcc"
104 action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
107 makerule ./failover.inc
108 depends "$(MAINBOARD)/failover.c ./romcc"
109 action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
113 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
114 action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
117 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
118 action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
125 ## Build our 16 bit and 32 bit coreboot entry code
127 if USE_FALLBACK_IMAGE
128 mainboardinit cpu/x86/16bit/entry16.inc
129 ldscript /cpu/x86/16bit/entry16.lds
132 mainboardinit cpu/x86/32bit/entry32.inc
136 ldscript /cpu/x86/32bit/entry32.lds
140 ldscript /cpu/amd/car/cache_as_ram.lds
145 ## Build our reset vector (This is where coreboot is entered)
147 if USE_FALLBACK_IMAGE
148 mainboardinit cpu/x86/16bit/reset16.inc
149 ldscript /cpu/x86/16bit/reset16.lds
151 mainboardinit cpu/x86/32bit/reset32.inc
152 ldscript /cpu/x86/32bit/reset32.lds
157 ### Should this be in the northbridge code?
158 mainboardinit arch/i386/lib/cpu_reset.inc
162 ## Include an id string (For safe flashing)
164 mainboardinit southbridge/nvidia/mcp55/id.inc
165 ldscript /southbridge/nvidia/mcp55/id.lds
168 ## ROMSTRAP table for MCP55
170 if USE_FALLBACK_IMAGE
171 mainboardinit southbridge/nvidia/mcp55/romstrap.inc
172 ldscript /southbridge/nvidia/mcp55/romstrap.lds
177 ## Setup Cache-As-Ram
179 mainboardinit cpu/amd/car/cache_as_ram.inc
183 ### This is the early phase of coreboot startup
184 ### Things are delicate and we test to see if we should
185 ### failover to another image.
187 if USE_FALLBACK_IMAGE
189 ldscript /arch/i386/lib/failover.lds
191 ldscript /arch/i386/lib/failover.lds
192 mainboardinit ./failover.inc
197 ### O.k. We aren't just an intermediary anymore!
208 mainboardinit ./auto.inc
213 mainboardinit cpu/x86/fpu/enable_fpu.inc
214 mainboardinit cpu/x86/mmx/enable_mmx.inc
215 mainboardinit cpu/x86/sse/enable_sse.inc
216 mainboardinit ./auto.inc
217 mainboardinit cpu/x86/sse/disable_sse.inc
218 mainboardinit cpu/x86/mmx/disable_mmx.inc
223 ## Include the secondary Configuration files
230 # sample config for msi/ms9282
231 chip northbridge/amd/amdk8/root_complex
232 device apic_cluster 0 on
233 chip cpu/amd/socket_F
238 device pci_domain 0 on
239 chip northbridge/amd/amdk8 #mc0
240 device pci 18.0 on # northbridge
241 # devices on link 0, link 0 == LDT 0
242 chip southbridge/nvidia/mcp55
243 device pci 0.0 on end # HT
244 device pci 1.0 on # LPC
245 chip superio/winbond/w83627ehg
246 device pnp 2e.0 on # Floppy
251 device pnp 2e.1 off # Parallel Port
255 device pnp 2e.2 on # Com1
259 device pnp 2e.3 off # Com2
263 device pnp 2e.5 on # Keyboard
269 device pnp 2e.6 off # SERIAL_FALSH
272 device pnp 2e.7 off # GAME_MIDI_GIPO1
277 device pnp 2e.8 off end # WDTO_PLED
278 device pnp 2e.9 off end # GPIO2_GPIO3_GPIO4_GPIO5
279 device pnp 2e.a off end # ACPI
280 device pnp 2e.b on # HW Monitor
286 device pci 1.1 on # SM 0
287 chip drivers/i2c/i2cmux2 # pca9554 smbus mux
288 device i2c 70 on #0 pca9554 1
289 chip drivers/generic/generic #dimm 0-0-0
292 chip drivers/generic/generic #dimm 0-0-1
295 chip drivers/generic/generic #dimm 0-1-0
298 chip drivers/generic/generic #dimm 0-1-1
301 chip drivers/generic/generic #dimm 0-0-0
304 chip drivers/generic/generic #dimm 0-0-1
307 chip drivers/generic/generic #dimm 0-1-0
310 chip drivers/generic/generic #dimm 0-1-1
314 device i2c 70 on #0 pca9554 2
315 chip drivers/generic/generic #dimm 0-0-0
318 chip drivers/generic/generic #dimm 0-0-1
321 chip drivers/generic/generic #dimm 0-1-0
324 chip drivers/generic/generic #dimm 0-1-1
327 chip drivers/generic/generic #dimm 0-0-0
330 chip drivers/generic/generic #dimm 0-0-1
333 chip drivers/generic/generic #dimm 0-1-0
336 chip drivers/generic/generic #dimm 0-1-1
342 device pci 1.1 on # SM 1
343 chip drivers/i2c/i2cmux2 # pca9554 smbus mux
344 device i2c 72 on #pca9554 channle1
345 chip drivers/i2c/adm1027 #HWM ADT7476 1
349 device i2c 72 on #pca9545 channel 2
350 chip drivers/i2c/adm1027 #HWM ADT7463
354 device i2c 72 on end #pca9545 channel 3
355 device i2c 72 on #pca9545 channel 4
356 chip drivers/i2c/adm1027 #HWM ADT7476 2
363 device pci 2.0 on end # USB 1.1
364 device pci 2.1 on end # USB 2
365 device pci 4.0 on end # IDE
366 device pci 5.0 on end # SATA 0
367 device pci 5.1 on end # SATA 1
368 device pci 5.2 on end # SATA 2
369 device pci 6.0 on #P2P
370 chip drivers/pci/onboard
371 device pci 4.0 on end
372 register "rom_address" = "0xfff80000"
375 device pci 7.0 on end # reserve
376 device pci 8.0 on end # MAC0
377 device pci 9.0 on end # MAC1
380 chip drivers/pci/onboard
381 device pci 4.0 on end #pci_E lan1
382 device pci 4.1 on end #pci_E lan2
386 device pci b.0 on end # PCI E 0x374
387 device pci c.0 on end
388 device pci d.0 on #SAS
389 chip drivers/pci/onboard
390 device pci 0.0 on end
393 device pci e.0 on end # PCI E 0 0x375
394 device pci f.0 on end #PCI E 0x377 pci_E slot
395 register "ide0_enable" = "1"
396 register "ide1_enable" = "1"
397 register "sata0_enable" = "1"
398 register "sata1_enable" = "1"
400 end # device pci 18.0
401 device pci 18.0 on end # Link 1
402 device pci 18.0 on end
403 device pci 18.1 on end
404 device pci 18.2 on end
405 device pci 18.3 on end
410 # chip drivers/generic/debug
411 # device pnp 0.0 off end
412 # device pnp 0.1 off end
413 # device pnp 0.2 off end
414 # device pnp 0.3 off end
415 # device pnp 0.4 off end
416 # device pnp 0.5 on end