spec/*.pdf
*.swp
*~
+
+*.ppk
\ No newline at end of file
--- /dev/null
+[InternetShortcut]\r
+URL=http://www.altera.com/support/software/nativelink/simulation/modelsim/eda_pro_msim_timing_sim.html\r
+Modified=00C1946036C4CA017A\r
--- /dev/null
+[InternetShortcut]\r
+URL=http://ti.tuwien.ac.at/ecs/teaching/courses/hwmod\r
+Modified=D073354C36C4CA0189\r
--- /dev/null
+--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone II" LPM_DIRECTION="SUB" LPM_WIDTH=1 cout dataa datab result
+--VERSION_BEGIN 7.0 cbx_cycloneii 2006:09:30:03:03:26:SJ cbx_lpm_add_sub 2006:10:11:06:03:24:SJ cbx_mgl 2006:10:28:00:08:48:SJ cbx_stratix 2006:09:18:18:47:42:SJ cbx_stratixii 2006:10:13:22:01:30:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2007 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+
+
+--synthesis_resources =
+SUBDESIGN add_sub_lkc
+(
+ cout : output;
+ dataa[0..0] : input;
+ datab[0..0] : input;
+ result[0..0] : output;
+)
+VARIABLE
+ carry_eqn[0..0] : WIRE;
+ cin_wire : WIRE;
+ datab_node[0..0] : WIRE;
+ sum_eqn[0..0] : WIRE;
+
+BEGIN
+ carry_eqn[] = ( ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & cin_wire)));
+ cin_wire = B"1";
+ cout = carry_eqn[0..0];
+ datab_node[] = (! datab[]);
+ result[] = sum_eqn[];
+ sum_eqn[] = ( ((dataa[0..0] $ datab_node[0..0]) $ cin_wire));
+END;
+--VALID FILE
--- /dev/null
+--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone II" LPM_DIRECTION="SUB" LPM_WIDTH=2 cout dataa datab result
+--VERSION_BEGIN 7.0 cbx_cycloneii 2006:09:30:03:03:26:SJ cbx_lpm_add_sub 2006:10:11:06:03:24:SJ cbx_mgl 2006:10:28:00:08:48:SJ cbx_stratix 2006:09:18:18:47:42:SJ cbx_stratixii 2006:10:13:22:01:30:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2007 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+
+
+--synthesis_resources =
+SUBDESIGN add_sub_mkc
+(
+ cout : output;
+ dataa[1..0] : input;
+ datab[1..0] : input;
+ result[1..0] : output;
+)
+VARIABLE
+ carry_eqn[1..0] : WIRE;
+ cin_wire : WIRE;
+ datab_node[1..0] : WIRE;
+ sum_eqn[1..0] : WIRE;
+
+BEGIN
+ carry_eqn[] = ( ((dataa[1..1] & datab_node[1..1]) # ((dataa[1..1] # datab_node[1..1]) & carry_eqn[0..0])), ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & cin_wire)));
+ cin_wire = B"1";
+ cout = carry_eqn[1..1];
+ datab_node[] = (! datab[]);
+ result[] = sum_eqn[];
+ sum_eqn[] = ( ((dataa[1..1] $ datab_node[1..1]) $ carry_eqn[0..0]), ((dataa[0..0] $ datab_node[0..0]) $ cin_wire));
+END;
+--VALID FILE
--- /dev/null
+--alt_u_div DEVICE_FAMILY="Cyclone II" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 SKIP_BITS=0 WIDTH_D=8 WIDTH_N=8 WIDTH_Q=8 WIDTH_R=8 denominator numerator quotient remainder
+--VERSION_BEGIN 7.0 cbx_cycloneii 2006:09:30:03:03:26:SJ cbx_lpm_abs 2006:04:25:22:52:42:SJ cbx_lpm_add_sub 2006:10:11:06:03:24:SJ cbx_lpm_divide 2006:01:19:01:01:10:SJ cbx_mgl 2006:10:28:00:08:48:SJ cbx_stratix 2006:09:18:18:47:42:SJ cbx_stratixii 2006:10:13:22:01:30:SJ cbx_util_mgl 2006:11:03:18:32:30:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2007 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+
+FUNCTION add_sub_lkc (dataa[0..0], datab[0..0])
+RETURNS ( cout, result[0..0]);
+FUNCTION add_sub_mkc (dataa[1..0], datab[1..0])
+RETURNS ( cout, result[1..0]);
+
+--synthesis_resources = lut 39
+SUBDESIGN alt_u_div_00f
+(
+ den_out[7..0] : output;
+ denominator[7..0] : input;
+ numerator[7..0] : input;
+ quotient[7..0] : output;
+ remainder[7..0] : output;
+)
+VARIABLE
+ add_sub_0 : add_sub_lkc;
+ add_sub_1 : add_sub_mkc;
+ add_sub_2_result_int[3..0] : WIRE;
+ add_sub_2_cout : WIRE;
+ add_sub_2_dataa[2..0] : WIRE;
+ add_sub_2_datab[2..0] : WIRE;
+ add_sub_2_result[2..0] : WIRE;
+ add_sub_3_result_int[4..0] : WIRE;
+ add_sub_3_cout : WIRE;
+ add_sub_3_dataa[3..0] : WIRE;
+ add_sub_3_datab[3..0] : WIRE;
+ add_sub_3_result[3..0] : WIRE;
+ add_sub_4_result_int[5..0] : WIRE;
+ add_sub_4_cout : WIRE;
+ add_sub_4_dataa[4..0] : WIRE;
+ add_sub_4_datab[4..0] : WIRE;
+ add_sub_4_result[4..0] : WIRE;
+ add_sub_5_result_int[6..0] : WIRE;
+ add_sub_5_cout : WIRE;
+ add_sub_5_dataa[5..0] : WIRE;
+ add_sub_5_datab[5..0] : WIRE;
+ add_sub_5_result[5..0] : WIRE;
+ add_sub_6_result_int[7..0] : WIRE;
+ add_sub_6_cout : WIRE;
+ add_sub_6_dataa[6..0] : WIRE;
+ add_sub_6_datab[6..0] : WIRE;
+ add_sub_6_result[6..0] : WIRE;
+ add_sub_7_result_int[8..0] : WIRE;
+ add_sub_7_cout : WIRE;
+ add_sub_7_dataa[7..0] : WIRE;
+ add_sub_7_datab[7..0] : WIRE;
+ add_sub_7_result[7..0] : WIRE;
+ DenominatorIn[80..0] : WIRE;
+ DenominatorIn_tmp[80..0] : WIRE;
+ gnd_wire : WIRE;
+ nose[71..0] : WIRE;
+ NumeratorIn[71..0] : WIRE;
+ NumeratorIn_tmp[71..0] : WIRE;
+ prestg[63..0] : WIRE;
+ quotient_tmp[7..0] : WIRE;
+ sel[71..0] : WIRE;
+ selnose[71..0] : WIRE;
+ StageIn[71..0] : WIRE;
+ StageIn_tmp[71..0] : WIRE;
+ StageOut[63..0] : WIRE;
+
+BEGIN
+ add_sub_0.dataa[0..0] = NumeratorIn[7..7];
+ add_sub_0.datab[0..0] = DenominatorIn[0..0];
+ add_sub_1.dataa[] = ( StageIn[8..8], NumeratorIn[14..14]);
+ add_sub_1.datab[1..0] = DenominatorIn[10..9];
+ add_sub_2_result_int[] = (0, add_sub_2_dataa[]) - (0, add_sub_2_datab[]);
+ add_sub_2_result[] = add_sub_2_result_int[2..0];
+ add_sub_2_cout = !add_sub_2_result_int[3];
+ add_sub_2_dataa[] = ( StageIn[17..16], NumeratorIn[21..21]);
+ add_sub_2_datab[] = DenominatorIn[20..18];
+ add_sub_3_result_int[] = (0, add_sub_3_dataa[]) - (0, add_sub_3_datab[]);
+ add_sub_3_result[] = add_sub_3_result_int[3..0];
+ add_sub_3_cout = !add_sub_3_result_int[4];
+ add_sub_3_dataa[] = ( StageIn[26..24], NumeratorIn[28..28]);
+ add_sub_3_datab[] = DenominatorIn[30..27];
+ add_sub_4_result_int[] = (0, add_sub_4_dataa[]) - (0, add_sub_4_datab[]);
+ add_sub_4_result[] = add_sub_4_result_int[4..0];
+ add_sub_4_cout = !add_sub_4_result_int[5];
+ add_sub_4_dataa[] = ( StageIn[35..32], NumeratorIn[35..35]);
+ add_sub_4_datab[] = DenominatorIn[40..36];
+ add_sub_5_result_int[] = (0, add_sub_5_dataa[]) - (0, add_sub_5_datab[]);
+ add_sub_5_result[] = add_sub_5_result_int[5..0];
+ add_sub_5_cout = !add_sub_5_result_int[6];
+ add_sub_5_dataa[] = ( StageIn[44..40], NumeratorIn[42..42]);
+ add_sub_5_datab[] = DenominatorIn[50..45];
+ add_sub_6_result_int[] = (0, add_sub_6_dataa[]) - (0, add_sub_6_datab[]);
+ add_sub_6_result[] = add_sub_6_result_int[6..0];
+ add_sub_6_cout = !add_sub_6_result_int[7];
+ add_sub_6_dataa[] = ( StageIn[53..48], NumeratorIn[49..49]);
+ add_sub_6_datab[] = DenominatorIn[60..54];
+ add_sub_7_result_int[] = (0, add_sub_7_dataa[]) - (0, add_sub_7_datab[]);
+ add_sub_7_result[] = add_sub_7_result_int[7..0];
+ add_sub_7_cout = !add_sub_7_result_int[8];
+ add_sub_7_dataa[] = ( StageIn[62..56], NumeratorIn[56..56]);
+ add_sub_7_datab[] = DenominatorIn[70..63];
+ den_out[7..0] = DenominatorIn[70..63];
+ DenominatorIn[] = (gnd_wire # DenominatorIn_tmp[]);
+ DenominatorIn_tmp[] = ( DenominatorIn[71..0], ( gnd_wire, denominator[]));
+ gnd_wire = B"0";
+ nose[] = ( B"00000000", (add_sub_7_cout # gnd_wire), B"00000000", (add_sub_6_cout # gnd_wire), B"00000000", (add_sub_5_cout # gnd_wire), B"00000000", (add_sub_4_cout # gnd_wire), B"00000000", (add_sub_3_cout # gnd_wire), B"00000000", (add_sub_2_cout # gnd_wire), B"00000000", (add_sub_1.cout # gnd_wire), B"00000000", (add_sub_0.cout # gnd_wire));
+ NumeratorIn[] = (gnd_wire # NumeratorIn_tmp[]);
+ NumeratorIn_tmp[] = ( NumeratorIn[63..0], numerator[]);
+ prestg[] = ( add_sub_7_result[], GND, add_sub_6_result[], B"00", add_sub_5_result[], B"000", add_sub_4_result[], B"0000", add_sub_3_result[], B"00000", add_sub_2_result[], B"000000", add_sub_1.result[], B"0000000", add_sub_0.result[]);
+ quotient[] = quotient_tmp[];
+ quotient_tmp[] = ( (! selnose[0..0]), (! selnose[9..9]), (! selnose[18..18]), (! selnose[27..27]), (! selnose[36..36]), (! selnose[45..45]), (! selnose[54..54]), (! selnose[63..63]));
+ remainder[7..0] = StageIn[71..64];
+ sel[] = ( gnd_wire, (gnd_wire # (sel[71..71] # DenominatorIn[79..79])), (gnd_wire # (sel[70..70] # DenominatorIn[78..78])), (gnd_wire # (sel[69..69] # DenominatorIn[77..77])), (gnd_wire # (sel[68..68] # DenominatorIn[76..76])), (gnd_wire # (sel[67..67] # DenominatorIn[75..75])), (gnd_wire # (sel[66..66] # DenominatorIn[74..74])), (gnd_wire # (sel[65..65] # DenominatorIn[73..73])), gnd_wire, (gnd_wire # (sel[63..63] # DenominatorIn[70..70])), (gnd_wire # (sel[62..62] # DenominatorIn[69..69])), (gnd_wire # (sel[61..61] # DenominatorIn[68..68])), (gnd_wire # (sel[60..60] # DenominatorIn[67..67])), (gnd_wire # (sel[59..59] # DenominatorIn[66..66])), (gnd_wire # (sel[58..58] # DenominatorIn[65..65])), (gnd_wire # (sel[57..57] # DenominatorIn[64..64])), gnd_wire, (gnd_wire # (sel[55..55] # DenominatorIn[61..61])), (gnd_wire # (sel[54..54] # DenominatorIn[60..60])), (gnd_wire # (sel[53..53] # DenominatorIn[59..59])), (gnd_wire # (sel[52..52] # DenominatorIn[58..58])), (gnd_wire # (sel[51..51] # DenominatorIn[57..57])), (gnd_wire # (sel[50..50] # DenominatorIn[56..56])), (gnd_wire # (sel[49..49] # DenominatorIn[55..55])), gnd_wire, (gnd_wire # (sel[47..47] # DenominatorIn[52..52])), (gnd_wire # (sel[46..46] # DenominatorIn[51..51])), (gnd_wire # (sel[45..45] # DenominatorIn[50..50])), (gnd_wire # (sel[44..44] # DenominatorIn[49..49])), (gnd_wire # (sel[43..43] # DenominatorIn[48..48])), (gnd_wire # (sel[42..42] # DenominatorIn[47..47])), (gnd_wire # (sel[41..41] # DenominatorIn[46..46])), gnd_wire, (gnd_wire # (sel[39..39] # DenominatorIn[43..43])), (gnd_wire # (sel[38..38] # DenominatorIn[42..42])), (gnd_wire # (sel[37..37] # DenominatorIn[41..41])), (gnd_wire # (sel[36..36] # DenominatorIn[40..40])), (gnd_wire # (sel[35..35] # DenominatorIn[39..39])), (gnd_wire # (sel[34..34] # DenominatorIn[38..38])), (gnd_wire # (sel[33..33] # DenominatorIn[37..37])), gnd_wire, (gnd_wire # (sel[31..31] # DenominatorIn[34..34])), (gnd_wire # (sel[30..30] # DenominatorIn[33..33])), (gnd_wire # (sel[29..29] # DenominatorIn[32..32])), (gnd_wire # (sel[28..28] # DenominatorIn[31..31])), (gnd_wire # (sel[27..27] # DenominatorIn[30..30])), (gnd_wire # (sel[26..26] # DenominatorIn[29..29])), (gnd_wire # (sel[25..25] # DenominatorIn[28..28])), gnd_wire, (gnd_wire # (sel[23..23] # DenominatorIn[25..25])), (gnd_wire # (sel[22..22] # DenominatorIn[24..24])), (gnd_wire # (sel[21..21] # DenominatorIn[23..23])), (gnd_wire # (sel[20..20] # DenominatorIn[22..22])), (gnd_wire # (sel[19..19] # DenominatorIn[21..21])), (gnd_wire # (sel[18..18] # DenominatorIn[20..20])), (gnd_wire # (sel[17..17] # DenominatorIn[19..19])), gnd_wire, (gnd_wire # (sel[15..15] # DenominatorIn[16..16])), (gnd_wire # (sel[14..14] # DenominatorIn[15..15])), (gnd_wire # (sel[13..13] # DenominatorIn[14..14])), (gnd_wire # (sel[12..12] # DenominatorIn[13..13])), (gnd_wire # (sel[11..11] # DenominatorIn[12..12])), (gnd_wire # (sel[10..10] # DenominatorIn[11..11])), (gnd_wire # (sel[9..9] # DenominatorIn[10..10])), gnd_wire, (gnd_wire # (sel[7..7] # DenominatorIn[7..7])), (gnd_wire # (sel[6..6] # DenominatorIn[6..6])), (gnd_wire # (sel[5..5] # DenominatorIn[5..5])), (gnd_wire # (sel[4..4] # DenominatorIn[4..4])), (gnd_wire # (sel[3..3] # DenominatorIn[3..3])), (gnd_wire # (sel[2..2] # DenominatorIn[2..2])), (gnd_wire # (sel[1..1] # DenominatorIn[1..1])));
+ selnose[] = ( ((gnd_wire # (! nose[71..71])) # sel[71..71]), ((gnd_wire # (! nose[70..70])) # sel[70..70]), ((gnd_wire # (! nose[69..69])) # sel[69..69]), ((gnd_wire # (! nose[68..68])) # sel[68..68]), ((gnd_wire # (! nose[67..67])) # sel[67..67]), ((gnd_wire # (! nose[66..66])) # sel[66..66]), ((gnd_wire # (! nose[65..65])) # sel[65..65]), ((gnd_wire # (! nose[64..64])) # sel[64..64]), ((gnd_wire # (! nose[63..63])) # sel[63..63]), ((gnd_wire # (! nose[62..62])) # sel[62..62]), ((gnd_wire # (! nose[61..61])) # sel[61..61]), ((gnd_wire # (! nose[60..60])) # sel[60..60]), ((gnd_wire # (! nose[59..59])) # sel[59..59]), ((gnd_wire # (! nose[58..58])) # sel[58..58]), ((gnd_wire # (! nose[57..57])) # sel[57..57]), ((gnd_wire # (! nose[56..56])) # sel[56..56]), ((gnd_wire # (! nose[55..55])) # sel[55..55]), ((gnd_wire # (! nose[54..54])) # sel[54..54]), ((gnd_wire # (! nose[53..53])) # sel[53..53]), ((gnd_wire # (! nose[52..52])) # sel[52..52]), ((gnd_wire # (! nose[51..51])) # sel[51..51]), ((gnd_wire # (! nose[50..50])) # sel[50..50]), ((gnd_wire # (! nose[49..49])) # sel[49..49]), ((gnd_wire # (! nose[48..48])) # sel[48..48]), ((gnd_wire # (! nose[47..47])) # sel[47..47]), ((gnd_wire # (! nose[46..46])) # sel[46..46]), ((gnd_wire # (! nose[45..45])) # sel[45..45]), ((gnd_wire # (! nose[44..44])) # sel[44..44]), ((gnd_wire # (! nose[43..43])) # sel[43..43]), ((gnd_wire # (! nose[42..42])) # sel[42..42]), ((gnd_wire # (! nose[41..41])) # sel[41..41]), ((gnd_wire # (! nose[40..40])) # sel[40..40]), ((gnd_wire # (! nose[39..39])) # sel[39..39]), ((gnd_wire # (! nose[38..38])) # sel[38..38]), ((gnd_wire # (! nose[37..37])) # sel[37..37]), ((gnd_wire # (! nose[36..36])) # sel[36..36]), ((gnd_wire # (! nose[35..35])) # sel[35..35]), ((gnd_wire # (! nose[34..34])) # sel[34..34]), ((gnd_wire # (! nose[33..33])) # sel[33..33]), ((gnd_wire # (! nose[32..32])) # sel[32..32]), ((gnd_wire # (! nose[31..31])) # sel[31..31]), ((gnd_wire # (! nose[30..30])) # sel[30..30]), ((gnd_wire # (! nose[29..29])) # sel[29..29]), ((gnd_wire # (! nose[28..28])) # sel[28..28]), ((gnd_wire # (! nose[27..27])) # sel[27..27]), ((gnd_wire # (! nose[26..26])) # sel[26..26]), ((gnd_wire # (! nose[25..25])) # sel[25..25]), ((gnd_wire # (! nose[24..24])) # sel[24..24]), ((gnd_wire # (! nose[23..23])) # sel[23..23]), ((gnd_wire # (! nose[22..22])) # sel[22..22]), ((gnd_wire # (! nose[21..21])) # sel[21..21]), ((gnd_wire # (! nose[20..20])) # sel[20..20]), ((gnd_wire # (! nose[19..19])) # sel[19..19]), ((gnd_wire # (! nose[18..18])) # sel[18..18]), ((gnd_wire # (! nose[17..17])) # sel[17..17]), ((gnd_wire # (! nose[16..16])) # sel[16..16]), ((gnd_wire # (! nose[15..15])) # sel[15..15]), ((gnd_wire # (! nose[14..14])) # sel[14..14]), ((gnd_wire # (! nose[13..13])) # sel[13..13]), ((gnd_wire # (! nose[12..12])) # sel[12..12]), ((gnd_wire # (! nose[11..11])) # sel[11..11]), ((gnd_wire # (! nose[10..10])) # sel[10..10]), ((gnd_wire # (! nose[9..9])) # sel[9..9]), ((gnd_wire # (! nose[8..8])) # sel[8..8]), ((gnd_wire # (! nose[7..7])) # sel[7..7]), ((gnd_wire # (! nose[6..6])) # sel[6..6]), ((gnd_wire # (! nose[5..5])) # sel[5..5]), ((gnd_wire # (! nose[4..4])) # sel[4..4]), ((gnd_wire # (! nose[3..3])) # sel[3..3]), ((gnd_wire # (! nose[2..2])) # sel[2..2]), ((gnd_wire # (! nose[1..1])) # sel[1..1]), ((gnd_wire # (! nose[0..0])) # sel[0..0]));
+ StageIn[] = (gnd_wire # StageIn_tmp[]);
+ StageIn_tmp[] = ( StageOut[63..0], B"00000000");
+ StageOut[] = ( ((( StageIn[62..56], NumeratorIn[56..56]) & selnose[63..63]) # (prestg[63..56] & (! selnose[63..63]))), ((( StageIn[54..48], NumeratorIn[49..49]) & selnose[54..54]) # (prestg[55..48] & (! selnose[54..54]))), ((( StageIn[46..40], NumeratorIn[42..42]) & selnose[45..45]) # (prestg[47..40] & (! selnose[45..45]))), ((( StageIn[38..32], NumeratorIn[35..35]) & selnose[36..36]) # (prestg[39..32] & (! selnose[36..36]))), ((( StageIn[30..24], NumeratorIn[28..28]) & selnose[27..27]) # (prestg[31..24] & (! selnose[27..27]))), ((( StageIn[22..16], NumeratorIn[21..21]) & selnose[18..18]) # (prestg[23..16] & (! selnose[18..18]))), ((( StageIn[14..8], NumeratorIn[14..14]) & selnose[9..9]) # (prestg[15..8] & (! selnose[9..9]))), ((( StageIn[6..0], NumeratorIn[7..7]) & selnose[0..0]) # (prestg[7..0] & (! selnose[0..0]))));
+END;
+--VALID FILE
--- /dev/null
+--alt_u_div DEVICE_FAMILY="Cyclone II" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 SKIP_BITS=0 WIDTH_D=25 WIDTH_N=25 WIDTH_Q=25 WIDTH_R=25 denominator numerator quotient remainder
+--VERSION_BEGIN 7.0 cbx_cycloneii 2006:09:30:03:03:26:SJ cbx_lpm_abs 2006:04:25:22:52:42:SJ cbx_lpm_add_sub 2006:10:11:06:03:24:SJ cbx_lpm_divide 2006:01:19:01:01:10:SJ cbx_mgl 2006:10:28:00:08:48:SJ cbx_stratix 2006:09:18:18:47:42:SJ cbx_stratixii 2006:10:13:22:01:30:SJ cbx_util_mgl 2006:11:03:18:32:30:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2007 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+
+FUNCTION add_sub_lkc (dataa[0..0], datab[0..0])
+RETURNS ( cout, result[0..0]);
+FUNCTION add_sub_mkc (dataa[1..0], datab[1..0])
+RETURNS ( cout, result[1..0]);
+
+--synthesis_resources = lut 345
+SUBDESIGN alt_u_div_s5f
+(
+ den_out[24..0] : output;
+ denominator[24..0] : input;
+ numerator[24..0] : input;
+ quotient[24..0] : output;
+ remainder[24..0] : output;
+)
+VARIABLE
+ add_sub_0 : add_sub_lkc;
+ add_sub_1 : add_sub_mkc;
+ add_sub_10_result_int[11..0] : WIRE;
+ add_sub_10_cout : WIRE;
+ add_sub_10_dataa[10..0] : WIRE;
+ add_sub_10_datab[10..0] : WIRE;
+ add_sub_10_result[10..0] : WIRE;
+ add_sub_11_result_int[12..0] : WIRE;
+ add_sub_11_cout : WIRE;
+ add_sub_11_dataa[11..0] : WIRE;
+ add_sub_11_datab[11..0] : WIRE;
+ add_sub_11_result[11..0] : WIRE;
+ add_sub_12_result_int[13..0] : WIRE;
+ add_sub_12_cout : WIRE;
+ add_sub_12_dataa[12..0] : WIRE;
+ add_sub_12_datab[12..0] : WIRE;
+ add_sub_12_result[12..0] : WIRE;
+ add_sub_13_result_int[14..0] : WIRE;
+ add_sub_13_cout : WIRE;
+ add_sub_13_dataa[13..0] : WIRE;
+ add_sub_13_datab[13..0] : WIRE;
+ add_sub_13_result[13..0] : WIRE;
+ add_sub_14_result_int[15..0] : WIRE;
+ add_sub_14_cout : WIRE;
+ add_sub_14_dataa[14..0] : WIRE;
+ add_sub_14_datab[14..0] : WIRE;
+ add_sub_14_result[14..0] : WIRE;
+ add_sub_15_result_int[16..0] : WIRE;
+ add_sub_15_cout : WIRE;
+ add_sub_15_dataa[15..0] : WIRE;
+ add_sub_15_datab[15..0] : WIRE;
+ add_sub_15_result[15..0] : WIRE;
+ add_sub_16_result_int[17..0] : WIRE;
+ add_sub_16_cout : WIRE;
+ add_sub_16_dataa[16..0] : WIRE;
+ add_sub_16_datab[16..0] : WIRE;
+ add_sub_16_result[16..0] : WIRE;
+ add_sub_17_result_int[18..0] : WIRE;
+ add_sub_17_cout : WIRE;
+ add_sub_17_dataa[17..0] : WIRE;
+ add_sub_17_datab[17..0] : WIRE;
+ add_sub_17_result[17..0] : WIRE;
+ add_sub_18_result_int[19..0] : WIRE;
+ add_sub_18_cout : WIRE;
+ add_sub_18_dataa[18..0] : WIRE;
+ add_sub_18_datab[18..0] : WIRE;
+ add_sub_18_result[18..0] : WIRE;
+ add_sub_19_result_int[20..0] : WIRE;
+ add_sub_19_cout : WIRE;
+ add_sub_19_dataa[19..0] : WIRE;
+ add_sub_19_datab[19..0] : WIRE;
+ add_sub_19_result[19..0] : WIRE;
+ add_sub_2_result_int[3..0] : WIRE;
+ add_sub_2_cout : WIRE;
+ add_sub_2_dataa[2..0] : WIRE;
+ add_sub_2_datab[2..0] : WIRE;
+ add_sub_2_result[2..0] : WIRE;
+ add_sub_20_result_int[21..0] : WIRE;
+ add_sub_20_cout : WIRE;
+ add_sub_20_dataa[20..0] : WIRE;
+ add_sub_20_datab[20..0] : WIRE;
+ add_sub_20_result[20..0] : WIRE;
+ add_sub_21_result_int[22..0] : WIRE;
+ add_sub_21_cout : WIRE;
+ add_sub_21_dataa[21..0] : WIRE;
+ add_sub_21_datab[21..0] : WIRE;
+ add_sub_21_result[21..0] : WIRE;
+ add_sub_22_result_int[23..0] : WIRE;
+ add_sub_22_cout : WIRE;
+ add_sub_22_dataa[22..0] : WIRE;
+ add_sub_22_datab[22..0] : WIRE;
+ add_sub_22_result[22..0] : WIRE;
+ add_sub_23_result_int[24..0] : WIRE;
+ add_sub_23_cout : WIRE;
+ add_sub_23_dataa[23..0] : WIRE;
+ add_sub_23_datab[23..0] : WIRE;
+ add_sub_23_result[23..0] : WIRE;
+ add_sub_24_result_int[25..0] : WIRE;
+ add_sub_24_cout : WIRE;
+ add_sub_24_dataa[24..0] : WIRE;
+ add_sub_24_datab[24..0] : WIRE;
+ add_sub_24_result[24..0] : WIRE;
+ add_sub_3_result_int[4..0] : WIRE;
+ add_sub_3_cout : WIRE;
+ add_sub_3_dataa[3..0] : WIRE;
+ add_sub_3_datab[3..0] : WIRE;
+ add_sub_3_result[3..0] : WIRE;
+ add_sub_4_result_int[5..0] : WIRE;
+ add_sub_4_cout : WIRE;
+ add_sub_4_dataa[4..0] : WIRE;
+ add_sub_4_datab[4..0] : WIRE;
+ add_sub_4_result[4..0] : WIRE;
+ add_sub_5_result_int[6..0] : WIRE;
+ add_sub_5_cout : WIRE;
+ add_sub_5_dataa[5..0] : WIRE;
+ add_sub_5_datab[5..0] : WIRE;
+ add_sub_5_result[5..0] : WIRE;
+ add_sub_6_result_int[7..0] : WIRE;
+ add_sub_6_cout : WIRE;
+ add_sub_6_dataa[6..0] : WIRE;
+ add_sub_6_datab[6..0] : WIRE;
+ add_sub_6_result[6..0] : WIRE;
+ add_sub_7_result_int[8..0] : WIRE;
+ add_sub_7_cout : WIRE;
+ add_sub_7_dataa[7..0] : WIRE;
+ add_sub_7_datab[7..0] : WIRE;
+ add_sub_7_result[7..0] : WIRE;
+ add_sub_8_result_int[9..0] : WIRE;
+ add_sub_8_cout : WIRE;
+ add_sub_8_dataa[8..0] : WIRE;
+ add_sub_8_datab[8..0] : WIRE;
+ add_sub_8_result[8..0] : WIRE;
+ add_sub_9_result_int[10..0] : WIRE;
+ add_sub_9_cout : WIRE;
+ add_sub_9_dataa[9..0] : WIRE;
+ add_sub_9_datab[9..0] : WIRE;
+ add_sub_9_result[9..0] : WIRE;
+ DenominatorIn[675..0] : WIRE;
+ DenominatorIn_tmp[675..0] : WIRE;
+ gnd_wire : WIRE;
+ nose[649..0] : WIRE;
+ NumeratorIn[649..0] : WIRE;
+ NumeratorIn_tmp[649..0] : WIRE;
+ prestg[624..0] : WIRE;
+ quotient_tmp[24..0] : WIRE;
+ sel[649..0] : WIRE;
+ selnose[649..0] : WIRE;
+ StageIn[649..0] : WIRE;
+ StageIn_tmp[649..0] : WIRE;
+ StageOut[624..0] : WIRE;
+
+BEGIN
+ add_sub_0.dataa[0..0] = NumeratorIn[24..24];
+ add_sub_0.datab[0..0] = DenominatorIn[0..0];
+ add_sub_1.dataa[] = ( StageIn[25..25], NumeratorIn[48..48]);
+ add_sub_1.datab[1..0] = DenominatorIn[27..26];
+ add_sub_10_result_int[] = (0, add_sub_10_dataa[]) - (0, add_sub_10_datab[]);
+ add_sub_10_result[] = add_sub_10_result_int[10..0];
+ add_sub_10_cout = !add_sub_10_result_int[11];
+ add_sub_10_dataa[] = ( StageIn[259..250], NumeratorIn[264..264]);
+ add_sub_10_datab[] = DenominatorIn[270..260];
+ add_sub_11_result_int[] = (0, add_sub_11_dataa[]) - (0, add_sub_11_datab[]);
+ add_sub_11_result[] = add_sub_11_result_int[11..0];
+ add_sub_11_cout = !add_sub_11_result_int[12];
+ add_sub_11_dataa[] = ( StageIn[285..275], NumeratorIn[288..288]);
+ add_sub_11_datab[] = DenominatorIn[297..286];
+ add_sub_12_result_int[] = (0, add_sub_12_dataa[]) - (0, add_sub_12_datab[]);
+ add_sub_12_result[] = add_sub_12_result_int[12..0];
+ add_sub_12_cout = !add_sub_12_result_int[13];
+ add_sub_12_dataa[] = ( StageIn[311..300], NumeratorIn[312..312]);
+ add_sub_12_datab[] = DenominatorIn[324..312];
+ add_sub_13_result_int[] = (0, add_sub_13_dataa[]) - (0, add_sub_13_datab[]);
+ add_sub_13_result[] = add_sub_13_result_int[13..0];
+ add_sub_13_cout = !add_sub_13_result_int[14];
+ add_sub_13_dataa[] = ( StageIn[337..325], NumeratorIn[336..336]);
+ add_sub_13_datab[] = DenominatorIn[351..338];
+ add_sub_14_result_int[] = (0, add_sub_14_dataa[]) - (0, add_sub_14_datab[]);
+ add_sub_14_result[] = add_sub_14_result_int[14..0];
+ add_sub_14_cout = !add_sub_14_result_int[15];
+ add_sub_14_dataa[] = ( StageIn[363..350], NumeratorIn[360..360]);
+ add_sub_14_datab[] = DenominatorIn[378..364];
+ add_sub_15_result_int[] = (0, add_sub_15_dataa[]) - (0, add_sub_15_datab[]);
+ add_sub_15_result[] = add_sub_15_result_int[15..0];
+ add_sub_15_cout = !add_sub_15_result_int[16];
+ add_sub_15_dataa[] = ( StageIn[389..375], NumeratorIn[384..384]);
+ add_sub_15_datab[] = DenominatorIn[405..390];
+ add_sub_16_result_int[] = (0, add_sub_16_dataa[]) - (0, add_sub_16_datab[]);
+ add_sub_16_result[] = add_sub_16_result_int[16..0];
+ add_sub_16_cout = !add_sub_16_result_int[17];
+ add_sub_16_dataa[] = ( StageIn[415..400], NumeratorIn[408..408]);
+ add_sub_16_datab[] = DenominatorIn[432..416];
+ add_sub_17_result_int[] = (0, add_sub_17_dataa[]) - (0, add_sub_17_datab[]);
+ add_sub_17_result[] = add_sub_17_result_int[17..0];
+ add_sub_17_cout = !add_sub_17_result_int[18];
+ add_sub_17_dataa[] = ( StageIn[441..425], NumeratorIn[432..432]);
+ add_sub_17_datab[] = DenominatorIn[459..442];
+ add_sub_18_result_int[] = (0, add_sub_18_dataa[]) - (0, add_sub_18_datab[]);
+ add_sub_18_result[] = add_sub_18_result_int[18..0];
+ add_sub_18_cout = !add_sub_18_result_int[19];
+ add_sub_18_dataa[] = ( StageIn[467..450], NumeratorIn[456..456]);
+ add_sub_18_datab[] = DenominatorIn[486..468];
+ add_sub_19_result_int[] = (0, add_sub_19_dataa[]) - (0, add_sub_19_datab[]);
+ add_sub_19_result[] = add_sub_19_result_int[19..0];
+ add_sub_19_cout = !add_sub_19_result_int[20];
+ add_sub_19_dataa[] = ( StageIn[493..475], NumeratorIn[480..480]);
+ add_sub_19_datab[] = DenominatorIn[513..494];
+ add_sub_2_result_int[] = (0, add_sub_2_dataa[]) - (0, add_sub_2_datab[]);
+ add_sub_2_result[] = add_sub_2_result_int[2..0];
+ add_sub_2_cout = !add_sub_2_result_int[3];
+ add_sub_2_dataa[] = ( StageIn[51..50], NumeratorIn[72..72]);
+ add_sub_2_datab[] = DenominatorIn[54..52];
+ add_sub_20_result_int[] = (0, add_sub_20_dataa[]) - (0, add_sub_20_datab[]);
+ add_sub_20_result[] = add_sub_20_result_int[20..0];
+ add_sub_20_cout = !add_sub_20_result_int[21];
+ add_sub_20_dataa[] = ( StageIn[519..500], NumeratorIn[504..504]);
+ add_sub_20_datab[] = DenominatorIn[540..520];
+ add_sub_21_result_int[] = (0, add_sub_21_dataa[]) - (0, add_sub_21_datab[]);
+ add_sub_21_result[] = add_sub_21_result_int[21..0];
+ add_sub_21_cout = !add_sub_21_result_int[22];
+ add_sub_21_dataa[] = ( StageIn[545..525], NumeratorIn[528..528]);
+ add_sub_21_datab[] = DenominatorIn[567..546];
+ add_sub_22_result_int[] = (0, add_sub_22_dataa[]) - (0, add_sub_22_datab[]);
+ add_sub_22_result[] = add_sub_22_result_int[22..0];
+ add_sub_22_cout = !add_sub_22_result_int[23];
+ add_sub_22_dataa[] = ( StageIn[571..550], NumeratorIn[552..552]);
+ add_sub_22_datab[] = DenominatorIn[594..572];
+ add_sub_23_result_int[] = (0, add_sub_23_dataa[]) - (0, add_sub_23_datab[]);
+ add_sub_23_result[] = add_sub_23_result_int[23..0];
+ add_sub_23_cout = !add_sub_23_result_int[24];
+ add_sub_23_dataa[] = ( StageIn[597..575], NumeratorIn[576..576]);
+ add_sub_23_datab[] = DenominatorIn[621..598];
+ add_sub_24_result_int[] = (0, add_sub_24_dataa[]) - (0, add_sub_24_datab[]);
+ add_sub_24_result[] = add_sub_24_result_int[24..0];
+ add_sub_24_cout = !add_sub_24_result_int[25];
+ add_sub_24_dataa[] = ( StageIn[623..600], NumeratorIn[600..600]);
+ add_sub_24_datab[] = DenominatorIn[648..624];
+ add_sub_3_result_int[] = (0, add_sub_3_dataa[]) - (0, add_sub_3_datab[]);
+ add_sub_3_result[] = add_sub_3_result_int[3..0];
+ add_sub_3_cout = !add_sub_3_result_int[4];
+ add_sub_3_dataa[] = ( StageIn[77..75], NumeratorIn[96..96]);
+ add_sub_3_datab[] = DenominatorIn[81..78];
+ add_sub_4_result_int[] = (0, add_sub_4_dataa[]) - (0, add_sub_4_datab[]);
+ add_sub_4_result[] = add_sub_4_result_int[4..0];
+ add_sub_4_cout = !add_sub_4_result_int[5];
+ add_sub_4_dataa[] = ( StageIn[103..100], NumeratorIn[120..120]);
+ add_sub_4_datab[] = DenominatorIn[108..104];
+ add_sub_5_result_int[] = (0, add_sub_5_dataa[]) - (0, add_sub_5_datab[]);
+ add_sub_5_result[] = add_sub_5_result_int[5..0];
+ add_sub_5_cout = !add_sub_5_result_int[6];
+ add_sub_5_dataa[] = ( StageIn[129..125], NumeratorIn[144..144]);
+ add_sub_5_datab[] = DenominatorIn[135..130];
+ add_sub_6_result_int[] = (0, add_sub_6_dataa[]) - (0, add_sub_6_datab[]);
+ add_sub_6_result[] = add_sub_6_result_int[6..0];
+ add_sub_6_cout = !add_sub_6_result_int[7];
+ add_sub_6_dataa[] = ( StageIn[155..150], NumeratorIn[168..168]);
+ add_sub_6_datab[] = DenominatorIn[162..156];
+ add_sub_7_result_int[] = (0, add_sub_7_dataa[]) - (0, add_sub_7_datab[]);
+ add_sub_7_result[] = add_sub_7_result_int[7..0];
+ add_sub_7_cout = !add_sub_7_result_int[8];
+ add_sub_7_dataa[] = ( StageIn[181..175], NumeratorIn[192..192]);
+ add_sub_7_datab[] = DenominatorIn[189..182];
+ add_sub_8_result_int[] = (0, add_sub_8_dataa[]) - (0, add_sub_8_datab[]);
+ add_sub_8_result[] = add_sub_8_result_int[8..0];
+ add_sub_8_cout = !add_sub_8_result_int[9];
+ add_sub_8_dataa[] = ( StageIn[207..200], NumeratorIn[216..216]);
+ add_sub_8_datab[] = DenominatorIn[216..208];
+ add_sub_9_result_int[] = (0, add_sub_9_dataa[]) - (0, add_sub_9_datab[]);
+ add_sub_9_result[] = add_sub_9_result_int[9..0];
+ add_sub_9_cout = !add_sub_9_result_int[10];
+ add_sub_9_dataa[] = ( StageIn[233..225], NumeratorIn[240..240]);
+ add_sub_9_datab[] = DenominatorIn[243..234];
+ den_out[24..0] = DenominatorIn[648..624];
+ DenominatorIn[] = (gnd_wire # DenominatorIn_tmp[]);
+ DenominatorIn_tmp[] = ( DenominatorIn[649..0], ( gnd_wire, denominator[]));
+ gnd_wire = B"0";
+ nose[] = ( B"0000000000000000000000000", (add_sub_24_cout # gnd_wire), B"0000000000000000000000000", (add_sub_23_cout # gnd_wire), B"0000000000000000000000000", (add_sub_22_cout # gnd_wire), B"0000000000000000000000000", (add_sub_21_cout # gnd_wire), B"0000000000000000000000000", (add_sub_20_cout # gnd_wire), B"0000000000000000000000000", (add_sub_19_cout # gnd_wire), B"0000000000000000000000000", (add_sub_18_cout # gnd_wire), B"0000000000000000000000000", (add_sub_17_cout # gnd_wire), B"0000000000000000000000000", (add_sub_16_cout # gnd_wire), B"0000000000000000000000000", (add_sub_15_cout # gnd_wire), B"0000000000000000000000000", (add_sub_14_cout # gnd_wire), B"0000000000000000000000000", (add_sub_13_cout # gnd_wire), B"0000000000000000000000000", (add_sub_12_cout # gnd_wire), B"0000000000000000000000000", (add_sub_11_cout # gnd_wire), B"0000000000000000000000000", (add_sub_10_cout # gnd_wire), B"0000000000000000000000000", (add_sub_9_cout # gnd_wire), B"0000000000000000000000000", (add_sub_8_cout # gnd_wire), B"0000000000000000000000000", (add_sub_7_cout # gnd_wire), B"0000000000000000000000000", (add_sub_6_cout # gnd_wire), B"0000000000000000000000000", (add_sub_5_cout # gnd_wire), B"0000000000000000000000000", (add_sub_4_cout # gnd_wire), B"0000000000000000000000000", (add_sub_3_cout # gnd_wire), B"0000000000000000000000000", (add_sub_2_cout # gnd_wire), B"0000000000000000000000000", (add_sub_1.cout # gnd_wire), B"0000000000000000000000000", (add_sub_0.cout # gnd_wire));
+ NumeratorIn[] = (gnd_wire # NumeratorIn_tmp[]);
+ NumeratorIn_tmp[] = ( NumeratorIn[624..0], numerator[]);
+ prestg[] = ( add_sub_24_result[], GND, add_sub_23_result[], B"00", add_sub_22_result[], B"000", add_sub_21_result[], B"0000", add_sub_20_result[], B"00000", add_sub_19_result[], B"000000", add_sub_18_result[], B"0000000", add_sub_17_result[], B"00000000", add_sub_16_result[], B"000000000", add_sub_15_result[], B"0000000000", add_sub_14_result[], B"00000000000", add_sub_13_result[], B"000000000000", add_sub_12_result[], B"0000000000000", add_sub_11_result[], B"00000000000000", add_sub_10_result[], B"000000000000000", add_sub_9_result[], B"0000000000000000", add_sub_8_result[], B"00000000000000000", add_sub_7_result[], B"000000000000000000", add_sub_6_result[], B"0000000000000000000", add_sub_5_result[], B"00000000000000000000", add_sub_4_result[], B"000000000000000000000", add_sub_3_result[], B"0000000000000000000000", add_sub_2_result[], B"00000000000000000000000", add_sub_1.result[], B"000000000000000000000000", add_sub_0.result[]);
+ quotient[] = quotient_tmp[];
+ quotient_tmp[] = ( (! selnose[0..0]), (! selnose[26..26]), (! selnose[52..52]), (! selnose[78..78]), (! selnose[104..104]), (! selnose[130..130]), (! selnose[156..156]), (! selnose[182..182]), (! selnose[208..208]), (! selnose[234..234]), (! selnose[260..260]), (! selnose[286..286]), (! selnose[312..312]), (! selnose[338..338]), (! selnose[364..364]), (! selnose[390..390]), (! selnose[416..416]), (! selnose[442..442]), (! selnose[468..468]), (! selnose[494..494]), (! selnose[520..520]), (! selnose[546..546]), (! selnose[572..572]), (! selnose[598..598]), (! selnose[624..624]));
+ remainder[24..0] = StageIn[649..625];
+ sel[] = ( gnd_wire, (gnd_wire # (sel[649..649] # DenominatorIn[674..674])), (gnd_wire # (sel[648..648] # DenominatorIn[673..673])), (gnd_wire # (sel[647..647] # DenominatorIn[672..672])), (gnd_wire # (sel[646..646] # DenominatorIn[671..671])), (gnd_wire # (sel[645..645] # DenominatorIn[670..670])), (gnd_wire # (sel[644..644] # DenominatorIn[669..669])), (gnd_wire # (sel[643..643] # DenominatorIn[668..668])), (gnd_wire # (sel[642..642] # DenominatorIn[667..667])), (gnd_wire # (sel[641..641] # DenominatorIn[666..666])), (gnd_wire # (sel[640..640] # DenominatorIn[665..665])), (gnd_wire # (sel[639..639] # DenominatorIn[664..664])), (gnd_wire # (sel[638..638] # DenominatorIn[663..663])), (gnd_wire # (sel[637..637] # DenominatorIn[662..662])), (gnd_wire # (sel[636..636] # DenominatorIn[661..661])), (gnd_wire # (sel[635..635] # DenominatorIn[660..660])), (gnd_wire # (sel[634..634] # DenominatorIn[659..659])), (gnd_wire # (sel[633..633] # DenominatorIn[658..658])), (gnd_wire # (sel[632..632] # DenominatorIn[657..657])), (gnd_wire # (sel[631..631] # DenominatorIn[656..656])), (gnd_wire # (sel[630..630] # DenominatorIn[655..655])), (gnd_wire # (sel[629..629] # DenominatorIn[654..654])), (gnd_wire # (sel[628..628] # DenominatorIn[653..653])), (gnd_wire # (sel[627..627] # DenominatorIn[652..652])), (gnd_wire # (sel[626..626] # DenominatorIn[651..651])), gnd_wire, (gnd_wire # (sel[624..624] # DenominatorIn[648..648])), (gnd_wire # (sel[623..623] # DenominatorIn[647..647])), (gnd_wire # (sel[622..622] # DenominatorIn[646..646])), (gnd_wire # (sel[621..621] # DenominatorIn[645..645])), (gnd_wire # (sel[620..620] # DenominatorIn[644..644])), (gnd_wire # (sel[619..619] # DenominatorIn[643..643])), (gnd_wire # (sel[618..618] # DenominatorIn[642..642])), (gnd_wire # (sel[617..617] # DenominatorIn[641..641])), (gnd_wire # (sel[616..616] # DenominatorIn[640..640])), (gnd_wire # (sel[615..615] # DenominatorIn[639..639])), (gnd_wire # (sel[614..614] # DenominatorIn[638..638])), (gnd_wire # (sel[613..613] # DenominatorIn[637..637])), (gnd_wire # (sel[612..612] # DenominatorIn[636..636])), (gnd_wire # (sel[611..611] # DenominatorIn[635..635])), (gnd_wire # (sel[610..610] # DenominatorIn[634..634])), (gnd_wire # (sel[609..609] # DenominatorIn[633..633])), (gnd_wire # (sel[608..608] # DenominatorIn[632..632])), (gnd_wire # (sel[607..607] # DenominatorIn[631..631])), (gnd_wire # (sel[606..606] # DenominatorIn[630..630])), (gnd_wire # (sel[605..605] # DenominatorIn[629..629])), (gnd_wire # (sel[604..604] # DenominatorIn[628..628])), (gnd_wire # (sel[603..603] # DenominatorIn[627..627])), (gnd_wire # (sel[602..602] # DenominatorIn[626..626])), (gnd_wire # (sel[601..601] # DenominatorIn[625..625])), gnd_wire, (gnd_wire # (sel[599..599] # DenominatorIn[622..622])), (gnd_wire # (sel[598..598] # DenominatorIn[621..621])), (gnd_wire # (sel[597..597] # DenominatorIn[620..620])), (gnd_wire # (sel[596..596] # DenominatorIn[619..619])), (gnd_wire # (sel[595..595] # DenominatorIn[618..618])), (gnd_wire # (sel[594..594] # DenominatorIn[617..617])), (gnd_wire # (sel[593..593] # DenominatorIn[616..616])), (gnd_wire # (sel[592..592] # DenominatorIn[615..615])), (gnd_wire # (sel[591..591] # DenominatorIn[614..614])), (gnd_wire # (sel[590..590] # DenominatorIn[613..613])), (gnd_wire # (sel[589..589] # DenominatorIn[612..612])), (gnd_wire # (sel[588..588] # DenominatorIn[611..611])), (gnd_wire # (sel[587..587] # DenominatorIn[610..610])), (gnd_wire # (sel[586..586] # DenominatorIn[609..609])), (gnd_wire # (sel[585..585] # DenominatorIn[608..608])), (gnd_wire # (sel[584..584] # DenominatorIn[607..607])), (gnd_wire # (sel[583..583] # DenominatorIn[606..606])), (gnd_wire # (sel[582..582] # DenominatorIn[605..605])), (gnd_wire # (sel[581..581] # DenominatorIn[604..604])), (gnd_wire # (sel[580..580] # DenominatorIn[603..603])), (gnd_wire # (sel[579..579] # DenominatorIn[602..602])), (gnd_wire # (sel[578..578] # DenominatorIn[601..601])), (gnd_wire # (sel[577..577] # DenominatorIn[600..600])), (gnd_wire # (sel[576..576] # DenominatorIn[599..599])), gnd_wire, (gnd_wire # (sel[574..574] # DenominatorIn[596..596])), (gnd_wire # (sel[573..573] # DenominatorIn[595..595])), (gnd_wire # (sel[572..572] # DenominatorIn[594..594])), (gnd_wire # (sel[571..571] # DenominatorIn[593..593])), (gnd_wire # (sel[570..570] # DenominatorIn[592..592])), (gnd_wire # (sel[569..569] # DenominatorIn[591..591])), (gnd_wire # (sel[568..568] # DenominatorIn[590..590])), (gnd_wire # (sel[567..567] # DenominatorIn[589..589])), (gnd_wire # (sel[566..566] # DenominatorIn[588..588])), (gnd_wire # (sel[565..565] # DenominatorIn[587..587])), (gnd_wire # (sel[564..564] # DenominatorIn[586..586])), (gnd_wire # (sel[563..563] # DenominatorIn[585..585])), (gnd_wire # (sel[562..562] # DenominatorIn[584..584])), (gnd_wire # (sel[561..561] # DenominatorIn[583..583])), (gnd_wire # (sel[560..560] # DenominatorIn[582..582])), (gnd_wire # (sel[559..559] # DenominatorIn[581..581])), (gnd_wire # (sel[558..558] # DenominatorIn[580..580])), (gnd_wire # (sel[557..557] # DenominatorIn[579..579])), (gnd_wire # (sel[556..556] # DenominatorIn[578..578])), (gnd_wire # (sel[555..555] # DenominatorIn[577..577])), (gnd_wire # (sel[554..554] # DenominatorIn[576..576])), (gnd_wire # (sel[553..553] # DenominatorIn[575..575])), (gnd_wire # (sel[552..552] # DenominatorIn[574..574])), (gnd_wire # (sel[551..551] # DenominatorIn[573..573])), gnd_wire, (gnd_wire # (sel[549..549] # DenominatorIn[570..570])), (gnd_wire # (sel[548..548] # DenominatorIn[569..569])), (gnd_wire # (sel[547..547] # DenominatorIn[568..568])), (gnd_wire # (sel[546..546] # DenominatorIn[567..567])), (gnd_wire # (sel[545..545] # DenominatorIn[566..566])), (gnd_wire # (sel[544..544] # DenominatorIn[565..565])), (gnd_wire # (sel[543..543] # DenominatorIn[564..564])), (gnd_wire # (sel[542..542] # DenominatorIn[563..563])), (gnd_wire # (sel[541..541] # DenominatorIn[562..562])), (gnd_wire # (sel[540..540] # DenominatorIn[561..561])), (gnd_wire # (sel[539..539] # DenominatorIn[560..560])), (gnd_wire # (sel[538..538] # DenominatorIn[559..559])), (gnd_wire # (sel[537..537] # DenominatorIn[558..558])), (gnd_wire # (sel[536..536] # DenominatorIn[557..557])), (gnd_wire # (sel[535..535] # DenominatorIn[556..556])), (gnd_wire # (sel[534..534] # DenominatorIn[555..555])), (gnd_wire # (sel[533..533] # DenominatorIn[554..554])), (gnd_wire # (sel[532..532] # DenominatorIn[553..553])), (gnd_wire # (sel[531..531] # DenominatorIn[552..552])), (gnd_wire # (sel[530..530] # DenominatorIn[551..551])), (gnd_wire # (sel[529..529] # DenominatorIn[550..550])), (gnd_wire # (sel[528..528] # DenominatorIn[549..549])), (gnd_wire # (sel[527..527] # DenominatorIn[548..548])), (gnd_wire # (sel[526..526] # DenominatorIn[547..547])), gnd_wire, (gnd_wire # (sel[524..524] # DenominatorIn[544..544])), (gnd_wire # (sel[523..523] # DenominatorIn[543..543])), (gnd_wire # (sel[522..522] # DenominatorIn[542..542])), (gnd_wire # (sel[521..521] # DenominatorIn[541..541])), (gnd_wire # (sel[520..520] # DenominatorIn[540..540])), (gnd_wire # (sel[519..519] # DenominatorIn[539..539])), (gnd_wire # (sel[518..518] # DenominatorIn[538..538])), (gnd_wire # (sel[517..517] # DenominatorIn[537..537])), (gnd_wire # (sel[516..516] # DenominatorIn[536..536])), (gnd_wire # (sel[515..515] # DenominatorIn[535..535])), (gnd_wire # (sel[514..514] # DenominatorIn[534..534])), (gnd_wire # (sel[513..513] # DenominatorIn[533..533])), (gnd_wire # (sel[512..512] # DenominatorIn[532..532])), (gnd_wire # (sel[511..511] # DenominatorIn[531..531])), (gnd_wire # (sel[510..510] # DenominatorIn[530..530])), (gnd_wire # (sel[509..509] # DenominatorIn[529..529])), (gnd_wire # (sel[508..508] # DenominatorIn[528..528])), (gnd_wire # (sel[507..507] # DenominatorIn[527..527])), (gnd_wire # (sel[506..506] # DenominatorIn[526..526])), (gnd_wire # (sel[505..505] # DenominatorIn[525..525])), (gnd_wire # (sel[504..504] # DenominatorIn[524..524])), (gnd_wire # (sel[503..503] # DenominatorIn[523..523])), (gnd_wire # (sel[502..502] # DenominatorIn[522..522])), (gnd_wire # (sel[501..501] # DenominatorIn[521..521])), gnd_wire, (gnd_wire # (sel[499..499] # DenominatorIn[518..518])), (gnd_wire # (sel[498..498] # DenominatorIn[517..517])), (gnd_wire # (sel[497..497] # DenominatorIn[516..516])), (gnd_wire # (sel[496..496] # DenominatorIn[515..515])), (gnd_wire # (sel[495..495] # DenominatorIn[514..514])), (gnd_wire # (sel[494..494] # DenominatorIn[513..513])), (gnd_wire # (sel[493..493] # DenominatorIn[512..512])), (gnd_wire # (sel[492..492] # DenominatorIn[511..511])), (gnd_wire # (sel[491..491] # DenominatorIn[510..510])), (gnd_wire # (sel[490..490] # DenominatorIn[509..509])), (gnd_wire # (sel[489..489] # DenominatorIn[508..508])), (gnd_wire # (sel[488..488] # DenominatorIn[507..507])), (gnd_wire # (sel[487..487] # DenominatorIn[506..506])), (gnd_wire # (sel[486..486] # DenominatorIn[505..505])), (gnd_wire # (sel[485..485] # DenominatorIn[504..504])), (gnd_wire # (sel[484..484] # DenominatorIn[503..503])), (gnd_wire # (sel[483..483] # DenominatorIn[502..502])), (gnd_wire # (sel[482..482] # DenominatorIn[501..501])), (gnd_wire # (sel[481..481] # DenominatorIn[500..500])), (gnd_wire # (sel[480..480] # DenominatorIn[499..499])), (gnd_wire # (sel[479..479] # DenominatorIn[498..498])), (gnd_wire # (sel[478..478] # DenominatorIn[497..497])), (gnd_wire # (sel[477..477] # DenominatorIn[496..496])), (gnd_wire # (sel[476..476] # DenominatorIn[495..495])), gnd_wire, (gnd_wire # (sel[474..474] # DenominatorIn[492..492])), (gnd_wire # (sel[473..473] # DenominatorIn[491..491])), (gnd_wire # (sel[472..472] # DenominatorIn[490..490])), (gnd_wire # (sel[471..471] # DenominatorIn[489..489])), (gnd_wire # (sel[470..470] # DenominatorIn[488..488])), (gnd_wire # (sel[469..469] # DenominatorIn[487..487])), (gnd_wire # (sel[468..468] # DenominatorIn[486..486])), (gnd_wire # (sel[467..467] # DenominatorIn[485..485])), (gnd_wire # (sel[466..466] # DenominatorIn[484..484])), (gnd_wire # (sel[465..465] # DenominatorIn[483..483])), (gnd_wire # (sel[464..464] # DenominatorIn[482..482])), (gnd_wire # (sel[463..463] # DenominatorIn[481..481])), (gnd_wire # (sel[462..462] # DenominatorIn[480..480])), (gnd_wire # (sel[461..461] # DenominatorIn[479..479])), (gnd_wire # (sel[460..460] # DenominatorIn[478..478])), (gnd_wire # (sel[459..459] # DenominatorIn[477..477])), (gnd_wire # (sel[458..458] # DenominatorIn[476..476])), (gnd_wire # (sel[457..457] # DenominatorIn[475..475])), (gnd_wire # (sel[456..456] # DenominatorIn[474..474])), (gnd_wire # (sel[455..455] # DenominatorIn[473..473])), (gnd_wire # (sel[454..454] # DenominatorIn[472..472])), (gnd_wire # (sel[453..453] # DenominatorIn[471..471])), (gnd_wire # (sel[452..452] # DenominatorIn[470..470])), (gnd_wire # (sel[451..451] # DenominatorIn[469..469])), gnd_wire, (gnd_wire # (sel[449..449] # DenominatorIn[466..466])), (gnd_wire # (sel[448..448] # DenominatorIn[465..465])), (gnd_wire # (sel[447..447] # DenominatorIn[464..464])), (gnd_wire # (sel[446..446] # DenominatorIn[463..463])), (gnd_wire # (sel[445..445] # DenominatorIn[462..462])), (gnd_wire # (sel[444..444] # DenominatorIn[461..461])), (gnd_wire # (sel[443..443] # DenominatorIn[460..460])), (gnd_wire # (sel[442..442] # DenominatorIn[459..459])), (gnd_wire # (sel[441..441] # DenominatorIn[458..458])), (gnd_wire # (sel[440..440] # DenominatorIn[457..457])), (gnd_wire # (sel[439..439] # DenominatorIn[456..456])), (gnd_wire # (sel[438..438] # DenominatorIn[455..455])), (gnd_wire # (sel[437..437] # DenominatorIn[454..454])), (gnd_wire # (sel[436..436] # DenominatorIn[453..453])), (gnd_wire # (sel[435..435] # DenominatorIn[452..452])), (gnd_wire # (sel[434..434] # DenominatorIn[451..451])), (gnd_wire # (sel[433..433] # DenominatorIn[450..450])), (gnd_wire # (sel[432..432] # DenominatorIn[449..449])), (gnd_wire # (sel[431..431] # DenominatorIn[448..448])), (gnd_wire # (sel[430..430] # DenominatorIn[447..447])), (gnd_wire # (sel[429..429] # DenominatorIn[446..446])), (gnd_wire # (sel[428..428] # DenominatorIn[445..445])), (gnd_wire # (sel[427..427] # DenominatorIn[444..444])), (gnd_wire # (sel[426..426] # DenominatorIn[443..443])), gnd_wire, (gnd_wire # (sel[424..424] # DenominatorIn[440..440])), (gnd_wire # (sel[423..423] # DenominatorIn[439..439])), (gnd_wire # (sel[422..422] # DenominatorIn[438..438])), (gnd_wire # (sel[421..421] # DenominatorIn[437..437])), (gnd_wire # (sel[420..420] # DenominatorIn[436..436])), (gnd_wire # (sel[419..419] # DenominatorIn[435..435])), (gnd_wire # (sel[418..418] # DenominatorIn[434..434])), (gnd_wire # (sel[417..417] # DenominatorIn[433..433])), (gnd_wire # (sel[416..416] # DenominatorIn[432..432])), (gnd_wire # (sel[415..415] # DenominatorIn[431..431])), (gnd_wire # (sel[414..414] # DenominatorIn[430..430])), (gnd_wire # (sel[413..413] # DenominatorIn[429..429])), (gnd_wire # (sel[412..412] # DenominatorIn[428..428])), (gnd_wire # (sel[411..411] # DenominatorIn[427..427])), (gnd_wire # (sel[410..410] # DenominatorIn[426..426])), (gnd_wire # (sel[409..409] # DenominatorIn[425..425])), (gnd_wire # (sel[408..408] # DenominatorIn[424..424])), (gnd_wire # (sel[407..407] # DenominatorIn[423..423])), (gnd_wire # (sel[406..406] # DenominatorIn[422..422])), (gnd_wire # (sel[405..405] # DenominatorIn[421..421])), (gnd_wire # (sel[404..404] # DenominatorIn[420..420])), (gnd_wire # (sel[403..403] # DenominatorIn[419..419])), (gnd_wire # (sel[402..402] # DenominatorIn[418..418])), (gnd_wire # (sel[401..401] # DenominatorIn[417..417])), gnd_wire, (gnd_wire # (sel[399..399] # DenominatorIn[414..414])), (gnd_wire # (sel[398..398] # DenominatorIn[413..413])), (gnd_wire # (sel[397..397] # DenominatorIn[412..412])), (gnd_wire # (sel[396..396] # DenominatorIn[411..411])), (gnd_wire # (sel[395..395] # DenominatorIn[410..410])), (gnd_wire # (sel[394..394] # DenominatorIn[409..409])), (gnd_wire # (sel[393..393] # DenominatorIn[408..408])), (gnd_wire # (sel[392..392] # DenominatorIn[407..407])), (gnd_wire # (sel[391..391] # DenominatorIn[406..406])), (gnd_wire # (sel[390..390] # DenominatorIn[405..405])), (gnd_wire # (sel[389..389] # DenominatorIn[404..404])), (gnd_wire # (sel[388..388] # DenominatorIn[403..403])), (gnd_wire # (sel[387..387] # DenominatorIn[402..402])), (gnd_wire # (sel[386..386] # DenominatorIn[401..401])), (gnd_wire # (sel[385..385] # DenominatorIn[400..400])), (gnd_wire # (sel[384..384] # DenominatorIn[399..399])), (gnd_wire # (sel[383..383] # DenominatorIn[398..398])), (gnd_wire # (sel[382..382] # DenominatorIn[397..397])), (gnd_wire # (sel[381..381] # DenominatorIn[396..396])), (gnd_wire # (sel[380..380] # DenominatorIn[395..395])), (gnd_wire # (sel[379..379] # DenominatorIn[394..394])), (gnd_wire # (sel[378..378] # DenominatorIn[393..393])), (gnd_wire # (sel[377..377] # DenominatorIn[392..392])), (gnd_wire # (sel[376..376] # DenominatorIn[391..391])), gnd_wire, (gnd_wire # (sel[374..374] # DenominatorIn[388..388])), (gnd_wire # (sel[373..373] # DenominatorIn[387..387])), (gnd_wire # (sel[372..372] # DenominatorIn[386..386])), (gnd_wire # (sel[371..371] # DenominatorIn[385..385])), (gnd_wire # (sel[370..370] # DenominatorIn[384..384])), (gnd_wire # (sel[369..369] # DenominatorIn[383..383])), (gnd_wire # (sel[368..368] # DenominatorIn[382..382])), (gnd_wire # (sel[367..367] # DenominatorIn[381..381])), (gnd_wire # (sel[366..366] # DenominatorIn[380..380])), (gnd_wire # (sel[365..365] # DenominatorIn[379..379])), (gnd_wire # (sel[364..364] # DenominatorIn[378..378])), (gnd_wire # (sel[363..363] # DenominatorIn[377..377])), (gnd_wire # (sel[362..362] # DenominatorIn[376..376])), (gnd_wire # (sel[361..361] # DenominatorIn[375..375])), (gnd_wire # (sel[360..360] # DenominatorIn[374..374])), (gnd_wire # (sel[359..359] # DenominatorIn[373..373])), (gnd_wire # (sel[358..358] # DenominatorIn[372..372])), (gnd_wire # (sel[357..357] # DenominatorIn[371..371])), (gnd_wire # (sel[356..356] # DenominatorIn[370..370])), (gnd_wire # (sel[355..355] # DenominatorIn[369..369])), (gnd_wire # (sel[354..354] # DenominatorIn[368..368])), (gnd_wire # (sel[353..353] # DenominatorIn[367..367])), (gnd_wire # (sel[352..352] # DenominatorIn[366..366])), (gnd_wire # (sel[351..351] # DenominatorIn[365..365])), gnd_wire, (gnd_wire # (sel[349..349] # DenominatorIn[362..362])), (gnd_wire # (sel[348..348] # DenominatorIn[361..361])), (gnd_wire # (sel[347..347] # DenominatorIn[360..360])), (gnd_wire # (sel[346..346] # DenominatorIn[359..359])), (gnd_wire # (sel[345..345] # DenominatorIn[358..358])), (gnd_wire # (sel[344..344] # DenominatorIn[357..357])), (gnd_wire # (sel[343..343] # DenominatorIn[356..356])), (gnd_wire # (sel[342..342] # DenominatorIn[355..355])), (gnd_wire # (sel[341..341] # DenominatorIn[354..354])), (gnd_wire # (sel[340..340] # DenominatorIn[353..353])), (gnd_wire # (sel[339..339] # DenominatorIn[352..352])), (gnd_wire # (sel[338..338] # DenominatorIn[351..351])), (gnd_wire # (sel[337..337] # DenominatorIn[350..350])), (gnd_wire # (sel[336..336] # DenominatorIn[349..349])), (gnd_wire # (sel[335..335] # DenominatorIn[348..348])), (gnd_wire # (sel[334..334] # DenominatorIn[347..347])), (gnd_wire # (sel[333..333] # DenominatorIn[346..346])), (gnd_wire # (sel[332..332] # DenominatorIn[345..345])), (gnd_wire # (sel[331..331] # DenominatorIn[344..344])), (gnd_wire # (sel[330..330] # DenominatorIn[343..343])), (gnd_wire # (sel[329..329] # DenominatorIn[342..342])), (gnd_wire # (sel[328..328] # DenominatorIn[341..341])), (gnd_wire # (sel[327..327] # DenominatorIn[340..340])), (gnd_wire # (sel[326..326] # DenominatorIn[339..339])), gnd_wire, (gnd_wire # (sel[324..324] # DenominatorIn[336..336])), (gnd_wire # (sel[323..323] # DenominatorIn[335..335])), (gnd_wire # (sel[322..322] # DenominatorIn[334..334])), (gnd_wire # (sel[321..321] # DenominatorIn[333..333])), (gnd_wire # (sel[320..320] # DenominatorIn[332..332])), (gnd_wire # (sel[319..319] # DenominatorIn[331..331])), (gnd_wire # (sel[318..318] # DenominatorIn[330..330])), (gnd_wire # (sel[317..317] # DenominatorIn[329..329])), (gnd_wire # (sel[316..316] # DenominatorIn[328..328])), (gnd_wire # (sel[315..315] # DenominatorIn[327..327])), (gnd_wire # (sel[314..314] # DenominatorIn[326..326])), (gnd_wire # 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DenominatorIn[28..28])), (gnd_wire # (sel[26..26] # DenominatorIn[27..27])), gnd_wire, (gnd_wire # (sel[24..24] # DenominatorIn[24..24])), (gnd_wire # (sel[23..23] # DenominatorIn[23..23])), (gnd_wire # (sel[22..22] # DenominatorIn[22..22])), (gnd_wire # (sel[21..21] # DenominatorIn[21..21])), (gnd_wire # (sel[20..20] # DenominatorIn[20..20])), (gnd_wire # (sel[19..19] # DenominatorIn[19..19])), (gnd_wire # (sel[18..18] # DenominatorIn[18..18])), (gnd_wire # (sel[17..17] # DenominatorIn[17..17])), (gnd_wire # (sel[16..16] # DenominatorIn[16..16])), (gnd_wire # (sel[15..15] # DenominatorIn[15..15])), (gnd_wire # (sel[14..14] # DenominatorIn[14..14])), (gnd_wire # (sel[13..13] # DenominatorIn[13..13])), (gnd_wire # (sel[12..12] # DenominatorIn[12..12])), (gnd_wire # (sel[11..11] # DenominatorIn[11..11])), (gnd_wire # (sel[10..10] # DenominatorIn[10..10])), (gnd_wire # (sel[9..9] # DenominatorIn[9..9])), (gnd_wire # (sel[8..8] # DenominatorIn[8..8])), (gnd_wire # (sel[7..7] # DenominatorIn[7..7])), (gnd_wire # (sel[6..6] # DenominatorIn[6..6])), (gnd_wire # (sel[5..5] # DenominatorIn[5..5])), (gnd_wire # (sel[4..4] # DenominatorIn[4..4])), (gnd_wire # (sel[3..3] # DenominatorIn[3..3])), (gnd_wire # (sel[2..2] # DenominatorIn[2..2])), (gnd_wire # (sel[1..1] # DenominatorIn[1..1])));
+ selnose[] = ( ((gnd_wire # (! nose[649..649])) # sel[649..649]), ((gnd_wire # (! nose[648..648])) # sel[648..648]), ((gnd_wire # (! nose[647..647])) # sel[647..647]), ((gnd_wire # (! nose[646..646])) # sel[646..646]), ((gnd_wire # (! nose[645..645])) # sel[645..645]), ((gnd_wire # (! nose[644..644])) # sel[644..644]), ((gnd_wire # (! nose[643..643])) # sel[643..643]), ((gnd_wire # (! nose[642..642])) # sel[642..642]), ((gnd_wire # (! nose[641..641])) # sel[641..641]), ((gnd_wire # (! nose[640..640])) # sel[640..640]), ((gnd_wire # (! nose[639..639])) # sel[639..639]), ((gnd_wire # (! nose[638..638])) # sel[638..638]), ((gnd_wire # (! nose[637..637])) # sel[637..637]), ((gnd_wire # (! nose[636..636])) # sel[636..636]), ((gnd_wire # (! nose[635..635])) # sel[635..635]), ((gnd_wire # (! nose[634..634])) # sel[634..634]), ((gnd_wire # (! nose[633..633])) # sel[633..633]), ((gnd_wire # (! nose[632..632])) # sel[632..632]), ((gnd_wire # (! nose[631..631])) # sel[631..631]), ((gnd_wire # (! nose[630..630])) # sel[630..630]), ((gnd_wire # (! nose[629..629])) # sel[629..629]), ((gnd_wire # (! nose[628..628])) # sel[628..628]), ((gnd_wire # (! nose[627..627])) # sel[627..627]), ((gnd_wire # (! nose[626..626])) # sel[626..626]), ((gnd_wire # (! nose[625..625])) # sel[625..625]), ((gnd_wire # (! nose[624..624])) # sel[624..624]), ((gnd_wire # (! nose[623..623])) # sel[623..623]), ((gnd_wire # (! nose[622..622])) # sel[622..622]), ((gnd_wire # (! nose[621..621])) # sel[621..621]), ((gnd_wire # (! nose[620..620])) # sel[620..620]), ((gnd_wire # (! nose[619..619])) # sel[619..619]), ((gnd_wire # (! nose[618..618])) # sel[618..618]), ((gnd_wire # (! nose[617..617])) # sel[617..617]), ((gnd_wire # (! nose[616..616])) # sel[616..616]), ((gnd_wire # (! nose[615..615])) # sel[615..615]), ((gnd_wire # (! nose[614..614])) # sel[614..614]), ((gnd_wire # (! nose[613..613])) # sel[613..613]), ((gnd_wire # (! nose[612..612])) # sel[612..612]), ((gnd_wire # (! nose[611..611])) # sel[611..611]), ((gnd_wire # (! nose[610..610])) # sel[610..610]), ((gnd_wire # (! nose[609..609])) # sel[609..609]), ((gnd_wire # (! nose[608..608])) # sel[608..608]), ((gnd_wire # (! nose[607..607])) # sel[607..607]), ((gnd_wire # (! nose[606..606])) # sel[606..606]), ((gnd_wire # (! nose[605..605])) # sel[605..605]), ((gnd_wire # (! nose[604..604])) # sel[604..604]), ((gnd_wire # (! nose[603..603])) # sel[603..603]), ((gnd_wire # (! nose[602..602])) # sel[602..602]), ((gnd_wire # (! nose[601..601])) # sel[601..601]), ((gnd_wire # (! nose[600..600])) # sel[600..600]), ((gnd_wire # (! nose[599..599])) # sel[599..599]), ((gnd_wire # (! nose[598..598])) # sel[598..598]), ((gnd_wire # (! nose[597..597])) # sel[597..597]), ((gnd_wire # (! nose[596..596])) # sel[596..596]), ((gnd_wire # (! nose[595..595])) # sel[595..595]), ((gnd_wire # (! nose[594..594])) # sel[594..594]), ((gnd_wire # (! nose[593..593])) # sel[593..593]), ((gnd_wire # (! nose[592..592])) # sel[592..592]), ((gnd_wire # (! nose[591..591])) # sel[591..591]), ((gnd_wire # (! nose[590..590])) # sel[590..590]), ((gnd_wire # (! nose[589..589])) # sel[589..589]), ((gnd_wire # (! nose[588..588])) # sel[588..588]), ((gnd_wire # (! nose[587..587])) # sel[587..587]), ((gnd_wire # (! nose[586..586])) # sel[586..586]), ((gnd_wire # (! nose[585..585])) # sel[585..585]), ((gnd_wire # (! nose[584..584])) # sel[584..584]), ((gnd_wire # (! nose[583..583])) # sel[583..583]), ((gnd_wire # (! nose[582..582])) # sel[582..582]), ((gnd_wire # (! nose[581..581])) # sel[581..581]), ((gnd_wire # (! nose[580..580])) # sel[580..580]), ((gnd_wire # (! nose[579..579])) # sel[579..579]), ((gnd_wire # (! nose[578..578])) # sel[578..578]), ((gnd_wire # (! nose[577..577])) # sel[577..577]), ((gnd_wire # (! nose[576..576])) # sel[576..576]), ((gnd_wire # (! nose[575..575])) # sel[575..575]), ((gnd_wire # (! nose[574..574])) # sel[574..574]), ((gnd_wire # (! nose[573..573])) # sel[573..573]), ((gnd_wire # (! nose[572..572])) # sel[572..572]), ((gnd_wire # (! nose[571..571])) # sel[571..571]), ((gnd_wire # (! nose[570..570])) # sel[570..570]), ((gnd_wire # (! nose[569..569])) # sel[569..569]), ((gnd_wire # (! nose[568..568])) # sel[568..568]), ((gnd_wire # (! nose[567..567])) # sel[567..567]), ((gnd_wire # (! nose[566..566])) # sel[566..566]), ((gnd_wire # (! nose[565..565])) # sel[565..565]), ((gnd_wire # (! nose[564..564])) # sel[564..564]), ((gnd_wire # (! nose[563..563])) # sel[563..563]), ((gnd_wire # (! nose[562..562])) # sel[562..562]), ((gnd_wire # (! nose[561..561])) # sel[561..561]), ((gnd_wire # (! nose[560..560])) # sel[560..560]), ((gnd_wire # (! nose[559..559])) # sel[559..559]), ((gnd_wire # (! nose[558..558])) # sel[558..558]), ((gnd_wire # (! nose[557..557])) # sel[557..557]), ((gnd_wire # (! nose[556..556])) # sel[556..556]), ((gnd_wire # (! nose[555..555])) # sel[555..555]), ((gnd_wire # (! nose[554..554])) # sel[554..554]), ((gnd_wire # (! nose[553..553])) # sel[553..553]), ((gnd_wire # (! nose[552..552])) # sel[552..552]), ((gnd_wire # (! nose[551..551])) # sel[551..551]), ((gnd_wire # (! nose[550..550])) # sel[550..550]), ((gnd_wire # (! nose[549..549])) # sel[549..549]), ((gnd_wire # (! nose[548..548])) # sel[548..548]), ((gnd_wire # (! nose[547..547])) # sel[547..547]), ((gnd_wire # (! nose[546..546])) # sel[546..546]), ((gnd_wire # (! nose[545..545])) # sel[545..545]), ((gnd_wire # (! nose[544..544])) # sel[544..544]), ((gnd_wire # (! nose[543..543])) # sel[543..543]), ((gnd_wire # (! nose[542..542])) # sel[542..542]), ((gnd_wire # (! nose[541..541])) # sel[541..541]), ((gnd_wire # (! nose[540..540])) # sel[540..540]), ((gnd_wire # (! nose[539..539])) # sel[539..539]), ((gnd_wire # (! nose[538..538])) # sel[538..538]), ((gnd_wire # (! nose[537..537])) # sel[537..537]), ((gnd_wire # (! nose[536..536])) # sel[536..536]), ((gnd_wire # (! nose[535..535])) # sel[535..535]), ((gnd_wire # (! nose[534..534])) # sel[534..534]), ((gnd_wire # (! nose[533..533])) # sel[533..533]), ((gnd_wire # (! nose[532..532])) # sel[532..532]), ((gnd_wire # (! nose[531..531])) # sel[531..531]), ((gnd_wire # (! nose[530..530])) # sel[530..530]), ((gnd_wire # (! nose[529..529])) # sel[529..529]), ((gnd_wire # (! nose[528..528])) # sel[528..528]), ((gnd_wire # (! nose[527..527])) # sel[527..527]), ((gnd_wire # (! nose[526..526])) # sel[526..526]), ((gnd_wire # (! nose[525..525])) # sel[525..525]), ((gnd_wire # (! nose[524..524])) # sel[524..524]), ((gnd_wire # (! nose[523..523])) # sel[523..523]), ((gnd_wire # (! nose[522..522])) # sel[522..522]), ((gnd_wire # (! nose[521..521])) # sel[521..521]), ((gnd_wire # (! nose[520..520])) # sel[520..520]), ((gnd_wire # (! nose[519..519])) # sel[519..519]), ((gnd_wire # (! nose[518..518])) # sel[518..518]), ((gnd_wire # (! nose[517..517])) # sel[517..517]), ((gnd_wire # (! nose[516..516])) # sel[516..516]), ((gnd_wire # (! nose[515..515])) # sel[515..515]), ((gnd_wire # (! nose[514..514])) # sel[514..514]), ((gnd_wire # (! nose[513..513])) # sel[513..513]), ((gnd_wire # (! nose[512..512])) # sel[512..512]), ((gnd_wire # (! nose[511..511])) # sel[511..511]), ((gnd_wire # (! nose[510..510])) # sel[510..510]), ((gnd_wire # (! nose[509..509])) # sel[509..509]), ((gnd_wire # (! nose[508..508])) # sel[508..508]), ((gnd_wire # (! nose[507..507])) # sel[507..507]), ((gnd_wire # (! nose[506..506])) # sel[506..506]), ((gnd_wire # (! nose[505..505])) # sel[505..505]), ((gnd_wire # (! nose[504..504])) # sel[504..504]), ((gnd_wire # (! nose[503..503])) # sel[503..503]), ((gnd_wire # (! nose[502..502])) # sel[502..502]), ((gnd_wire # (! nose[501..501])) # sel[501..501]), ((gnd_wire # (! nose[500..500])) # sel[500..500]), ((gnd_wire # (! nose[499..499])) # sel[499..499]), ((gnd_wire # (! nose[498..498])) # sel[498..498]), ((gnd_wire # (! nose[497..497])) # sel[497..497]), ((gnd_wire # (! nose[496..496])) # sel[496..496]), ((gnd_wire # (! nose[495..495])) # sel[495..495]), ((gnd_wire # (! nose[494..494])) # sel[494..494]), ((gnd_wire # (! nose[493..493])) # sel[493..493]), ((gnd_wire # (! nose[492..492])) # sel[492..492]), ((gnd_wire # (! nose[491..491])) # sel[491..491]), ((gnd_wire # (! nose[490..490])) # sel[490..490]), ((gnd_wire # (! nose[489..489])) # sel[489..489]), ((gnd_wire # (! nose[488..488])) # sel[488..488]), ((gnd_wire # (! nose[487..487])) # sel[487..487]), ((gnd_wire # (! nose[486..486])) # sel[486..486]), ((gnd_wire # (! nose[485..485])) # sel[485..485]), ((gnd_wire # (! nose[484..484])) # sel[484..484]), ((gnd_wire # (! nose[483..483])) # sel[483..483]), ((gnd_wire # (! nose[482..482])) # sel[482..482]), ((gnd_wire # (! nose[481..481])) # sel[481..481]), ((gnd_wire # (! nose[480..480])) # sel[480..480]), ((gnd_wire # (! nose[479..479])) # sel[479..479]), ((gnd_wire # (! nose[478..478])) # sel[478..478]), ((gnd_wire # (! nose[477..477])) # sel[477..477]), ((gnd_wire # (! nose[476..476])) # sel[476..476]), ((gnd_wire # (! nose[475..475])) # sel[475..475]), ((gnd_wire # (! nose[474..474])) # sel[474..474]), ((gnd_wire # (! nose[473..473])) # sel[473..473]), ((gnd_wire # (! nose[472..472])) # sel[472..472]), ((gnd_wire # (! nose[471..471])) # sel[471..471]), ((gnd_wire # (! nose[470..470])) # sel[470..470]), ((gnd_wire # (! nose[469..469])) # sel[469..469]), ((gnd_wire # (! nose[468..468])) # sel[468..468]), ((gnd_wire # (! nose[467..467])) # sel[467..467]), ((gnd_wire # (! nose[466..466])) # sel[466..466]), ((gnd_wire # (! nose[465..465])) # sel[465..465]), ((gnd_wire # (! nose[464..464])) # sel[464..464]), ((gnd_wire # (! nose[463..463])) # sel[463..463]), ((gnd_wire # (! nose[462..462])) # sel[462..462]), ((gnd_wire # (! nose[461..461])) # sel[461..461]), ((gnd_wire # (! nose[460..460])) # sel[460..460]), ((gnd_wire # (! nose[459..459])) # sel[459..459]), ((gnd_wire # (! nose[458..458])) # sel[458..458]), ((gnd_wire # (! nose[457..457])) # sel[457..457]), ((gnd_wire # (! nose[456..456])) # sel[456..456]), ((gnd_wire # (! nose[455..455])) # sel[455..455]), ((gnd_wire # (! nose[454..454])) # sel[454..454]), ((gnd_wire # (! nose[453..453])) # sel[453..453]), ((gnd_wire # (! nose[452..452])) # sel[452..452]), ((gnd_wire # (! nose[451..451])) # sel[451..451]), ((gnd_wire # (! nose[450..450])) # sel[450..450]), ((gnd_wire # (! nose[449..449])) # sel[449..449]), ((gnd_wire # (! nose[448..448])) # sel[448..448]), ((gnd_wire # (! nose[447..447])) # sel[447..447]), ((gnd_wire # (! nose[446..446])) # sel[446..446]), ((gnd_wire # (! nose[445..445])) # sel[445..445]), ((gnd_wire # (! nose[444..444])) # sel[444..444]), ((gnd_wire # (! nose[443..443])) # sel[443..443]), ((gnd_wire # (! nose[442..442])) # sel[442..442]), ((gnd_wire # (! nose[441..441])) # sel[441..441]), ((gnd_wire # (! nose[440..440])) # sel[440..440]), ((gnd_wire # (! nose[439..439])) # sel[439..439]), ((gnd_wire # (! nose[438..438])) # sel[438..438]), ((gnd_wire # (! nose[437..437])) # sel[437..437]), ((gnd_wire # (! nose[436..436])) # sel[436..436]), ((gnd_wire # (! nose[435..435])) # sel[435..435]), ((gnd_wire # (! nose[434..434])) # sel[434..434]), ((gnd_wire # (! nose[433..433])) # sel[433..433]), ((gnd_wire # (! nose[432..432])) # sel[432..432]), ((gnd_wire # (! nose[431..431])) # sel[431..431]), ((gnd_wire # (! nose[430..430])) # sel[430..430]), ((gnd_wire # (! nose[429..429])) # sel[429..429]), ((gnd_wire # (! nose[428..428])) # sel[428..428]), ((gnd_wire # (! nose[427..427])) # sel[427..427]), ((gnd_wire # (! nose[426..426])) # sel[426..426]), ((gnd_wire # (! nose[425..425])) # sel[425..425]), ((gnd_wire # (! nose[424..424])) # sel[424..424]), ((gnd_wire # (! nose[423..423])) # sel[423..423]), ((gnd_wire # (! nose[422..422])) # sel[422..422]), ((gnd_wire # (! nose[421..421])) # sel[421..421]), ((gnd_wire # (! nose[420..420])) # sel[420..420]), ((gnd_wire # (! nose[419..419])) # sel[419..419]), ((gnd_wire # (! nose[418..418])) # sel[418..418]), ((gnd_wire # (! nose[417..417])) # sel[417..417]), ((gnd_wire # (! nose[416..416])) # sel[416..416]), ((gnd_wire # (! nose[415..415])) # sel[415..415]), ((gnd_wire # (! nose[414..414])) # sel[414..414]), ((gnd_wire # (! nose[413..413])) # sel[413..413]), ((gnd_wire # (! nose[412..412])) # sel[412..412]), ((gnd_wire # (! nose[411..411])) # sel[411..411]), ((gnd_wire # (! nose[410..410])) # sel[410..410]), ((gnd_wire # (! nose[409..409])) # sel[409..409]), ((gnd_wire # (! nose[408..408])) # sel[408..408]), ((gnd_wire # (! nose[407..407])) # sel[407..407]), ((gnd_wire # (! nose[406..406])) # sel[406..406]), ((gnd_wire # (! nose[405..405])) # sel[405..405]), ((gnd_wire # (! nose[404..404])) # sel[404..404]), ((gnd_wire # (! nose[403..403])) # sel[403..403]), ((gnd_wire # (! nose[402..402])) # sel[402..402]), ((gnd_wire # (! nose[401..401])) # sel[401..401]), ((gnd_wire # (! nose[400..400])) # sel[400..400]), ((gnd_wire # (! nose[399..399])) # sel[399..399]), ((gnd_wire # (! nose[398..398])) # sel[398..398]), ((gnd_wire # (! nose[397..397])) # sel[397..397]), ((gnd_wire # (! nose[396..396])) # sel[396..396]), ((gnd_wire # (! nose[395..395])) # sel[395..395]), ((gnd_wire # (! nose[394..394])) # sel[394..394]), ((gnd_wire # (! nose[393..393])) # sel[393..393]), ((gnd_wire # (! nose[392..392])) # sel[392..392]), ((gnd_wire # (! nose[391..391])) # sel[391..391]), ((gnd_wire # (! nose[390..390])) # sel[390..390]), ((gnd_wire # (! nose[389..389])) # sel[389..389]), ((gnd_wire # (! nose[388..388])) # sel[388..388]), ((gnd_wire # (! nose[387..387])) # sel[387..387]), ((gnd_wire # (! nose[386..386])) # sel[386..386]), ((gnd_wire # (! nose[385..385])) # sel[385..385]), ((gnd_wire # (! nose[384..384])) # sel[384..384]), ((gnd_wire # (! nose[383..383])) # sel[383..383]), ((gnd_wire # (! nose[382..382])) # sel[382..382]), ((gnd_wire # (! nose[381..381])) # sel[381..381]), ((gnd_wire # (! nose[380..380])) # sel[380..380]), ((gnd_wire # (! nose[379..379])) # sel[379..379]), ((gnd_wire # (! nose[378..378])) # sel[378..378]), ((gnd_wire # (! nose[377..377])) # sel[377..377]), ((gnd_wire # (! nose[376..376])) # sel[376..376]), ((gnd_wire # (! nose[375..375])) # sel[375..375]), ((gnd_wire # (! nose[374..374])) # sel[374..374]), ((gnd_wire # (! nose[373..373])) # sel[373..373]), ((gnd_wire # (! nose[372..372])) # sel[372..372]), ((gnd_wire # (! nose[371..371])) # sel[371..371]), ((gnd_wire # (! nose[370..370])) # sel[370..370]), ((gnd_wire # (! nose[369..369])) # sel[369..369]), ((gnd_wire # (! nose[368..368])) # sel[368..368]), ((gnd_wire # (! nose[367..367])) # sel[367..367]), ((gnd_wire # (! nose[366..366])) # sel[366..366]), ((gnd_wire # (! nose[365..365])) # sel[365..365]), ((gnd_wire # (! nose[364..364])) # sel[364..364]), ((gnd_wire # (! nose[363..363])) # sel[363..363]), ((gnd_wire # (! nose[362..362])) # sel[362..362]), ((gnd_wire # (! nose[361..361])) # sel[361..361]), ((gnd_wire # (! nose[360..360])) # sel[360..360]), ((gnd_wire # (! nose[359..359])) # sel[359..359]), ((gnd_wire # (! nose[358..358])) # sel[358..358]), ((gnd_wire # (! nose[357..357])) # sel[357..357]), ((gnd_wire # (! nose[356..356])) # sel[356..356]), ((gnd_wire # (! nose[355..355])) # sel[355..355]), ((gnd_wire # (! nose[354..354])) # sel[354..354]), ((gnd_wire # (! nose[353..353])) # sel[353..353]), ((gnd_wire # (! nose[352..352])) # sel[352..352]), ((gnd_wire # (! nose[351..351])) # sel[351..351]), ((gnd_wire # (! nose[350..350])) # sel[350..350]), ((gnd_wire # (! nose[349..349])) # sel[349..349]), ((gnd_wire # (! nose[348..348])) # sel[348..348]), ((gnd_wire # (! nose[347..347])) # sel[347..347]), ((gnd_wire # (! nose[346..346])) # sel[346..346]), ((gnd_wire # (! nose[345..345])) # sel[345..345]), ((gnd_wire # (! nose[344..344])) # sel[344..344]), ((gnd_wire # (! nose[343..343])) # sel[343..343]), ((gnd_wire # (! nose[342..342])) # sel[342..342]), ((gnd_wire # (! nose[341..341])) # sel[341..341]), ((gnd_wire # (! nose[340..340])) # sel[340..340]), ((gnd_wire # (! nose[339..339])) # sel[339..339]), ((gnd_wire # (! nose[338..338])) # sel[338..338]), ((gnd_wire # (! nose[337..337])) # sel[337..337]), ((gnd_wire # (! nose[336..336])) # sel[336..336]), ((gnd_wire # (! nose[335..335])) # sel[335..335]), ((gnd_wire # (! nose[334..334])) # sel[334..334]), ((gnd_wire # (! nose[333..333])) # sel[333..333]), ((gnd_wire # (! nose[332..332])) # sel[332..332]), ((gnd_wire # (! nose[331..331])) # sel[331..331]), ((gnd_wire # (! nose[330..330])) # sel[330..330]), ((gnd_wire # (! nose[329..329])) # sel[329..329]), ((gnd_wire # (! nose[328..328])) # sel[328..328]), ((gnd_wire # (! nose[327..327])) # sel[327..327]), ((gnd_wire # (! nose[326..326])) # sel[326..326]), ((gnd_wire # (! nose[325..325])) # sel[325..325]), ((gnd_wire # (! nose[324..324])) # sel[324..324]), ((gnd_wire # (! nose[323..323])) # sel[323..323]), ((gnd_wire # (! nose[322..322])) # sel[322..322]), ((gnd_wire # (! nose[321..321])) # sel[321..321]), ((gnd_wire # (! nose[320..320])) # sel[320..320]), ((gnd_wire # (! nose[319..319])) # sel[319..319]), ((gnd_wire # (! nose[318..318])) # sel[318..318]), ((gnd_wire # (! nose[317..317])) # sel[317..317]), ((gnd_wire # (! nose[316..316])) # sel[316..316]), ((gnd_wire # (! nose[315..315])) # sel[315..315]), ((gnd_wire # (! nose[314..314])) # sel[314..314]), ((gnd_wire # (! nose[313..313])) # sel[313..313]), ((gnd_wire # (! nose[312..312])) # sel[312..312]), ((gnd_wire # (! nose[311..311])) # sel[311..311]), ((gnd_wire # (! nose[310..310])) # sel[310..310]), ((gnd_wire # (! nose[309..309])) # sel[309..309]), ((gnd_wire # (! nose[308..308])) # sel[308..308]), ((gnd_wire # (! nose[307..307])) # sel[307..307]), ((gnd_wire # (! nose[306..306])) # sel[306..306]), ((gnd_wire # (! nose[305..305])) # sel[305..305]), ((gnd_wire # (! nose[304..304])) # sel[304..304]), ((gnd_wire # (! nose[303..303])) # sel[303..303]), ((gnd_wire # (! nose[302..302])) # sel[302..302]), ((gnd_wire # (! nose[301..301])) # sel[301..301]), ((gnd_wire # (! nose[300..300])) # sel[300..300]), ((gnd_wire # (! nose[299..299])) # sel[299..299]), ((gnd_wire # (! nose[298..298])) # sel[298..298]), ((gnd_wire # (! nose[297..297])) # sel[297..297]), ((gnd_wire # (! nose[296..296])) # sel[296..296]), ((gnd_wire # (! nose[295..295])) # sel[295..295]), ((gnd_wire # (! nose[294..294])) # sel[294..294]), ((gnd_wire # (! nose[293..293])) # sel[293..293]), ((gnd_wire # (! nose[292..292])) # sel[292..292]), ((gnd_wire # (! nose[291..291])) # sel[291..291]), ((gnd_wire # (! nose[290..290])) # sel[290..290]), ((gnd_wire # (! nose[289..289])) # sel[289..289]), ((gnd_wire # (! nose[288..288])) # sel[288..288]), ((gnd_wire # (! nose[287..287])) # sel[287..287]), ((gnd_wire # (! nose[286..286])) # sel[286..286]), ((gnd_wire # (! nose[285..285])) # sel[285..285]), ((gnd_wire # (! nose[284..284])) # sel[284..284]), ((gnd_wire # (! nose[283..283])) # sel[283..283]), ((gnd_wire # (! nose[282..282])) # sel[282..282]), ((gnd_wire # (! nose[281..281])) # sel[281..281]), ((gnd_wire # (! nose[280..280])) # sel[280..280]), ((gnd_wire # (! nose[279..279])) # sel[279..279]), ((gnd_wire # (! nose[278..278])) # sel[278..278]), ((gnd_wire # (! nose[277..277])) # sel[277..277]), ((gnd_wire # (! nose[276..276])) # sel[276..276]), ((gnd_wire # (! nose[275..275])) # sel[275..275]), ((gnd_wire # (! nose[274..274])) # sel[274..274]), ((gnd_wire # (! nose[273..273])) # sel[273..273]), ((gnd_wire # (! nose[272..272])) # sel[272..272]), ((gnd_wire # (! nose[271..271])) # sel[271..271]), ((gnd_wire # (! nose[270..270])) # sel[270..270]), ((gnd_wire # (! nose[269..269])) # sel[269..269]), ((gnd_wire # (! nose[268..268])) # sel[268..268]), ((gnd_wire # (! nose[267..267])) # sel[267..267]), ((gnd_wire # (! nose[266..266])) # sel[266..266]), ((gnd_wire # (! nose[265..265])) # sel[265..265]), ((gnd_wire # (! nose[264..264])) # sel[264..264]), ((gnd_wire # (! nose[263..263])) # sel[263..263]), ((gnd_wire # (! nose[262..262])) # sel[262..262]), ((gnd_wire # (! nose[261..261])) # sel[261..261]), ((gnd_wire # (! nose[260..260])) # sel[260..260]), ((gnd_wire # (! nose[259..259])) # sel[259..259]), ((gnd_wire # (! nose[258..258])) # sel[258..258]), ((gnd_wire # (! nose[257..257])) # sel[257..257]), ((gnd_wire # (! nose[256..256])) # sel[256..256]), ((gnd_wire # (! nose[255..255])) # sel[255..255]), ((gnd_wire # (! nose[254..254])) # sel[254..254]), ((gnd_wire # (! nose[253..253])) # sel[253..253]), ((gnd_wire # (! nose[252..252])) # sel[252..252]), ((gnd_wire # (! nose[251..251])) # sel[251..251]), ((gnd_wire # (! nose[250..250])) # sel[250..250]), ((gnd_wire # (! nose[249..249])) # sel[249..249]), ((gnd_wire # (! nose[248..248])) # sel[248..248]), ((gnd_wire # (! nose[247..247])) # sel[247..247]), ((gnd_wire # (! nose[246..246])) # sel[246..246]), ((gnd_wire # (! nose[245..245])) # sel[245..245]), ((gnd_wire # (! nose[244..244])) # sel[244..244]), ((gnd_wire # (! nose[243..243])) # sel[243..243]), ((gnd_wire # (! nose[242..242])) # sel[242..242]), ((gnd_wire # (! nose[241..241])) # sel[241..241]), ((gnd_wire # (! nose[240..240])) # sel[240..240]), ((gnd_wire # (! nose[239..239])) # sel[239..239]), ((gnd_wire # (! nose[238..238])) # sel[238..238]), ((gnd_wire # (! nose[237..237])) # sel[237..237]), ((gnd_wire # (! nose[236..236])) # sel[236..236]), ((gnd_wire # (! nose[235..235])) # sel[235..235]), ((gnd_wire # (! nose[234..234])) # sel[234..234]), ((gnd_wire # (! nose[233..233])) # sel[233..233]), ((gnd_wire # (! nose[232..232])) # sel[232..232]), ((gnd_wire # (! nose[231..231])) # sel[231..231]), ((gnd_wire # (! nose[230..230])) # sel[230..230]), ((gnd_wire # (! nose[229..229])) # sel[229..229]), ((gnd_wire # (! nose[228..228])) # sel[228..228]), ((gnd_wire # (! nose[227..227])) # sel[227..227]), ((gnd_wire # (! nose[226..226])) # sel[226..226]), ((gnd_wire # (! nose[225..225])) # sel[225..225]), ((gnd_wire # (! nose[224..224])) # sel[224..224]), ((gnd_wire # (! nose[223..223])) # sel[223..223]), ((gnd_wire # (! nose[222..222])) # sel[222..222]), ((gnd_wire # (! nose[221..221])) # sel[221..221]), ((gnd_wire # (! nose[220..220])) # sel[220..220]), ((gnd_wire # (! nose[219..219])) # sel[219..219]), ((gnd_wire # (! nose[218..218])) # sel[218..218]), ((gnd_wire # (! nose[217..217])) # sel[217..217]), ((gnd_wire # (! nose[216..216])) # sel[216..216]), ((gnd_wire # (! nose[215..215])) # sel[215..215]), ((gnd_wire # (! nose[214..214])) # sel[214..214]), ((gnd_wire # (! nose[213..213])) # sel[213..213]), ((gnd_wire # (! nose[212..212])) # sel[212..212]), ((gnd_wire # (! nose[211..211])) # sel[211..211]), ((gnd_wire # (! nose[210..210])) # sel[210..210]), ((gnd_wire # (! nose[209..209])) # sel[209..209]), ((gnd_wire # (! nose[208..208])) # sel[208..208]), ((gnd_wire # (! nose[207..207])) # sel[207..207]), ((gnd_wire # (! nose[206..206])) # sel[206..206]), ((gnd_wire # (! nose[205..205])) # sel[205..205]), ((gnd_wire # (! nose[204..204])) # sel[204..204]), ((gnd_wire # (! nose[203..203])) # sel[203..203]), ((gnd_wire # (! nose[202..202])) # sel[202..202]), ((gnd_wire # (! nose[201..201])) # sel[201..201]), ((gnd_wire # (! nose[200..200])) # sel[200..200]), ((gnd_wire # (! nose[199..199])) # sel[199..199]), ((gnd_wire # (! nose[198..198])) # sel[198..198]), ((gnd_wire # (! nose[197..197])) # sel[197..197]), ((gnd_wire # (! nose[196..196])) # sel[196..196]), ((gnd_wire # (! nose[195..195])) # sel[195..195]), ((gnd_wire # (! nose[194..194])) # sel[194..194]), ((gnd_wire # (! nose[193..193])) # sel[193..193]), ((gnd_wire # (! nose[192..192])) # sel[192..192]), ((gnd_wire # (! nose[191..191])) # sel[191..191]), ((gnd_wire # (! nose[190..190])) # sel[190..190]), ((gnd_wire # (! nose[189..189])) # sel[189..189]), ((gnd_wire # (! nose[188..188])) # sel[188..188]), ((gnd_wire # (! nose[187..187])) # sel[187..187]), ((gnd_wire # (! nose[186..186])) # sel[186..186]), ((gnd_wire # (! nose[185..185])) # sel[185..185]), ((gnd_wire # (! nose[184..184])) # sel[184..184]), ((gnd_wire # (! nose[183..183])) # sel[183..183]), ((gnd_wire # (! nose[182..182])) # sel[182..182]), ((gnd_wire # (! nose[181..181])) # sel[181..181]), ((gnd_wire # (! nose[180..180])) # sel[180..180]), ((gnd_wire # (! nose[179..179])) # sel[179..179]), ((gnd_wire # (! nose[178..178])) # sel[178..178]), ((gnd_wire # (! nose[177..177])) # sel[177..177]), ((gnd_wire # (! nose[176..176])) # sel[176..176]), ((gnd_wire # (! nose[175..175])) # sel[175..175]), ((gnd_wire # (! nose[174..174])) # sel[174..174]), ((gnd_wire # (! nose[173..173])) # sel[173..173]), ((gnd_wire # (! nose[172..172])) # sel[172..172]), ((gnd_wire # (! nose[171..171])) # sel[171..171]), ((gnd_wire # (! nose[170..170])) # sel[170..170]), ((gnd_wire # (! nose[169..169])) # sel[169..169]), ((gnd_wire # (! nose[168..168])) # sel[168..168]), ((gnd_wire # (! nose[167..167])) # sel[167..167]), ((gnd_wire # (! nose[166..166])) # sel[166..166]), ((gnd_wire # (! nose[165..165])) # sel[165..165]), ((gnd_wire # (! nose[164..164])) # sel[164..164]), ((gnd_wire # (! nose[163..163])) # sel[163..163]), ((gnd_wire # (! nose[162..162])) # sel[162..162]), ((gnd_wire # (! nose[161..161])) # sel[161..161]), ((gnd_wire # (! nose[160..160])) # sel[160..160]), ((gnd_wire # (! nose[159..159])) # sel[159..159]), ((gnd_wire # (! nose[158..158])) # sel[158..158]), ((gnd_wire # (! nose[157..157])) # sel[157..157]), ((gnd_wire # (! nose[156..156])) # sel[156..156]), ((gnd_wire # (! nose[155..155])) # sel[155..155]), ((gnd_wire # (! nose[154..154])) # sel[154..154]), ((gnd_wire # (! nose[153..153])) # sel[153..153]), ((gnd_wire # (! nose[152..152])) # sel[152..152]), ((gnd_wire # (! nose[151..151])) # sel[151..151]), ((gnd_wire # (! nose[150..150])) # sel[150..150]), ((gnd_wire # (! nose[149..149])) # sel[149..149]), ((gnd_wire # (! nose[148..148])) # sel[148..148]), ((gnd_wire # (! nose[147..147])) # sel[147..147]), ((gnd_wire # (! nose[146..146])) # sel[146..146]), ((gnd_wire # (! nose[145..145])) # sel[145..145]), ((gnd_wire # (! nose[144..144])) # sel[144..144]), ((gnd_wire # (! nose[143..143])) # sel[143..143]), ((gnd_wire # (! nose[142..142])) # sel[142..142]), ((gnd_wire # (! nose[141..141])) # sel[141..141]), ((gnd_wire # (! nose[140..140])) # sel[140..140]), ((gnd_wire # (! nose[139..139])) # sel[139..139]), ((gnd_wire # (! nose[138..138])) # sel[138..138]), ((gnd_wire # (! nose[137..137])) # sel[137..137]), ((gnd_wire # (! nose[136..136])) # sel[136..136]), ((gnd_wire # (! nose[135..135])) # sel[135..135]), ((gnd_wire # (! nose[134..134])) # sel[134..134]), ((gnd_wire # (! nose[133..133])) # sel[133..133]), ((gnd_wire # (! nose[132..132])) # sel[132..132]), ((gnd_wire # (! nose[131..131])) # sel[131..131]), ((gnd_wire # (! nose[130..130])) # sel[130..130]), ((gnd_wire # (! nose[129..129])) # sel[129..129]), ((gnd_wire # (! nose[128..128])) # sel[128..128]), ((gnd_wire # (! nose[127..127])) # sel[127..127]), ((gnd_wire # (! nose[126..126])) # sel[126..126]), ((gnd_wire # (! nose[125..125])) # sel[125..125]), ((gnd_wire # (! nose[124..124])) # sel[124..124]), ((gnd_wire # (! nose[123..123])) # sel[123..123]), ((gnd_wire # (! nose[122..122])) # sel[122..122]), ((gnd_wire # (! nose[121..121])) # sel[121..121]), ((gnd_wire # (! nose[120..120])) # sel[120..120]), ((gnd_wire # (! nose[119..119])) # sel[119..119]), ((gnd_wire # (! nose[118..118])) # sel[118..118]), ((gnd_wire # (! nose[117..117])) # sel[117..117]), ((gnd_wire # (! nose[116..116])) # sel[116..116]), ((gnd_wire # (! nose[115..115])) # sel[115..115]), ((gnd_wire # (! nose[114..114])) # sel[114..114]), ((gnd_wire # (! nose[113..113])) # sel[113..113]), ((gnd_wire # (! nose[112..112])) # sel[112..112]), ((gnd_wire # (! nose[111..111])) # sel[111..111]), ((gnd_wire # (! nose[110..110])) # sel[110..110]), ((gnd_wire # (! nose[109..109])) # sel[109..109]), ((gnd_wire # (! nose[108..108])) # sel[108..108]), ((gnd_wire # (! nose[107..107])) # sel[107..107]), ((gnd_wire # (! nose[106..106])) # sel[106..106]), ((gnd_wire # (! nose[105..105])) # sel[105..105]), ((gnd_wire # (! nose[104..104])) # sel[104..104]), ((gnd_wire # (! nose[103..103])) # sel[103..103]), ((gnd_wire # (! nose[102..102])) # sel[102..102]), ((gnd_wire # (! nose[101..101])) # sel[101..101]), ((gnd_wire # (! nose[100..100])) # sel[100..100]), ((gnd_wire # (! nose[99..99])) # sel[99..99]), ((gnd_wire # (! nose[98..98])) # sel[98..98]), ((gnd_wire # (! nose[97..97])) # sel[97..97]), ((gnd_wire # (! nose[96..96])) # sel[96..96]), ((gnd_wire # (! nose[95..95])) # sel[95..95]), ((gnd_wire # (! nose[94..94])) # sel[94..94]), ((gnd_wire # (! nose[93..93])) # sel[93..93]), ((gnd_wire # (! nose[92..92])) # sel[92..92]), ((gnd_wire # (! nose[91..91])) # sel[91..91]), ((gnd_wire # (! nose[90..90])) # sel[90..90]), ((gnd_wire # (! nose[89..89])) # sel[89..89]), ((gnd_wire # (! nose[88..88])) # sel[88..88]), ((gnd_wire # (! nose[87..87])) # sel[87..87]), ((gnd_wire # (! nose[86..86])) # sel[86..86]), ((gnd_wire # (! nose[85..85])) # sel[85..85]), ((gnd_wire # (! nose[84..84])) # sel[84..84]), ((gnd_wire # (! nose[83..83])) # sel[83..83]), ((gnd_wire # (! nose[82..82])) # sel[82..82]), ((gnd_wire # (! nose[81..81])) # sel[81..81]), ((gnd_wire # (! nose[80..80])) # sel[80..80]), ((gnd_wire # (! nose[79..79])) # sel[79..79]), ((gnd_wire # (! nose[78..78])) # sel[78..78]), ((gnd_wire # (! nose[77..77])) # sel[77..77]), ((gnd_wire # (! nose[76..76])) # sel[76..76]), ((gnd_wire # (! nose[75..75])) # sel[75..75]), ((gnd_wire # (! nose[74..74])) # sel[74..74]), ((gnd_wire # (! nose[73..73])) # sel[73..73]), ((gnd_wire # (! nose[72..72])) # sel[72..72]), ((gnd_wire # (! nose[71..71])) # sel[71..71]), ((gnd_wire # (! nose[70..70])) # sel[70..70]), ((gnd_wire # (! nose[69..69])) # sel[69..69]), ((gnd_wire # (! nose[68..68])) # sel[68..68]), ((gnd_wire # (! nose[67..67])) # sel[67..67]), ((gnd_wire # (! nose[66..66])) # sel[66..66]), ((gnd_wire # (! nose[65..65])) # sel[65..65]), ((gnd_wire # (! nose[64..64])) # sel[64..64]), ((gnd_wire # (! nose[63..63])) # sel[63..63]), ((gnd_wire # (! nose[62..62])) # sel[62..62]), ((gnd_wire # (! nose[61..61])) # sel[61..61]), ((gnd_wire # (! nose[60..60])) # sel[60..60]), ((gnd_wire # (! nose[59..59])) # sel[59..59]), ((gnd_wire # (! nose[58..58])) # sel[58..58]), ((gnd_wire # (! nose[57..57])) # sel[57..57]), ((gnd_wire # (! nose[56..56])) # sel[56..56]), ((gnd_wire # (! nose[55..55])) # sel[55..55]), ((gnd_wire # (! nose[54..54])) # sel[54..54]), ((gnd_wire # (! nose[53..53])) # sel[53..53]), ((gnd_wire # (! nose[52..52])) # sel[52..52]), ((gnd_wire # (! nose[51..51])) # sel[51..51]), ((gnd_wire # (! nose[50..50])) # sel[50..50]), ((gnd_wire # (! nose[49..49])) # sel[49..49]), ((gnd_wire # (! nose[48..48])) # sel[48..48]), ((gnd_wire # (! nose[47..47])) # sel[47..47]), ((gnd_wire # (! nose[46..46])) # sel[46..46]), ((gnd_wire # (! nose[45..45])) # sel[45..45]), ((gnd_wire # (! nose[44..44])) # sel[44..44]), ((gnd_wire # (! nose[43..43])) # sel[43..43]), ((gnd_wire # (! nose[42..42])) # sel[42..42]), ((gnd_wire # (! nose[41..41])) # sel[41..41]), ((gnd_wire # (! nose[40..40])) # sel[40..40]), ((gnd_wire # (! nose[39..39])) # sel[39..39]), ((gnd_wire # (! nose[38..38])) # sel[38..38]), ((gnd_wire # (! nose[37..37])) # sel[37..37]), ((gnd_wire # (! nose[36..36])) # sel[36..36]), ((gnd_wire # (! nose[35..35])) # sel[35..35]), ((gnd_wire # (! nose[34..34])) # sel[34..34]), ((gnd_wire # (! nose[33..33])) # sel[33..33]), ((gnd_wire # (! nose[32..32])) # sel[32..32]), ((gnd_wire # (! nose[31..31])) # sel[31..31]), ((gnd_wire # (! nose[30..30])) # sel[30..30]), ((gnd_wire # (! nose[29..29])) # sel[29..29]), ((gnd_wire # (! nose[28..28])) # sel[28..28]), ((gnd_wire # (! nose[27..27])) # sel[27..27]), ((gnd_wire # (! nose[26..26])) # sel[26..26]), ((gnd_wire # (! nose[25..25])) # sel[25..25]), ((gnd_wire # (! nose[24..24])) # sel[24..24]), ((gnd_wire # (! nose[23..23])) # sel[23..23]), ((gnd_wire # (! nose[22..22])) # sel[22..22]), ((gnd_wire # (! nose[21..21])) # sel[21..21]), ((gnd_wire # (! nose[20..20])) # sel[20..20]), ((gnd_wire # (! nose[19..19])) # sel[19..19]), ((gnd_wire # (! nose[18..18])) # sel[18..18]), ((gnd_wire # (! nose[17..17])) # sel[17..17]), ((gnd_wire # (! nose[16..16])) # sel[16..16]), ((gnd_wire # (! nose[15..15])) # sel[15..15]), ((gnd_wire # (! nose[14..14])) # sel[14..14]), ((gnd_wire # (! nose[13..13])) # sel[13..13]), ((gnd_wire # (! nose[12..12])) # sel[12..12]), ((gnd_wire # (! nose[11..11])) # sel[11..11]), ((gnd_wire # (! nose[10..10])) # sel[10..10]), ((gnd_wire # (! nose[9..9])) # sel[9..9]), ((gnd_wire # (! nose[8..8])) # sel[8..8]), ((gnd_wire # (! nose[7..7])) # sel[7..7]), ((gnd_wire # (! nose[6..6])) # sel[6..6]), ((gnd_wire # (! nose[5..5])) # sel[5..5]), ((gnd_wire # (! nose[4..4])) # sel[4..4]), ((gnd_wire # (! nose[3..3])) # sel[3..3]), ((gnd_wire # (! nose[2..2])) # sel[2..2]), ((gnd_wire # (! nose[1..1])) # sel[1..1]), ((gnd_wire # (! nose[0..0])) # sel[0..0]));
+ StageIn[] = (gnd_wire # StageIn_tmp[]);
+ StageIn_tmp[] = ( StageOut[624..0], B"0000000000000000000000000");
+ StageOut[] = ( ((( StageIn[623..600], NumeratorIn[600..600]) & selnose[624..624]) # (prestg[624..600] & (! selnose[624..624]))), ((( StageIn[598..575], NumeratorIn[576..576]) & selnose[598..598]) # (prestg[599..575] & (! selnose[598..598]))), ((( StageIn[573..550], NumeratorIn[552..552]) & selnose[572..572]) # (prestg[574..550] & (! selnose[572..572]))), ((( StageIn[548..525], NumeratorIn[528..528]) & selnose[546..546]) # (prestg[549..525] & (! selnose[546..546]))), ((( StageIn[523..500], NumeratorIn[504..504]) & selnose[520..520]) # (prestg[524..500] & (! selnose[520..520]))), ((( StageIn[498..475], NumeratorIn[480..480]) & selnose[494..494]) # (prestg[499..475] & (! selnose[494..494]))), ((( StageIn[473..450], NumeratorIn[456..456]) & selnose[468..468]) # (prestg[474..450] & (! selnose[468..468]))), ((( StageIn[448..425], NumeratorIn[432..432]) & selnose[442..442]) # (prestg[449..425] & (! selnose[442..442]))), ((( StageIn[423..400], NumeratorIn[408..408]) & selnose[416..416]) # (prestg[424..400] & (! selnose[416..416]))), ((( StageIn[398..375], NumeratorIn[384..384]) & selnose[390..390]) # (prestg[399..375] & (! selnose[390..390]))), ((( StageIn[373..350], NumeratorIn[360..360]) & selnose[364..364]) # (prestg[374..350] & (! selnose[364..364]))), ((( StageIn[348..325], NumeratorIn[336..336]) & selnose[338..338]) # (prestg[349..325] & (! selnose[338..338]))), ((( StageIn[323..300], NumeratorIn[312..312]) & selnose[312..312]) # (prestg[324..300] & (! selnose[312..312]))), ((( StageIn[298..275], NumeratorIn[288..288]) & selnose[286..286]) # (prestg[299..275] & (! selnose[286..286]))), ((( StageIn[273..250], NumeratorIn[264..264]) & selnose[260..260]) # (prestg[274..250] & (! selnose[260..260]))), ((( StageIn[248..225], NumeratorIn[240..240]) & selnose[234..234]) # (prestg[249..225] & (! selnose[234..234]))), ((( StageIn[223..200], NumeratorIn[216..216]) & selnose[208..208]) # (prestg[224..200] & (! selnose[208..208]))), ((( StageIn[198..175], NumeratorIn[192..192]) & selnose[182..182]) # (prestg[199..175] & (! selnose[182..182]))), ((( StageIn[173..150], NumeratorIn[168..168]) & selnose[156..156]) # (prestg[174..150] & (! selnose[156..156]))), ((( StageIn[148..125], NumeratorIn[144..144]) & selnose[130..130]) # (prestg[149..125] & (! selnose[130..130]))), ((( StageIn[123..100], NumeratorIn[120..120]) & selnose[104..104]) # (prestg[124..100] & (! selnose[104..104]))), ((( StageIn[98..75], NumeratorIn[96..96]) & selnose[78..78]) # (prestg[99..75] & (! selnose[78..78]))), ((( StageIn[73..50], NumeratorIn[72..72]) & selnose[52..52]) # (prestg[74..50] & (! selnose[52..52]))), ((( StageIn[48..25], NumeratorIn[48..48]) & selnose[26..26]) # (prestg[49..25] & (! selnose[26..26]))), ((( StageIn[23..0], NumeratorIn[24..24]) & selnose[0..0]) # (prestg[24..0] & (! selnose[0..0]))));
+END;
+--VALID FILE
--- /dev/null
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 30 19:53:02 2009 " "Info: Processing started: Mon Mar 30 19:53:02 2009" { } { } 0 0 "Processing started: %1!s!" 0 0} } { } 4 0 "Running %2!s! %1!s!" 0 0}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off demo -c demo " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off demo -c demo" { } { } 0 0 "Command: %1!s!" 0 0}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 30 19:53:29 2009 " "Info: Processing ended: Mon Mar 30 19:53:29 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:27 " "Info: Elapsed time: 00:00:27" { } { } 0 0 "Elapsed time: %1!s!" 0 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
--- /dev/null
+<?xml version="1.0" ?>
+<LOG_ROOT>
+ <PROJECT NAME="demo">
+ <CBX_INST_ENTRY INSTANCE_NAME="|demo_top|demo:inst|lpm_divide:Mod0" CBX_FILE_NAME="lpm_divide_85m.tdf"/>
+ </PROJECT>
+</LOG_ROOT>
--- /dev/null
+Quartus_Version = Version 7.0 Build 33 02/05/2007 SJ Full Version
+Version_Index = 100671744
+Creation_Time = Tue Mar 24 17:09:40 2009
--- /dev/null
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II " "Info: Running Quartus II EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 30 19:53:35 2009 " "Info: Processing started: Mon Mar 30 19:53:35 2009" { } { } 0 0 "Processing started: %1!s!" 0 0} } { } 4 0 "Running %2!s! %1!s!" 0 0}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off demo -c demo " "Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off demo -c demo" { } { } 0 0 "Command: %1!s!" 0 0}
+{ "Info" "IWSC_DONE_HDL_SDO_GENERATION" "demo.vho demo_vhd.sdo /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/simulation/modelsim/ simulation " "Info: Generated files \"demo.vho\" and \"demo_vhd.sdo\" in directory \"/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/simulation/modelsim/\" for EDA simulation tool" { } { } 0 0 "Generated files \"%1!s!\" and \"%2!s!\" in directory \"%3!s!\" for EDA %4!s! tool" 0 0}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II " "Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 30 19:53:36 2009 " "Info: Processing ended: Mon Mar 30 19:53:36 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
--- /dev/null
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 30 19:52:45 2009 " "Info: Processing started: Mon Mar 30 19:52:45 2009" { } { } 0 0 "Processing started: %1!s!" 0 0} } { } 4 0 "Running %2!s! %1!s!" 0 0}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off demo -c demo " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off demo -c demo" { } { } 0 0 "Command: %1!s!" 0 0}
+{ "Info" "IMPP_MPP_USER_DEVICE" "demo EP2C35F484C6 " "Info: Selected device EP2C35F484C6 for design \"demo\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
+{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "pll:inst1\|altpll:altpll_component\|pll Cyclone II " "Info: Implemented PLL \"pll:inst1\|altpll:altpll_component\|pll\" as Cyclone II PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "pll:inst1\|altpll:altpll_component\|_clk0 4 1 0 0 " "Info: Implementing clock multiplication of 4, clock division of 1, and phase shift of 0 degrees (0 ps) for pll:inst1\|altpll:altpll_component\|_clk0 port" { } { { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } } } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0} } { { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } } } 0 0 "Implemented PLL \"%1!s!\" as %2!s! PLL type" 0 0}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
+{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0}
+{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 0 "Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" 0 0}
+{ "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_TOP" "1 0 " "Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use" { { "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_NONE_OVERRIDE" "92 Top " "Info: Previous placement does not exist for 92 of 92 atoms in partition Top" { } { } 0 0 "Previous placement does not exist for %1!d! of %1!d! atoms in partition %2!s!" 0 0} } { } 0 0 "The Fitter has identified %1!d! logical partitions of which %2!d! have a previous placement to use" 0 0}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C15AF484C6 " "Info: Device EP2C15AF484C6 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C20F484C6 " "Info: Device EP2C20F484C6 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F484C6 " "Info: Device EP2C50F484C6 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ C4 " "Info: Pin ~ASDO~ is reserved at location C4" { } { } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ C3 " "Info: Pin ~nCSO~ is reserved at location C3" { } { } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS150p/nCEO~ W20 " "Info: Pin ~LVDS150p/nCEO~ is reserved at location W20" { } { } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "pll:inst1\|altpll:altpll_component\|_clk0 (placed in counter C0 of PLL_1) " "Info: Automatically promoted node pll:inst1\|altpll:altpll_component\|_clk0 (placed in counter C0 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} } { { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 495 3 0 } } { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "" { pll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "" { pll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:01 " "Info: Finished register packing: elapsed time is 00:00:01" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0} } { } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
+{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "6.881 ns register register " "Info: Estimated most critical path is register to register delay of 6.881 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns demo:inst\|counter\[3\] 1 REG LAB_X57_Y31 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X57_Y31; Fanout = 3; REG Node = 'demo:inst\|counter\[3\]'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "" { demo:inst|counter[3] } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 82 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.914 ns) + CELL(0.414 ns) 1.328 ns demo:inst\|Add0~101 2 COMB LAB_X55_Y31 2 " "Info: 2: + IC(0.914 ns) + CELL(0.414 ns) = 1.328 ns; Loc. = LAB_X55_Y31; Fanout = 2; COMB Node = 'demo:inst\|Add0~101'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "1.328 ns" { demo:inst|counter[3] demo:inst|Add0~101 } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 86 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 1.738 ns demo:inst\|Add0~102 3 COMB LAB_X55_Y31 3 " "Info: 3: + IC(0.000 ns) + CELL(0.410 ns) = 1.738 ns; Loc. = LAB_X55_Y31; Fanout = 3; COMB Node = 'demo:inst\|Add0~102'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.410 ns" { demo:inst|Add0~101 demo:inst|Add0~102 } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 86 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.397 ns) + CELL(0.414 ns) 2.549 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[3\]~19 4 COMB LAB_X55_Y31 2 " "Info: 4: + IC(0.397 ns) + CELL(0.414 ns) = 2.549 ns; Loc. = LAB_X55_Y31; Fanout = 2; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[3\]~19'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.811 ns" { demo:inst|Add0~102 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[3]~19 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 57 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.620 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[4\]~21 5 COMB LAB_X55_Y31 2 " "Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 2.620 ns; Loc. = LAB_X55_Y31; Fanout = 2; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[4\]~21'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.071 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[3]~19 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[4]~21 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 57 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.691 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[5\]~23 6 COMB LAB_X55_Y31 2 " "Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 2.691 ns; Loc. = LAB_X55_Y31; Fanout = 2; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[5\]~23'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.071 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[4]~21 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[5]~23 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 57 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.762 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[6\]~25 7 COMB LAB_X55_Y31 1 " "Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 2.762 ns; Loc. = LAB_X55_Y31; Fanout = 1; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[6\]~25'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.071 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[5]~23 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[6]~25 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 57 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 3.172 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[7\]~26 8 COMB LAB_X55_Y31 14 " "Info: 8: + IC(0.000 ns) + CELL(0.410 ns) = 3.172 ns; Loc. = LAB_X55_Y31; Fanout = 14; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[7\]~26'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.410 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[6]~25 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[7]~26 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 57 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.587 ns) + CELL(0.437 ns) 4.196 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|StageOut\[49\]~22 9 COMB LAB_X57_Y31 2 " "Info: 9: + IC(0.587 ns) + CELL(0.437 ns) = 4.196 ns; Loc. = LAB_X57_Y31; Fanout = 2; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|StageOut\[49\]~22'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "1.024 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[7]~26 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[49]~22 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 79 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.397 ns) + CELL(0.414 ns) 5.007 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[2\]~21 10 COMB LAB_X57_Y31 2 " "Info: 10: + IC(0.397 ns) + CELL(0.414 ns) = 5.007 ns; Loc. = LAB_X57_Y31; Fanout = 2; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[2\]~21'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.811 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[49]~22 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[2]~21 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 62 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 5.078 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[3\]~23 11 COMB LAB_X57_Y31 2 " "Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 5.078 ns; Loc. = LAB_X57_Y31; Fanout = 2; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[3\]~23'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.071 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[2]~21 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[3]~23 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 62 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 5.149 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[4\]~25 12 COMB LAB_X57_Y31 2 " "Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 5.149 ns; Loc. = LAB_X57_Y31; Fanout = 2; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[4\]~25'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.071 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[3]~23 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[4]~25 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 62 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 5.220 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[5\]~27 13 COMB LAB_X57_Y31 2 " "Info: 13: + IC(0.000 ns) + CELL(0.071 ns) = 5.220 ns; Loc. = LAB_X57_Y31; Fanout = 2; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[5\]~27'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.071 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[4]~25 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[5]~27 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 62 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 5.291 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[6\]~29 14 COMB LAB_X57_Y31 1 " "Info: 14: + IC(0.000 ns) + CELL(0.071 ns) = 5.291 ns; Loc. = LAB_X57_Y31; Fanout = 1; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[6\]~29'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.071 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[5]~27 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[6]~29 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 62 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 5.362 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[7\]~31 15 COMB LAB_X57_Y31 1 " "Info: 15: + IC(0.000 ns) + CELL(0.071 ns) = 5.362 ns; Loc. = LAB_X57_Y31; Fanout = 1; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[7\]~31'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.071 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[6]~29 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[7]~31 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 62 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 5.772 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[8\]~32 16 COMB LAB_X57_Y31 7 " "Info: 16: + IC(0.000 ns) + CELL(0.410 ns) = 5.772 ns; Loc. = LAB_X57_Y31; Fanout = 7; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[8\]~32'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.410 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[7]~31 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[8]~32 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 62 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.875 ns) + CELL(0.150 ns) 6.797 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|StageOut\[57\]~636 17 COMB LAB_X55_Y31 1 " "Info: 17: + IC(0.875 ns) + CELL(0.150 ns) = 6.797 ns; Loc. = LAB_X55_Y31; Fanout = 1; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|StageOut\[57\]~636'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "1.025 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[8]~32 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[57]~636 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 79 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 6.881 ns demo:inst\|counter\[1\] 18 REG LAB_X55_Y31 3 " "Info: 18: + IC(0.000 ns) + CELL(0.084 ns) = 6.881 ns; Loc. = LAB_X55_Y31; Fanout = 3; REG Node = 'demo:inst\|counter\[1\]'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.084 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[57]~636 demo:inst|counter[1] } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 82 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.711 ns ( 53.93 % ) " "Info: Total cell delay = 3.711 ns ( 53.93 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.170 ns ( 46.07 % ) " "Info: Total interconnect delay = 3.170 ns ( 46.07 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "6.881 ns" { demo:inst|counter[3] demo:inst|Add0~101 demo:inst|Add0~102 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[3]~19 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[4]~21 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[5]~23 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[6]~25 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[7]~26 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[49]~22 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[2]~21 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[3]~23 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[4]~25 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[5]~27 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[6]~29 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[7]~31 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[8]~32 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[57]~636 demo:inst|counter[1] } "NODE_NAME" } } } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X22_Y12 X32_Y23 " "Info: The peak interconnect region extends from location X22_Y12 to location X32_Y23" { } { } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0}
+{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0}
+{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "8 " "Warning: Found 8 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDS\[7\] 0 " "Info: Pin \"LEDS\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDS\[6\] 0 " "Info: Pin \"LEDS\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDS\[5\] 0 " "Info: Pin \"LEDS\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDS\[4\] 0 " "Info: Pin \"LEDS\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDS\[3\] 0 " "Info: Pin \"LEDS\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDS\[2\] 0 " "Info: Pin \"LEDS\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDS\[1\] 0 " "Info: Pin \"LEDS\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDS\[0\] 0 " "Info: Pin \"LEDS\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 30 19:52:59 2009 " "Info: Processing ended: Mon Mar 30 19:52:59 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Info: Elapsed time: 00:00:14" { } { } 0 0 "Elapsed time: %1!s!" 0 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/demo.fit.smsg " "Info: Generated suppressed messages file /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/demo.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0}
--- /dev/null
+|demo_top
+LEDS[0] <= demo:inst.leds[0]
+LEDS[1] <= demo:inst.leds[1]
+LEDS[2] <= demo:inst.leds[2]
+LEDS[3] <= demo:inst.leds[3]
+LEDS[4] <= demo:inst.leds[4]
+LEDS[5] <= demo:inst.leds[5]
+LEDS[6] <= demo:inst.leds[6]
+LEDS[7] <= demo:inst.leds[7]
+CLK => pll:inst1.inclk0
+RESET => demo:inst.reset
+
+
+|demo_top|demo:inst
+clk => counter[0].CLK
+clk => counter[1].CLK
+clk => counter[2].CLK
+clk => counter[3].CLK
+clk => counter[4].CLK
+clk => counter[5].CLK
+clk => counter[6].CLK
+clk => ledstate.CLK
+clk => knightlight[0].CLK
+clk => knightlight[1].CLK
+clk => knightlight[2].CLK
+clk => knightlight[3].CLK
+clk => knightlight[4].CLK
+clk => knightlight[5].CLK
+clk => knightlight[6].CLK
+clk => knightlight[7].CLK
+reset => knightlight~0.OUTPUTSELECT
+reset => knightlight~1.OUTPUTSELECT
+reset => knightlight~2.OUTPUTSELECT
+reset => knightlight~3.OUTPUTSELECT
+reset => knightlight~4.OUTPUTSELECT
+reset => knightlight~5.OUTPUTSELECT
+reset => knightlight~6.OUTPUTSELECT
+reset => knightlight~7.OUTPUTSELECT
+reset => ledstate~0.OUTPUTSELECT
+reset => counter~0.OUTPUTSELECT
+reset => counter~1.OUTPUTSELECT
+reset => counter~2.OUTPUTSELECT
+reset => counter~3.OUTPUTSELECT
+reset => counter~4.OUTPUTSELECT
+reset => counter~5.OUTPUTSELECT
+reset => counter~6.OUTPUTSELECT
+leds[0] <= knightlight[0].DB_MAX_OUTPUT_PORT_TYPE
+leds[1] <= knightlight[1].DB_MAX_OUTPUT_PORT_TYPE
+leds[2] <= knightlight[2].DB_MAX_OUTPUT_PORT_TYPE
+leds[3] <= knightlight[3].DB_MAX_OUTPUT_PORT_TYPE
+leds[4] <= knightlight[4].DB_MAX_OUTPUT_PORT_TYPE
+leds[5] <= knightlight[5].DB_MAX_OUTPUT_PORT_TYPE
+leds[6] <= knightlight[6].DB_MAX_OUTPUT_PORT_TYPE
+leds[7] <= knightlight[7].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|demo_top|pll:inst1
+inclk0 => altpll:altpll_component.inclk[0]
+c0 <= altpll:altpll_component.clk[0]
+
+
+|demo_top|pll:inst1|altpll:altpll_component
+inclk[0] => pll.CLK
+inclk[1] => ~NO_FANOUT~
+fbin => ~NO_FANOUT~
+pllena => ~NO_FANOUT~
+clkswitch => ~NO_FANOUT~
+areset => ~NO_FANOUT~
+pfdena => ~NO_FANOUT~
+clkena[0] => ~NO_FANOUT~
+clkena[1] => ~NO_FANOUT~
+clkena[2] => ~NO_FANOUT~
+clkena[3] => ~NO_FANOUT~
+clkena[4] => ~NO_FANOUT~
+clkena[5] => ~NO_FANOUT~
+extclkena[0] => ~NO_FANOUT~
+extclkena[1] => ~NO_FANOUT~
+extclkena[2] => ~NO_FANOUT~
+extclkena[3] => ~NO_FANOUT~
+scanclk => ~NO_FANOUT~
+scanclkena => ~NO_FANOUT~
+scanaclr => ~NO_FANOUT~
+scanread => ~NO_FANOUT~
+scanwrite => ~NO_FANOUT~
+scandata => ~NO_FANOUT~
+phasecounterselect[0] => ~NO_FANOUT~
+phasecounterselect[1] => ~NO_FANOUT~
+phasecounterselect[2] => ~NO_FANOUT~
+phasecounterselect[3] => ~NO_FANOUT~
+phaseupdown => ~NO_FANOUT~
+phasestep => ~NO_FANOUT~
+configupdate => ~NO_FANOUT~
+clk[0] <= clk[0]~0.DB_MAX_OUTPUT_PORT_TYPE
+clk[1] <= <GND>
+clk[2] <= <GND>
+clk[3] <= <GND>
+clk[4] <= <GND>
+clk[5] <= <GND>
+extclk[0] <= <GND>
+extclk[1] <= <GND>
+extclk[2] <= <GND>
+extclk[3] <= <GND>
+clkbad[0] <= <GND>
+clkbad[1] <= <GND>
+enable1 <= <GND>
+enable0 <= <GND>
+activeclock <= <GND>
+clkloss <= <GND>
+locked <= <GND>
+scandataout <= <GND>
+scandone <= <GND>
+sclkout0 <= <GND>
+sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE
+phasedone <= <GND>
+vcooverrange <= <GND>
+vcounderrange <= <GND>
+fbout <= <GND>
+
+
--- /dev/null
+Version 7.0 Build 33 02/05/2007 SJ Full Version
+11
+866
+OFF
+OFF
+OFF
+OFF
+ON
+FV_OFF
+Level2
+0
+0
+VRSM_ON
+VHSM_ON
+0
+-- Start Partition --
+-- End Partition --
+-- Start Library Paths --
+-- End Library Paths --
+-- Start VHDL Libraries --
+-- End VHDL Libraries --
+# entity
+pll
+# storage
+db|demo.(2).cnf
+db|demo.(2).cnf
+# logic_option {
+AUTO_RAM_RECOGNITION
+ON
+}
+# case_insensitive
+# source_file
+..|src|pll.vhd
+1866c9e27a803e38a86b84bedcb78419
+4
+# internal_option {
+AUTO_RESOURCE_SHARING
+OFF
+}
+# hierarchies {
+pll:inst1
+}
+# end
+# entity
+altpll
+# storage
+db|demo.(3).cnf
+db|demo.(3).cnf
+# case_insensitive
+# source_file
+|opt|quartus|libraries|megafunctions|altpll.tdf
+9948948e9c204c786e29bcceb2be7f
+6
+# user_parameter {
+OPERATION_MODE
+NORMAL
+PARAMETER_UNKNOWN
+USR
+PLL_TYPE
+AUTO
+PARAMETER_UNKNOWN
+DEF
+QUALIFY_CONF_DONE
+OFF
+PARAMETER_UNKNOWN
+DEF
+COMPENSATE_CLOCK
+CLK0
+PARAMETER_UNKNOWN
+USR
+SCAN_CHAIN
+LONG
+PARAMETER_UNKNOWN
+DEF
+PRIMARY_CLOCK
+INCLK0
+PARAMETER_UNKNOWN
+DEF
+INCLK0_INPUT_FREQUENCY
+40000
+PARAMETER_SIGNED_DEC
+USR
+INCLK1_INPUT_FREQUENCY
+0
+PARAMETER_UNKNOWN
+DEF
+GATE_LOCK_SIGNAL
+NO
+PARAMETER_UNKNOWN
+DEF
+GATE_LOCK_COUNTER
+0
+PARAMETER_UNKNOWN
+DEF
+LOCK_HIGH
+1
+PARAMETER_UNKNOWN
+DEF
+LOCK_LOW
+1
+PARAMETER_UNKNOWN
+DEF
+VALID_LOCK_MULTIPLIER
+1
+PARAMETER_UNKNOWN
+DEF
+INVALID_LOCK_MULTIPLIER
+5
+PARAMETER_UNKNOWN
+DEF
+SWITCH_OVER_ON_LOSSCLK
+OFF
+PARAMETER_UNKNOWN
+DEF
+SWITCH_OVER_ON_GATED_LOCK
+OFF
+PARAMETER_UNKNOWN
+DEF
+ENABLE_SWITCH_OVER_COUNTER
+OFF
+PARAMETER_UNKNOWN
+DEF
+SKIP_VCO
+OFF
+PARAMETER_UNKNOWN
+DEF
+SWITCH_OVER_COUNTER
+0
+PARAMETER_UNKNOWN
+DEF
+SWITCH_OVER_TYPE
+AUTO
+PARAMETER_UNKNOWN
+DEF
+FEEDBACK_SOURCE
+EXTCLK0
+PARAMETER_UNKNOWN
+DEF
+BANDWIDTH
+0
+PARAMETER_UNKNOWN
+DEF
+BANDWIDTH_TYPE
+AUTO
+PARAMETER_UNKNOWN
+DEF
+SPREAD_FREQUENCY
+0
+PARAMETER_UNKNOWN
+DEF
+DOWN_SPREAD
+0
+PARAMETER_UNKNOWN
+DEF
+SELF_RESET_ON_GATED_LOSS_LOCK
+OFF
+PARAMETER_UNKNOWN
+DEF
+SELF_RESET_ON_LOSS_LOCK
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK9_MULTIPLY_BY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK8_MULTIPLY_BY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK7_MULTIPLY_BY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK6_MULTIPLY_BY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK5_MULTIPLY_BY
+1
+PARAMETER_UNKNOWN
+DEF
+CLK4_MULTIPLY_BY
+1
+PARAMETER_UNKNOWN
+DEF
+CLK3_MULTIPLY_BY
+1
+PARAMETER_UNKNOWN
+DEF
+CLK2_MULTIPLY_BY
+1
+PARAMETER_UNKNOWN
+DEF
+CLK1_MULTIPLY_BY
+1
+PARAMETER_UNKNOWN
+DEF
+CLK0_MULTIPLY_BY
+4
+PARAMETER_SIGNED_DEC
+USR
+CLK9_DIVIDE_BY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK8_DIVIDE_BY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK7_DIVIDE_BY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK6_DIVIDE_BY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK5_DIVIDE_BY
+1
+PARAMETER_UNKNOWN
+DEF
+CLK4_DIVIDE_BY
+1
+PARAMETER_UNKNOWN
+DEF
+CLK3_DIVIDE_BY
+1
+PARAMETER_UNKNOWN
+DEF
+CLK2_DIVIDE_BY
+1
+PARAMETER_UNKNOWN
+DEF
+CLK1_DIVIDE_BY
+1
+PARAMETER_UNKNOWN
+DEF
+CLK0_DIVIDE_BY
+1
+PARAMETER_SIGNED_DEC
+USR
+CLK9_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+CLK8_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+CLK7_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+CLK6_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+CLK5_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+CLK4_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+CLK3_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+CLK2_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+CLK1_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+CLK0_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+USR
+CLK5_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK4_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK3_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK2_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK1_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK0_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK9_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+CLK8_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+CLK7_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+CLK6_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+CLK5_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+CLK4_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+CLK3_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+CLK2_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+CLK1_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+CLK0_DUTY_CYCLE
+50
+PARAMETER_SIGNED_DEC
+USR
+CLK9_USE_EVEN_COUNTER_MODE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK8_USE_EVEN_COUNTER_MODE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK7_USE_EVEN_COUNTER_MODE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK6_USE_EVEN_COUNTER_MODE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK5_USE_EVEN_COUNTER_MODE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK4_USE_EVEN_COUNTER_MODE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK3_USE_EVEN_COUNTER_MODE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK2_USE_EVEN_COUNTER_MODE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK1_USE_EVEN_COUNTER_MODE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK0_USE_EVEN_COUNTER_MODE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK9_USE_EVEN_COUNTER_VALUE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK8_USE_EVEN_COUNTER_VALUE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK7_USE_EVEN_COUNTER_VALUE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK6_USE_EVEN_COUNTER_VALUE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK5_USE_EVEN_COUNTER_VALUE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK4_USE_EVEN_COUNTER_VALUE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK3_USE_EVEN_COUNTER_VALUE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK2_USE_EVEN_COUNTER_VALUE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK1_USE_EVEN_COUNTER_VALUE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK0_USE_EVEN_COUNTER_VALUE
+OFF
+PARAMETER_UNKNOWN
+DEF
+LOCK_WINDOW_UI
+ 0.05
+PARAMETER_UNKNOWN
+DEF
+EXTCLK3_MULTIPLY_BY
+1
+PARAMETER_UNKNOWN
+DEF
+EXTCLK2_MULTIPLY_BY
+1
+PARAMETER_UNKNOWN
+DEF
+EXTCLK1_MULTIPLY_BY
+1
+PARAMETER_UNKNOWN
+DEF
+EXTCLK0_MULTIPLY_BY
+1
+PARAMETER_UNKNOWN
+DEF
+EXTCLK3_DIVIDE_BY
+1
+PARAMETER_UNKNOWN
+DEF
+EXTCLK2_DIVIDE_BY
+1
+PARAMETER_UNKNOWN
+DEF
+EXTCLK1_DIVIDE_BY
+1
+PARAMETER_UNKNOWN
+DEF
+EXTCLK0_DIVIDE_BY
+1
+PARAMETER_UNKNOWN
+DEF
+EXTCLK3_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+EXTCLK2_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+EXTCLK1_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+EXTCLK0_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+EXTCLK3_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+EXTCLK2_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+EXTCLK1_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+EXTCLK0_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+EXTCLK3_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+EXTCLK2_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+EXTCLK1_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+EXTCLK0_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+VCO_MULTIPLY_BY
+0
+PARAMETER_UNKNOWN
+DEF
+VCO_DIVIDE_BY
+0
+PARAMETER_UNKNOWN
+DEF
+SCLKOUT0_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+SCLKOUT1_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+VCO_MIN
+0
+PARAMETER_UNKNOWN
+DEF
+VCO_MAX
+0
+PARAMETER_UNKNOWN
+DEF
+VCO_CENTER
+0
+PARAMETER_UNKNOWN
+DEF
+PFD_MIN
+0
+PARAMETER_UNKNOWN
+DEF
+PFD_MAX
+0
+PARAMETER_UNKNOWN
+DEF
+M_INITIAL
+0
+PARAMETER_UNKNOWN
+DEF
+M
+0
+PARAMETER_UNKNOWN
+DEF
+N
+1
+PARAMETER_UNKNOWN
+DEF
+M2
+1
+PARAMETER_UNKNOWN
+DEF
+N2
+1
+PARAMETER_UNKNOWN
+DEF
+SS
+1
+PARAMETER_UNKNOWN
+DEF
+C0_HIGH
+0
+PARAMETER_UNKNOWN
+DEF
+C1_HIGH
+0
+PARAMETER_UNKNOWN
+DEF
+C2_HIGH
+0
+PARAMETER_UNKNOWN
+DEF
+C3_HIGH
+0
+PARAMETER_UNKNOWN
+DEF
+C4_HIGH
+0
+PARAMETER_UNKNOWN
+DEF
+C5_HIGH
+0
+PARAMETER_UNKNOWN
+DEF
+C6_HIGH
+0
+PARAMETER_UNKNOWN
+DEF
+C7_HIGH
+0
+PARAMETER_UNKNOWN
+DEF
+C8_HIGH
+0
+PARAMETER_UNKNOWN
+DEF
+C9_HIGH
+0
+PARAMETER_UNKNOWN
+DEF
+C0_LOW
+0
+PARAMETER_UNKNOWN
+DEF
+C1_LOW
+0
+PARAMETER_UNKNOWN
+DEF
+C2_LOW
+0
+PARAMETER_UNKNOWN
+DEF
+C3_LOW
+0
+PARAMETER_UNKNOWN
+DEF
+C4_LOW
+0
+PARAMETER_UNKNOWN
+DEF
+C5_LOW
+0
+PARAMETER_UNKNOWN
+DEF
+C6_LOW
+0
+PARAMETER_UNKNOWN
+DEF
+C7_LOW
+0
+PARAMETER_UNKNOWN
+DEF
+C8_LOW
+0
+PARAMETER_UNKNOWN
+DEF
+C9_LOW
+0
+PARAMETER_UNKNOWN
+DEF
+C0_INITIAL
+0
+PARAMETER_UNKNOWN
+DEF
+C1_INITIAL
+0
+PARAMETER_UNKNOWN
+DEF
+C2_INITIAL
+0
+PARAMETER_UNKNOWN
+DEF
+C3_INITIAL
+0
+PARAMETER_UNKNOWN
+DEF
+C4_INITIAL
+0
+PARAMETER_UNKNOWN
+DEF
+C5_INITIAL
+0
+PARAMETER_UNKNOWN
+DEF
+C6_INITIAL
+0
+PARAMETER_UNKNOWN
+DEF
+C7_INITIAL
+0
+PARAMETER_UNKNOWN
+DEF
+C8_INITIAL
+0
+PARAMETER_UNKNOWN
+DEF
+C9_INITIAL
+0
+PARAMETER_UNKNOWN
+DEF
+C0_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+C1_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+C2_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+C3_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+C4_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+C5_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+C6_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+C7_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+C8_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+C9_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+C0_PH
+0
+PARAMETER_UNKNOWN
+DEF
+C1_PH
+0
+PARAMETER_UNKNOWN
+DEF
+C2_PH
+0
+PARAMETER_UNKNOWN
+DEF
+C3_PH
+0
+PARAMETER_UNKNOWN
+DEF
+C4_PH
+0
+PARAMETER_UNKNOWN
+DEF
+C5_PH
+0
+PARAMETER_UNKNOWN
+DEF
+C6_PH
+0
+PARAMETER_UNKNOWN
+DEF
+C7_PH
+0
+PARAMETER_UNKNOWN
+DEF
+C8_PH
+0
+PARAMETER_UNKNOWN
+DEF
+C9_PH
+0
+PARAMETER_UNKNOWN
+DEF
+L0_HIGH
+1
+PARAMETER_UNKNOWN
+DEF
+L1_HIGH
+1
+PARAMETER_UNKNOWN
+DEF
+G0_HIGH
+1
+PARAMETER_UNKNOWN
+DEF
+G1_HIGH
+1
+PARAMETER_UNKNOWN
+DEF
+G2_HIGH
+1
+PARAMETER_UNKNOWN
+DEF
+G3_HIGH
+1
+PARAMETER_UNKNOWN
+DEF
+E0_HIGH
+1
+PARAMETER_UNKNOWN
+DEF
+E1_HIGH
+1
+PARAMETER_UNKNOWN
+DEF
+E2_HIGH
+1
+PARAMETER_UNKNOWN
+DEF
+E3_HIGH
+1
+PARAMETER_UNKNOWN
+DEF
+L0_LOW
+1
+PARAMETER_UNKNOWN
+DEF
+L1_LOW
+1
+PARAMETER_UNKNOWN
+DEF
+G0_LOW
+1
+PARAMETER_UNKNOWN
+DEF
+G1_LOW
+1
+PARAMETER_UNKNOWN
+DEF
+G2_LOW
+1
+PARAMETER_UNKNOWN
+DEF
+G3_LOW
+1
+PARAMETER_UNKNOWN
+DEF
+E0_LOW
+1
+PARAMETER_UNKNOWN
+DEF
+E1_LOW
+1
+PARAMETER_UNKNOWN
+DEF
+E2_LOW
+1
+PARAMETER_UNKNOWN
+DEF
+E3_LOW
+1
+PARAMETER_UNKNOWN
+DEF
+L0_INITIAL
+1
+PARAMETER_UNKNOWN
+DEF
+L1_INITIAL
+1
+PARAMETER_UNKNOWN
+DEF
+G0_INITIAL
+1
+PARAMETER_UNKNOWN
+DEF
+G1_INITIAL
+1
+PARAMETER_UNKNOWN
+DEF
+G2_INITIAL
+1
+PARAMETER_UNKNOWN
+DEF
+G3_INITIAL
+1
+PARAMETER_UNKNOWN
+DEF
+E0_INITIAL
+1
+PARAMETER_UNKNOWN
+DEF
+E1_INITIAL
+1
+PARAMETER_UNKNOWN
+DEF
+E2_INITIAL
+1
+PARAMETER_UNKNOWN
+DEF
+E3_INITIAL
+1
+PARAMETER_UNKNOWN
+DEF
+L0_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+L1_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+G0_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+G1_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+G2_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+G3_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+E0_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+E1_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+E2_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+E3_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+L0_PH
+0
+PARAMETER_UNKNOWN
+DEF
+L1_PH
+0
+PARAMETER_UNKNOWN
+DEF
+G0_PH
+0
+PARAMETER_UNKNOWN
+DEF
+G1_PH
+0
+PARAMETER_UNKNOWN
+DEF
+G2_PH
+0
+PARAMETER_UNKNOWN
+DEF
+G3_PH
+0
+PARAMETER_UNKNOWN
+DEF
+E0_PH
+0
+PARAMETER_UNKNOWN
+DEF
+E1_PH
+0
+PARAMETER_UNKNOWN
+DEF
+E2_PH
+0
+PARAMETER_UNKNOWN
+DEF
+E3_PH
+0
+PARAMETER_UNKNOWN
+DEF
+M_PH
+0
+PARAMETER_UNKNOWN
+DEF
+C1_USE_CASC_IN
+OFF
+PARAMETER_UNKNOWN
+DEF
+C2_USE_CASC_IN
+OFF
+PARAMETER_UNKNOWN
+DEF
+C3_USE_CASC_IN
+OFF
+PARAMETER_UNKNOWN
+DEF
+C4_USE_CASC_IN
+OFF
+PARAMETER_UNKNOWN
+DEF
+C5_USE_CASC_IN
+OFF
+PARAMETER_UNKNOWN
+DEF
+C6_USE_CASC_IN
+OFF
+PARAMETER_UNKNOWN
+DEF
+C7_USE_CASC_IN
+OFF
+PARAMETER_UNKNOWN
+DEF
+C8_USE_CASC_IN
+OFF
+PARAMETER_UNKNOWN
+DEF
+C9_USE_CASC_IN
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK0_COUNTER
+G0
+PARAMETER_UNKNOWN
+DEF
+CLK1_COUNTER
+G0
+PARAMETER_UNKNOWN
+DEF
+CLK2_COUNTER
+G0
+PARAMETER_UNKNOWN
+DEF
+CLK3_COUNTER
+G0
+PARAMETER_UNKNOWN
+DEF
+CLK4_COUNTER
+G0
+PARAMETER_UNKNOWN
+DEF
+CLK5_COUNTER
+G0
+PARAMETER_UNKNOWN
+DEF
+L0_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+L1_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+G0_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+G1_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+G2_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+G3_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+E0_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+E1_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+E2_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+E3_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+M_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+N_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+EXTCLK3_COUNTER
+E3
+PARAMETER_UNKNOWN
+DEF
+EXTCLK2_COUNTER
+E2
+PARAMETER_UNKNOWN
+DEF
+EXTCLK1_COUNTER
+E1
+PARAMETER_UNKNOWN
+DEF
+EXTCLK0_COUNTER
+E0
+PARAMETER_UNKNOWN
+DEF
+ENABLE0_COUNTER
+L0
+PARAMETER_UNKNOWN
+DEF
+ENABLE1_COUNTER
+L0
+PARAMETER_UNKNOWN
+DEF
+CHARGE_PUMP_CURRENT
+2
+PARAMETER_UNKNOWN
+DEF
+LOOP_FILTER_R
+ 1.000000
+PARAMETER_UNKNOWN
+DEF
+LOOP_FILTER_C
+5
+PARAMETER_UNKNOWN
+DEF
+VCO_POST_SCALE
+0
+PARAMETER_UNKNOWN
+DEF
+CLK2_OUTPUT_FREQUENCY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK1_OUTPUT_FREQUENCY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK0_OUTPUT_FREQUENCY
+0
+PARAMETER_UNKNOWN
+DEF
+INTENDED_DEVICE_FAMILY
+Cyclone II
+PARAMETER_UNKNOWN
+USR
+PORT_CLKENA0
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+PORT_CLKENA1
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+PORT_CLKENA2
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+PORT_CLKENA3
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+PORT_CLKENA4
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+PORT_CLKENA5
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+PORT_EXTCLKENA0
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_EXTCLKENA1
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_EXTCLKENA2
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_EXTCLKENA3
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_EXTCLK0
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+PORT_EXTCLK1
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+PORT_EXTCLK2
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+PORT_EXTCLK3
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+PORT_CLKBAD0
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+PORT_CLKBAD1
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+PORT_CLK0
+PORT_USED
+PARAMETER_UNKNOWN
+USR
+PORT_CLK1
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+PORT_CLK2
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+PORT_CLK3
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+PORT_CLK4
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+PORT_CLK5
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+PORT_CLK6
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_CLK7
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_CLK8
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_CLK9
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_SCANDATA
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+PORT_SCANDATAOUT
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+PORT_SCANDONE
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+PORT_SCLKOUT1
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_SCLKOUT0
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_ACTIVECLOCK
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+PORT_CLKLOSS
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+PORT_INCLK1
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+PORT_INCLK0
+PORT_USED
+PARAMETER_UNKNOWN
+USR
+PORT_FBIN
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+PORT_PLLENA
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+PORT_CLKSWITCH
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+PORT_ARESET
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+PORT_PFDENA
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+PORT_SCANCLK
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+PORT_SCANACLR
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+PORT_SCANREAD
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+PORT_SCANWRITE
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+PORT_ENABLE0
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_ENABLE1
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_LOCKED
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+PORT_CONFIGUPDATE
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+PORT_FBOUT
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_PHASEDONE
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+PORT_PHASESTEP
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+PORT_PHASEUPDOWN
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+PORT_SCANCLKENA
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+PORT_PHASECOUNTERSELECT
+PORT_UNUSED
+PARAMETER_UNKNOWN
+USR
+M_TEST_SOURCE
+5
+PARAMETER_UNKNOWN
+DEF
+C0_TEST_SOURCE
+5
+PARAMETER_UNKNOWN
+DEF
+C1_TEST_SOURCE
+5
+PARAMETER_UNKNOWN
+DEF
+C2_TEST_SOURCE
+5
+PARAMETER_UNKNOWN
+DEF
+C3_TEST_SOURCE
+5
+PARAMETER_UNKNOWN
+DEF
+C4_TEST_SOURCE
+5
+PARAMETER_UNKNOWN
+DEF
+C5_TEST_SOURCE
+5
+PARAMETER_UNKNOWN
+DEF
+C6_TEST_SOURCE
+0
+PARAMETER_UNKNOWN
+DEF
+C7_TEST_SOURCE
+0
+PARAMETER_UNKNOWN
+DEF
+C8_TEST_SOURCE
+0
+PARAMETER_UNKNOWN
+DEF
+C9_TEST_SOURCE
+0
+PARAMETER_UNKNOWN
+DEF
+CBXI_PARAMETER
+NOTHING
+PARAMETER_UNKNOWN
+DEF
+VCO_FREQUENCY_CONTROL
+AUTO
+PARAMETER_UNKNOWN
+DEF
+VCO_PHASE_SHIFT_STEP
+0
+PARAMETER_UNKNOWN
+DEF
+WIDTH_CLOCK
+6
+PARAMETER_UNKNOWN
+DEF
+DEVICE_FAMILY
+Cyclone II
+PARAMETER_UNKNOWN
+USR
+AUTO_CARRY_CHAINS
+ON
+AUTO_CARRY
+USR
+IGNORE_CARRY_BUFFERS
+OFF
+IGNORE_CARRY
+USR
+AUTO_CASCADE_CHAINS
+ON
+AUTO_CASCADE
+USR
+IGNORE_CASCADE_BUFFERS
+OFF
+IGNORE_CASCADE
+USR
+}
+# used_port {
+inclk0
+-1
+3
+clk0
+-1
+3
+inclk1
+-1
+1
+}
+# include_file {
+|opt|quartus|libraries|megafunctions|aglobal70.inc
+6e323611d63cddcc66b682e7ab39d4b7
+|opt|quartus|libraries|megafunctions|stratix_pll.inc
+5f8211898149ceae8264a0ea5036254f
+|opt|quartus|libraries|megafunctions|stratixii_pll.inc
+6d1985e16ab5f59a1fd6b0ae20978a4e
+|opt|quartus|libraries|megafunctions|cycloneii_pll.inc
+39a0d9d1237d1db39c848c3f9faffc
+}
+# hierarchies {
+pll:inst1|altpll:altpll_component
+}
+# end
+# entity
+lpm_divide
+# storage
+db|demo.(4).cnf
+db|demo.(4).cnf
+# case_insensitive
+# source_file
+|opt|quartus|libraries|megafunctions|lpm_divide.tdf
+5dc73d7964222e4a26f9c0fe35122d62
+6
+# user_parameter {
+LPM_WIDTHN
+25
+PARAMETER_UNKNOWN
+USR
+LPM_WIDTHD
+25
+PARAMETER_UNKNOWN
+USR
+LPM_NREPRESENTATION
+UNSIGNED
+PARAMETER_UNKNOWN
+USR
+LPM_DREPRESENTATION
+UNSIGNED
+PARAMETER_UNKNOWN
+USR
+LPM_PIPELINE
+0
+PARAMETER_UNKNOWN
+DEF
+LPM_REMAINDERPOSITIVE
+TRUE
+PARAMETER_UNKNOWN
+DEF
+MAXIMIZE_SPEED
+5
+PARAMETER_UNKNOWN
+DEF
+CBXI_PARAMETER
+lpm_divide_68m
+PARAMETER_UNKNOWN
+USR
+CARRY_CHAIN
+MANUAL
+PARAMETER_UNKNOWN
+USR
+OPTIMIZE_FOR_SPEED
+5
+PARAMETER_UNKNOWN
+USR
+AUTO_CARRY_CHAINS
+ON
+AUTO_CARRY
+USR
+IGNORE_CARRY_BUFFERS
+OFF
+IGNORE_CARRY
+USR
+AUTO_CASCADE_CHAINS
+ON
+AUTO_CASCADE
+USR
+IGNORE_CASCADE_BUFFERS
+OFF
+IGNORE_CASCADE
+USR
+}
+# used_port {
+remain9
+-1
+3
+remain8
+-1
+3
+remain7
+-1
+3
+remain6
+-1
+3
+remain5
+-1
+3
+remain4
+-1
+3
+remain3
+-1
+3
+remain23
+-1
+3
+remain22
+-1
+3
+remain21
+-1
+3
+remain20
+-1
+3
+remain2
+-1
+3
+remain19
+-1
+3
+remain18
+-1
+3
+remain17
+-1
+3
+remain16
+-1
+3
+remain15
+-1
+3
+remain14
+-1
+3
+remain13
+-1
+3
+remain12
+-1
+3
+remain11
+-1
+3
+remain10
+-1
+3
+remain1
+-1
+3
+remain0
+-1
+3
+numer9
+-1
+3
+numer8
+-1
+3
+numer7
+-1
+3
+numer6
+-1
+3
+numer5
+-1
+3
+numer4
+-1
+3
+numer3
+-1
+3
+numer24
+-1
+3
+numer23
+-1
+3
+numer22
+-1
+3
+numer21
+-1
+3
+numer20
+-1
+3
+numer2
+-1
+3
+numer19
+-1
+3
+numer18
+-1
+3
+numer17
+-1
+3
+numer16
+-1
+3
+numer15
+-1
+3
+numer14
+-1
+3
+numer13
+-1
+3
+numer12
+-1
+3
+numer11
+-1
+3
+numer10
+-1
+3
+numer1
+-1
+3
+numer0
+-1
+3
+denom8
+-1
+1
+denom6
+-1
+1
+denom5
+-1
+1
+denom4
+-1
+1
+denom3
+-1
+1
+denom24
+-1
+1
+denom22
+-1
+1
+denom21
+-1
+1
+denom2
+-1
+1
+denom18
+-1
+1
+denom17
+-1
+1
+denom16
+-1
+1
+denom14
+-1
+1
+denom13
+-1
+1
+denom11
+-1
+1
+denom1
+-1
+1
+denom0
+-1
+1
+denom9
+-1
+2
+denom7
+-1
+2
+denom23
+-1
+2
+denom20
+-1
+2
+denom19
+-1
+2
+denom15
+-1
+2
+denom12
+-1
+2
+denom10
+-1
+2
+}
+# include_file {
+|opt|quartus|libraries|megafunctions|aglobal70.inc
+6e323611d63cddcc66b682e7ab39d4b7
+|opt|quartus|libraries|megafunctions|sign_div_unsign.inc
+c1e17922387cb5d0c88d7fb673544bb4
+|opt|quartus|libraries|megafunctions|abs_divider.inc
+cdfefd53e136b3a8e541899b82db37d
+}
+# end
+# entity
+lpm_divide_68m
+# storage
+db|demo.(5).cnf
+db|demo.(5).cnf
+# case_insensitive
+# source_file
+db|lpm_divide_68m.tdf
+aa7ece24474be76c0abeb51e6698f
+6
+# used_port {
+remain9
+-1
+3
+remain8
+-1
+3
+remain7
+-1
+3
+remain6
+-1
+3
+remain5
+-1
+3
+remain4
+-1
+3
+remain3
+-1
+3
+remain24
+-1
+3
+remain23
+-1
+3
+remain22
+-1
+3
+remain21
+-1
+3
+remain20
+-1
+3
+remain2
+-1
+3
+remain19
+-1
+3
+remain18
+-1
+3
+remain17
+-1
+3
+remain16
+-1
+3
+remain15
+-1
+3
+remain14
+-1
+3
+remain13
+-1
+3
+remain12
+-1
+3
+remain11
+-1
+3
+remain10
+-1
+3
+remain1
+-1
+3
+remain0
+-1
+3
+numer9
+-1
+3
+numer8
+-1
+3
+numer7
+-1
+3
+numer6
+-1
+3
+numer5
+-1
+3
+numer4
+-1
+3
+numer3
+-1
+3
+numer24
+-1
+3
+numer23
+-1
+3
+numer22
+-1
+3
+numer21
+-1
+3
+numer20
+-1
+3
+numer2
+-1
+3
+numer19
+-1
+3
+numer18
+-1
+3
+numer17
+-1
+3
+numer16
+-1
+3
+numer15
+-1
+3
+numer14
+-1
+3
+numer13
+-1
+3
+numer12
+-1
+3
+numer11
+-1
+3
+numer10
+-1
+3
+numer1
+-1
+3
+numer0
+-1
+3
+denom9
+-1
+3
+denom8
+-1
+3
+denom7
+-1
+3
+denom6
+-1
+3
+denom5
+-1
+3
+denom4
+-1
+3
+denom3
+-1
+3
+denom24
+-1
+3
+denom23
+-1
+3
+denom22
+-1
+3
+denom21
+-1
+3
+denom20
+-1
+3
+denom2
+-1
+3
+denom19
+-1
+3
+denom18
+-1
+3
+denom17
+-1
+3
+denom16
+-1
+3
+denom15
+-1
+3
+denom14
+-1
+3
+denom13
+-1
+3
+denom12
+-1
+3
+denom11
+-1
+3
+denom10
+-1
+3
+denom1
+-1
+3
+denom0
+-1
+3
+}
+# end
+# entity
+sign_div_unsign_dnh
+# storage
+db|demo.(6).cnf
+db|demo.(6).cnf
+# case_insensitive
+# source_file
+db|sign_div_unsign_dnh.tdf
+d444405ffe1be9b8a1a081c5e0acee2f
+6
+# used_port {
+remainder9
+-1
+3
+remainder8
+-1
+3
+remainder7
+-1
+3
+remainder6
+-1
+3
+remainder5
+-1
+3
+remainder4
+-1
+3
+remainder3
+-1
+3
+remainder24
+-1
+3
+remainder23
+-1
+3
+remainder22
+-1
+3
+remainder21
+-1
+3
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+-1
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+remainder2
+-1
+3
+remainder19
+-1
+3
+remainder18
+-1
+3
+remainder17
+-1
+3
+remainder16
+-1
+3
+remainder15
+-1
+3
+remainder14
+-1
+3
+remainder13
+-1
+3
+remainder12
+-1
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+remainder11
+-1
+3
+remainder10
+-1
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+remainder1
+-1
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+remainder0
+-1
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+quotient9
+-1
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+quotient8
+-1
+3
+quotient7
+-1
+3
+quotient6
+-1
+3
+quotient5
+-1
+3
+quotient4
+-1
+3
+quotient3
+-1
+3
+quotient24
+-1
+3
+quotient23
+-1
+3
+quotient22
+-1
+3
+quotient21
+-1
+3
+quotient20
+-1
+3
+quotient2
+-1
+3
+quotient19
+-1
+3
+quotient18
+-1
+3
+quotient17
+-1
+3
+quotient16
+-1
+3
+quotient15
+-1
+3
+quotient14
+-1
+3
+quotient13
+-1
+3
+quotient12
+-1
+3
+quotient11
+-1
+3
+quotient10
+-1
+3
+quotient1
+-1
+3
+quotient0
+-1
+3
+numerator9
+-1
+3
+numerator8
+-1
+3
+numerator7
+-1
+3
+numerator6
+-1
+3
+numerator5
+-1
+3
+numerator4
+-1
+3
+numerator3
+-1
+3
+numerator24
+-1
+3
+numerator23
+-1
+3
+numerator22
+-1
+3
+numerator21
+-1
+3
+numerator20
+-1
+3
+numerator2
+-1
+3
+numerator19
+-1
+3
+numerator18
+-1
+3
+numerator17
+-1
+3
+numerator16
+-1
+3
+numerator15
+-1
+3
+numerator14
+-1
+3
+numerator13
+-1
+3
+numerator12
+-1
+3
+numerator11
+-1
+3
+numerator10
+-1
+3
+numerator1
+-1
+3
+numerator0
+-1
+3
+denominator9
+-1
+3
+denominator8
+-1
+3
+denominator7
+-1
+3
+denominator6
+-1
+3
+denominator5
+-1
+3
+denominator4
+-1
+3
+denominator3
+-1
+3
+denominator24
+-1
+3
+denominator23
+-1
+3
+denominator22
+-1
+3
+denominator21
+-1
+3
+denominator20
+-1
+3
+denominator2
+-1
+3
+denominator19
+-1
+3
+denominator18
+-1
+3
+denominator17
+-1
+3
+denominator16
+-1
+3
+denominator15
+-1
+3
+denominator14
+-1
+3
+denominator13
+-1
+3
+denominator12
+-1
+3
+denominator11
+-1
+3
+denominator10
+-1
+3
+denominator1
+-1
+3
+denominator0
+-1
+3
+}
+# end
+# entity
+alt_u_div_s5f
+# storage
+db|demo.(7).cnf
+db|demo.(7).cnf
+# case_insensitive
+# source_file
+db|alt_u_div_s5f.tdf
+b1ea88f0fb757ed9c73c613312772435
+6
+# used_port {
+remainder9
+-1
+3
+remainder8
+-1
+3
+remainder7
+-1
+3
+remainder6
+-1
+3
+remainder5
+-1
+3
+remainder4
+-1
+3
+remainder3
+-1
+3
+remainder24
+-1
+3
+remainder23
+-1
+3
+remainder22
+-1
+3
+remainder21
+-1
+3
+remainder20
+-1
+3
+remainder2
+-1
+3
+remainder19
+-1
+3
+remainder18
+-1
+3
+remainder17
+-1
+3
+remainder16
+-1
+3
+remainder15
+-1
+3
+remainder14
+-1
+3
+remainder13
+-1
+3
+remainder12
+-1
+3
+remainder11
+-1
+3
+remainder10
+-1
+3
+remainder1
+-1
+3
+remainder0
+-1
+3
+quotient9
+-1
+3
+quotient8
+-1
+3
+quotient7
+-1
+3
+quotient6
+-1
+3
+quotient5
+-1
+3
+quotient4
+-1
+3
+quotient3
+-1
+3
+quotient24
+-1
+3
+quotient23
+-1
+3
+quotient22
+-1
+3
+quotient21
+-1
+3
+quotient20
+-1
+3
+quotient2
+-1
+3
+quotient19
+-1
+3
+quotient18
+-1
+3
+quotient17
+-1
+3
+quotient16
+-1
+3
+quotient15
+-1
+3
+quotient14
+-1
+3
+quotient13
+-1
+3
+quotient12
+-1
+3
+quotient11
+-1
+3
+quotient10
+-1
+3
+quotient1
+-1
+3
+quotient0
+-1
+3
+numerator9
+-1
+3
+numerator8
+-1
+3
+numerator7
+-1
+3
+numerator6
+-1
+3
+numerator5
+-1
+3
+numerator4
+-1
+3
+numerator3
+-1
+3
+numerator24
+-1
+3
+numerator23
+-1
+3
+numerator22
+-1
+3
+numerator21
+-1
+3
+numerator20
+-1
+3
+numerator2
+-1
+3
+numerator19
+-1
+3
+numerator18
+-1
+3
+numerator17
+-1
+3
+numerator16
+-1
+3
+numerator15
+-1
+3
+numerator14
+-1
+3
+numerator13
+-1
+3
+numerator12
+-1
+3
+numerator11
+-1
+3
+numerator10
+-1
+3
+numerator1
+-1
+3
+numerator0
+-1
+3
+denominator9
+-1
+3
+denominator8
+-1
+3
+denominator7
+-1
+3
+denominator6
+-1
+3
+denominator5
+-1
+3
+denominator4
+-1
+3
+denominator3
+-1
+3
+denominator24
+-1
+3
+denominator23
+-1
+3
+denominator22
+-1
+3
+denominator21
+-1
+3
+denominator20
+-1
+3
+denominator2
+-1
+3
+denominator19
+-1
+3
+denominator18
+-1
+3
+denominator17
+-1
+3
+denominator16
+-1
+3
+denominator15
+-1
+3
+denominator14
+-1
+3
+denominator13
+-1
+3
+denominator12
+-1
+3
+denominator11
+-1
+3
+denominator10
+-1
+3
+denominator1
+-1
+3
+denominator0
+-1
+3
+}
+# end
+# entity
+add_sub_lkc
+# storage
+db|demo.(8).cnf
+db|demo.(8).cnf
+# case_insensitive
+# source_file
+db|add_sub_lkc.tdf
+dff365fff4226483a2bd5d2d69e9bd8
+6
+# used_port {
+result0
+-1
+3
+datab0
+-1
+3
+dataa0
+-1
+3
+cout
+-1
+3
+}
+# end
+# entity
+add_sub_mkc
+# storage
+db|demo.(9).cnf
+db|demo.(9).cnf
+# case_insensitive
+# source_file
+db|add_sub_mkc.tdf
+384b2712191728c551b1d89cf529a
+6
+# used_port {
+result1
+-1
+3
+result0
+-1
+3
+datab1
+-1
+3
+datab0
+-1
+3
+dataa1
+-1
+3
+dataa0
+-1
+3
+cout
+-1
+3
+}
+# end
+# entity
+demo_top
+# storage
+db|demo.(0).cnf
+db|demo.(0).cnf
+# case_insensitive
+# source_file
+..|src|demo_top.bdf
+c22dfdad9f2d8e20a668d889fe5d3c4a
+24
+# hierarchies {
+|
+}
+# end
+# entity
+demo
+# storage
+db|demo.(1).cnf
+db|demo.(1).cnf
+# logic_option {
+AUTO_RAM_RECOGNITION
+ON
+}
+# case_insensitive
+# source_file
+..|src|demo.vhd
+2c4544981ae8a5224aef3f7cd1beb45d
+4
+# internal_option {
+AUTO_RESOURCE_SHARING
+OFF
+}
+# include_file {
+..|src|demo_pkg.vhd
+a44cae9584386640bca224889972f511
+}
+# hierarchies {
+demo:inst
+}
+# end
+# entity
+lpm_divide
+# storage
+db|demo.(10).cnf
+db|demo.(10).cnf
+# case_insensitive
+# source_file
+|opt|quartus|libraries|megafunctions|lpm_divide.tdf
+5dc73d7964222e4a26f9c0fe35122d62
+6
+# user_parameter {
+LPM_WIDTHN
+8
+PARAMETER_UNKNOWN
+USR
+LPM_WIDTHD
+8
+PARAMETER_UNKNOWN
+USR
+LPM_NREPRESENTATION
+UNSIGNED
+PARAMETER_UNKNOWN
+USR
+LPM_DREPRESENTATION
+UNSIGNED
+PARAMETER_UNKNOWN
+USR
+LPM_PIPELINE
+0
+PARAMETER_UNKNOWN
+DEF
+LPM_REMAINDERPOSITIVE
+TRUE
+PARAMETER_UNKNOWN
+DEF
+MAXIMIZE_SPEED
+5
+PARAMETER_UNKNOWN
+DEF
+CBXI_PARAMETER
+lpm_divide_85m
+PARAMETER_UNKNOWN
+USR
+CARRY_CHAIN
+MANUAL
+PARAMETER_UNKNOWN
+USR
+OPTIMIZE_FOR_SPEED
+5
+PARAMETER_UNKNOWN
+USR
+AUTO_CARRY_CHAINS
+ON
+AUTO_CARRY
+USR
+IGNORE_CARRY_BUFFERS
+OFF
+IGNORE_CARRY
+USR
+AUTO_CASCADE_CHAINS
+ON
+AUTO_CASCADE
+USR
+IGNORE_CASCADE_BUFFERS
+OFF
+IGNORE_CASCADE
+USR
+}
+# used_port {
+remain6
+-1
+3
+remain5
+-1
+3
+remain4
+-1
+3
+remain3
+-1
+3
+remain2
+-1
+3
+remain1
+-1
+3
+remain0
+-1
+3
+numer7
+-1
+3
+numer6
+-1
+3
+numer5
+-1
+3
+numer4
+-1
+3
+numer3
+-1
+3
+numer2
+-1
+3
+numer1
+-1
+3
+numer0
+-1
+3
+denom7
+-1
+1
+denom4
+-1
+1
+denom3
+-1
+1
+denom1
+-1
+1
+denom0
+-1
+1
+denom6
+-1
+2
+denom5
+-1
+2
+denom2
+-1
+2
+}
+# include_file {
+|opt|quartus|libraries|megafunctions|aglobal70.inc
+6e323611d63cddcc66b682e7ab39d4b7
+|opt|quartus|libraries|megafunctions|sign_div_unsign.inc
+c1e17922387cb5d0c88d7fb673544bb4
+|opt|quartus|libraries|megafunctions|abs_divider.inc
+cdfefd53e136b3a8e541899b82db37d
+}
+# end
+# entity
+lpm_divide_85m
+# storage
+db|demo.(11).cnf
+db|demo.(11).cnf
+# case_insensitive
+# source_file
+db|lpm_divide_85m.tdf
+8167d60745c46f8af3634c6389442e9
+6
+# used_port {
+remain7
+-1
+3
+remain6
+-1
+3
+remain5
+-1
+3
+remain4
+-1
+3
+remain3
+-1
+3
+remain2
+-1
+3
+remain1
+-1
+3
+remain0
+-1
+3
+numer7
+-1
+3
+numer6
+-1
+3
+numer5
+-1
+3
+numer4
+-1
+3
+numer3
+-1
+3
+numer2
+-1
+3
+numer1
+-1
+3
+numer0
+-1
+3
+denom7
+-1
+3
+denom6
+-1
+3
+denom5
+-1
+3
+denom4
+-1
+3
+denom3
+-1
+3
+denom2
+-1
+3
+denom1
+-1
+3
+denom0
+-1
+3
+}
+# end
+# entity
+sign_div_unsign_fkh
+# storage
+db|demo.(12).cnf
+db|demo.(12).cnf
+# case_insensitive
+# source_file
+db|sign_div_unsign_fkh.tdf
+561f2b42a8c48c36e255428b35be5c
+6
+# used_port {
+remainder7
+-1
+3
+remainder6
+-1
+3
+remainder5
+-1
+3
+remainder4
+-1
+3
+remainder3
+-1
+3
+remainder2
+-1
+3
+remainder1
+-1
+3
+remainder0
+-1
+3
+quotient7
+-1
+3
+quotient6
+-1
+3
+quotient5
+-1
+3
+quotient4
+-1
+3
+quotient3
+-1
+3
+quotient2
+-1
+3
+quotient1
+-1
+3
+quotient0
+-1
+3
+numerator7
+-1
+3
+numerator6
+-1
+3
+numerator5
+-1
+3
+numerator4
+-1
+3
+numerator3
+-1
+3
+numerator2
+-1
+3
+numerator1
+-1
+3
+numerator0
+-1
+3
+denominator7
+-1
+3
+denominator6
+-1
+3
+denominator5
+-1
+3
+denominator4
+-1
+3
+denominator3
+-1
+3
+denominator2
+-1
+3
+denominator1
+-1
+3
+denominator0
+-1
+3
+}
+# end
+# entity
+alt_u_div_00f
+# storage
+db|demo.(13).cnf
+db|demo.(13).cnf
+# case_insensitive
+# source_file
+db|alt_u_div_00f.tdf
+aeb2a5ddf83ea766ce72af370489f3
+6
+# used_port {
+remainder7
+-1
+3
+remainder6
+-1
+3
+remainder5
+-1
+3
+remainder4
+-1
+3
+remainder3
+-1
+3
+remainder2
+-1
+3
+remainder1
+-1
+3
+remainder0
+-1
+3
+quotient7
+-1
+3
+quotient6
+-1
+3
+quotient5
+-1
+3
+quotient4
+-1
+3
+quotient3
+-1
+3
+quotient2
+-1
+3
+quotient1
+-1
+3
+quotient0
+-1
+3
+numerator7
+-1
+3
+numerator6
+-1
+3
+numerator5
+-1
+3
+numerator4
+-1
+3
+numerator3
+-1
+3
+numerator2
+-1
+3
+numerator1
+-1
+3
+numerator0
+-1
+3
+denominator7
+-1
+3
+denominator6
+-1
+3
+denominator5
+-1
+3
+denominator4
+-1
+3
+denominator3
+-1
+3
+denominator2
+-1
+3
+denominator1
+-1
+3
+denominator0
+-1
+3
+}
+# end
+# complete
+\r
\ No newline at end of file
--- /dev/null
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 30 19:52:35 2009 " "Info: Processing started: Mon Mar 30 19:52:35 2009" { } { } 0 0 "Processing started: %1!s!" 0 0} } { } 4 0 "Running %2!s! %1!s!" 0 0}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off demo -c demo " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off demo -c demo" { } { } 0 0 "Command: %1!s!" 0 0}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../src/demo_pkg.vhd 1 0 " "Info: Found 1 design units, including 0 entities, in source file ../src/demo_pkg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 demo_pkg " "Info: Found design unit 1: demo_pkg" { } { { "../src/demo_pkg.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo_pkg.vhd" 4 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../src/demo.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../src/demo.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 demo-behav " "Info: Found design unit 1: demo-behav" { } { { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 16 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 demo " "Info: Found entity 1: demo" { } { { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 6 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../src/pll.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../src/pll.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pll-SYN " "Info: Found design unit 1: pll-SYN" { } { { "../src/pll.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/pll.vhd" 51 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 pll " "Info: Found entity 1: pll" { } { { "../src/pll.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/pll.vhd" 42 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../src/demo_top.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../src/demo_top.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 demo_top " "Info: Found entity 1: demo_top" { } { { "../src/demo_top.bdf" "" { Schematic "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo_top.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
+{ "Info" "ISGN_START_ELABORATION_TOP" "demo_top " "Info: Elaborating entity \"demo_top\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "demo demo:inst " "Info: Elaborating entity \"demo\" for hierarchy \"demo:inst\"" { } { { "../src/demo_top.bdf" "inst" { Schematic "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo_top.bdf" { { 120 696 856 216 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll pll:inst1 " "Info: Elaborating entity \"pll\" for hierarchy \"pll:inst1\"" { } { { "../src/demo_top.bdf" "inst1" { Schematic "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo_top.bdf" { { 56 352 592 216 "inst1" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/opt/quartus/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file /opt/quartus/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" { } { { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 454 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll pll:inst1\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"pll:inst1\|altpll:altpll_component\"" { } { { "../src/pll.vhd" "altpll_component" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/pll.vhd" 130 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
+{ "Info" "ISGN_ELABORATION_HEADER" "pll:inst1\|altpll:altpll_component " "Info: Elaborated megafunction instantiation \"pll:inst1\|altpll:altpll_component\"" { } { { "../src/pll.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/pll.vhd" 130 0 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/opt/quartus/libraries/megafunctions/lpm_divide.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file /opt/quartus/libraries/megafunctions/lpm_divide.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide " "Info: Found entity 1: lpm_divide" { } { { "lpm_divide.tdf" "" { Text "/opt/quartus/libraries/megafunctions/lpm_divide.tdf" 118 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
+{ "Info" "ISGN_ELABORATION_HEADER" "demo:inst\|lpm_divide:Mod0 " "Info: Elaborated megafunction instantiation \"demo:inst\|lpm_divide:Mod0\"" { } { { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 86 -1 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_85m.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_85m.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_85m " "Info: Found entity 1: lpm_divide_85m" { } { { "db/lpm_divide_85m.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/lpm_divide_85m.tdf" 24 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_fkh.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_fkh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_fkh " "Info: Found entity 1: sign_div_unsign_fkh" { } { { "db/sign_div_unsign_fkh.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/sign_div_unsign_fkh.tdf" 24 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_00f.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_00f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_00f " "Info: Found entity 1: alt_u_div_00f" { } { { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 26 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_lkc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_lkc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_lkc " "Info: Found entity 1: add_sub_lkc" { } { { "db/add_sub_lkc.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/add_sub_lkc.tdf" 22 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_mkc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_mkc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_mkc " "Info: Found entity 1: add_sub_mkc" { } { { "db/add_sub_mkc.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/add_sub_mkc.tdf" 22 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
+{ "Info" "ISCL_SCL_WANNA_REM_USR_WIRE" "" "Info: Found the following redundant logic cells in design" { { "Info" "ISCL_SCL_CELL_NAME" "demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[0\]~34 " "Info: Logic cell \"demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[0\]~34\"" { } { { "db/alt_u_div_00f.tdf" "add_sub_7_result_int\[0\]~34" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 62 22 0 } } } 0 0 "Logic cell \"%1!s!\"" 0 0} } { } 0 0 "Found the following redundant logic cells in design" 0 0}
+{ "Info" "ISCL_SCL_TM_SUMMARY" "84 " "Info: Implemented 84 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "73 " "Info: Implemented 73 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_PLLS" "1 " "Info: Implemented 1 ClockLock PLLs" { } { } 0 0 "Implemented %1!d! ClockLock PLLs" 0 0} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 30 19:52:38 2009 " "Info: Processing ended: Mon Mar 30 19:52:38 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
--- /dev/null
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Partition Merge Quartus II " "Info: Running Quartus II Partition Merge" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 30 19:52:41 2009 " "Info: Processing started: Mon Mar 30 19:52:41 2009" { } { } 0 0 "Processing started: %1!s!" 0 0} } { } 4 0 "Running %2!s! %1!s!" 0 0}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_cdb --read_settings_files=off --write_settings_files=off demo -c demo --merge=on " "Info: Command: quartus_cdb --read_settings_files=off --write_settings_files=off demo -c demo --merge=on" { } { } 0 0 "Command: %1!s!" 0 0}
+{ "Info" "IAMERGE_PARTITION_SOURCE_SOURCE" "Top " "Info: Using synthesis netlist for partition \"Top\"" { } { } 0 0 "Using synthesis netlist for partition \"%1!s!\"" 0 0}
+{ "Info" "IAMERGE_ATOM_BLACKBOX_RESOLVED" "1 1 " "Info: Netlist merging resolved 1 partition(s) out of the 1 partition(s) found" { } { } 0 0 "Netlist merging resolved %1!d! partition(s) out of the %2!d! partition(s) found" 0 0}
+{ "Info" "IQEXE_ERROR_COUNT" "Partition Merge 0 s 0 s Quartus II " "Info: Quartus II Partition Merge was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 30 19:52:42 2009 " "Info: Processing ended: Mon Mar 30 19:52:42 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
--- /dev/null
+|
+c22dfdad9f2d8e20a668d889fe5d3c4a
+demo:inst
+2c4544981ae8a5224aef3f7cd1beb45d
+pll:inst1
+1866c9e27a803e38a86b84bedcb78419
+pll:inst1|altpll:altpll_component
+9948948e9c204c786e29bcceb2be7f
--- /dev/null
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 30 19:53:31 2009 " "Info: Processing started: Mon Mar 30 19:53:31 2009" { } { } 0 0 "Processing started: %1!s!" 0 0} } { } 4 0 "Running %2!s! %1!s!" 0 0}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off demo -c demo --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off demo -c demo --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0}
+{ "Warning" "WTAN_USE_ENABLE_CLOCK_LATENCY_FOR_PLL" "" "Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" { } { } 0 0 "Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" 0 0}
+{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" { } { } 0 0 "Found timing assignments -- calculating delays" 0 0}
+{ "Info" "ITDB_FULL_SLACK_RESULT" "pll:inst1\|altpll:altpll_component\|_clk0 register demo:inst\|counter\[3\] register demo:inst\|counter\[1\] 3.604 ns " "Info: Slack time is 3.604 ns for clock \"pll:inst1\|altpll:altpll_component\|_clk0\" between source register \"demo:inst\|counter\[3\]\" and destination register \"demo:inst\|counter\[1\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "156.35 MHz 6.396 ns " "Info: Fmax is 156.35 MHz (period= 6.396 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "9.786 ns + Largest register register " "Info: + Largest register to register requirement is 9.786 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "10.000 ns + " "Info: + Setup relationship between source and destination is 10.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 7.622 ns " "Info: + Latch edge is 7.622 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination pll:inst1\|altpll:altpll_component\|_clk0 10.000 ns -2.378 ns 50 " "Info: Clock period of Destination clock \"pll:inst1\|altpll:altpll_component\|_clk0\" is 10.000 ns with offset of -2.378 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.378 ns " "Info: - Launch edge is -2.378 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source pll:inst1\|altpll:altpll_component\|_clk0 10.000 ns -2.378 ns 50 " "Info: Clock period of Source clock \"pll:inst1\|altpll:altpll_component\|_clk0\" is 10.000 ns with offset of -2.378 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll:inst1\|altpll:altpll_component\|_clk0 destination 2.650 ns + Shortest register " "Info: + Shortest clock path from clock \"pll:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.650 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "" { pll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns pll:inst1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'pll:inst1\|altpll:altpll_component\|_clk0~clkctrl'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "1.091 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.022 ns) + CELL(0.537 ns) 2.650 ns demo:inst\|counter\[1\] 3 REG LCFF_X55_Y31_N1 3 " "Info: 3: + IC(1.022 ns) + CELL(0.537 ns) = 2.650 ns; Loc. = LCFF_X55_Y31_N1; Fanout = 3; REG Node = 'demo:inst\|counter\[1\]'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "1.559 ns" { pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[1] } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 82 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.26 % ) " "Info: Total cell delay = 0.537 ns ( 20.26 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.113 ns ( 79.74 % ) " "Info: Total interconnect delay = 2.113 ns ( 79.74 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[1] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[1] } { 0.000ns 1.091ns 1.022ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll:inst1\|altpll:altpll_component\|_clk0 source 2.650 ns - Longest register " "Info: - Longest clock path from clock \"pll:inst1\|altpll:altpll_component\|_clk0\" to source register is 2.650 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "" { pll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns pll:inst1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'pll:inst1\|altpll:altpll_component\|_clk0~clkctrl'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "1.091 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.022 ns) + CELL(0.537 ns) 2.650 ns demo:inst\|counter\[3\] 3 REG LCFF_X57_Y31_N31 3 " "Info: 3: + IC(1.022 ns) + CELL(0.537 ns) = 2.650 ns; Loc. = LCFF_X57_Y31_N31; Fanout = 3; REG Node = 'demo:inst\|counter\[3\]'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "1.559 ns" { pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[3] } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 82 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.26 % ) " "Info: Total cell delay = 0.537 ns ( 20.26 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.113 ns ( 79.74 % ) " "Info: Total interconnect delay = 2.113 ns ( 79.74 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[3] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[3] } { 0.000ns 1.091ns 1.022ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[1] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[1] } { 0.000ns 1.091ns 1.022ns } { 0.000ns 0.000ns 0.537ns } "" } } { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[3] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[3] } { 0.000ns 1.091ns 1.022ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" { } { { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 82 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns - " "Info: - Micro setup delay of destination is -0.036 ns" { } { { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 82 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[1] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[1] } { 0.000ns 1.091ns 1.022ns } { 0.000ns 0.000ns 0.537ns } "" } } { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[3] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[3] } { 0.000ns 1.091ns 1.022ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.182 ns - Longest register register " "Info: - Longest register to register delay is 6.182 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns demo:inst\|counter\[3\] 1 REG LCFF_X57_Y31_N31 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X57_Y31_N31; Fanout = 3; REG Node = 'demo:inst\|counter\[3\]'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "" { demo:inst|counter[3] } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 82 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.741 ns) + CELL(0.414 ns) 1.155 ns demo:inst\|Add0~101 2 COMB LCCOMB_X55_Y31_N18 2 " "Info: 2: + IC(0.741 ns) + CELL(0.414 ns) = 1.155 ns; Loc. = LCCOMB_X55_Y31_N18; Fanout = 2; COMB Node = 'demo:inst\|Add0~101'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "1.155 ns" { demo:inst|counter[3] demo:inst|Add0~101 } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 86 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 1.565 ns demo:inst\|Add0~102 3 COMB LCCOMB_X55_Y31_N20 3 " "Info: 3: + IC(0.000 ns) + CELL(0.410 ns) = 1.565 ns; Loc. = LCCOMB_X55_Y31_N20; Fanout = 3; COMB Node = 'demo:inst\|Add0~102'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.410 ns" { demo:inst|Add0~101 demo:inst|Add0~102 } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 86 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.277 ns) + CELL(0.414 ns) 2.256 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[3\]~19 4 COMB LCCOMB_X55_Y31_N4 2 " "Info: 4: + IC(0.277 ns) + CELL(0.414 ns) = 2.256 ns; Loc. = LCCOMB_X55_Y31_N4; Fanout = 2; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[3\]~19'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.691 ns" { demo:inst|Add0~102 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[3]~19 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 57 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.327 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[4\]~21 5 COMB LCCOMB_X55_Y31_N6 2 " "Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 2.327 ns; Loc. = LCCOMB_X55_Y31_N6; Fanout = 2; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[4\]~21'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.071 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[3]~19 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[4]~21 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 57 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.398 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[5\]~23 6 COMB LCCOMB_X55_Y31_N8 2 " "Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 2.398 ns; Loc. = LCCOMB_X55_Y31_N8; Fanout = 2; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[5\]~23'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.071 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[4]~21 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[5]~23 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 57 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.469 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[6\]~25 7 COMB LCCOMB_X55_Y31_N10 1 " "Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 2.469 ns; Loc. = LCCOMB_X55_Y31_N10; Fanout = 1; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[6\]~25'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.071 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[5]~23 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[6]~25 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 57 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 2.879 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[7\]~26 8 COMB LCCOMB_X55_Y31_N12 14 " "Info: 8: + IC(0.000 ns) + CELL(0.410 ns) = 2.879 ns; Loc. = LCCOMB_X55_Y31_N12; Fanout = 14; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[7\]~26'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.410 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[6]~25 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[7]~26 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 57 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.705 ns) + CELL(0.150 ns) 3.734 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|StageOut\[49\]~22 9 COMB LCCOMB_X57_Y31_N10 2 " "Info: 9: + IC(0.705 ns) + CELL(0.150 ns) = 3.734 ns; Loc. = LCCOMB_X57_Y31_N10; Fanout = 2; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|StageOut\[49\]~22'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.855 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[7]~26 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[49]~22 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 79 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.263 ns) + CELL(0.504 ns) 4.501 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[2\]~21 10 COMB LCCOMB_X57_Y31_N14 2 " "Info: 10: + IC(0.263 ns) + CELL(0.504 ns) = 4.501 ns; Loc. = LCCOMB_X57_Y31_N14; Fanout = 2; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[2\]~21'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.767 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[49]~22 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[2]~21 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 62 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.572 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[3\]~23 11 COMB LCCOMB_X57_Y31_N16 2 " "Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 4.572 ns; Loc. = LCCOMB_X57_Y31_N16; Fanout = 2; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[3\]~23'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.071 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[2]~21 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[3]~23 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 62 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.643 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[4\]~25 12 COMB LCCOMB_X57_Y31_N18 2 " "Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 4.643 ns; Loc. = LCCOMB_X57_Y31_N18; Fanout = 2; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[4\]~25'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.071 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[3]~23 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[4]~25 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 62 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.714 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[5\]~27 13 COMB LCCOMB_X57_Y31_N20 2 " "Info: 13: + IC(0.000 ns) + CELL(0.071 ns) = 4.714 ns; Loc. = LCCOMB_X57_Y31_N20; Fanout = 2; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[5\]~27'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.071 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[4]~25 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[5]~27 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 62 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.785 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[6\]~29 14 COMB LCCOMB_X57_Y31_N22 1 " "Info: 14: + IC(0.000 ns) + CELL(0.071 ns) = 4.785 ns; Loc. = LCCOMB_X57_Y31_N22; Fanout = 1; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[6\]~29'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.071 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[5]~27 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[6]~29 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 62 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.856 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[7\]~31 15 COMB LCCOMB_X57_Y31_N24 1 " "Info: 15: + IC(0.000 ns) + CELL(0.071 ns) = 4.856 ns; Loc. = LCCOMB_X57_Y31_N24; Fanout = 1; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[7\]~31'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.071 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[6]~29 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[7]~31 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 62 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 5.266 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[8\]~32 16 COMB LCCOMB_X57_Y31_N26 7 " "Info: 16: + IC(0.000 ns) + CELL(0.410 ns) = 5.266 ns; Loc. = LCCOMB_X57_Y31_N26; Fanout = 7; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[8\]~32'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.410 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[7]~31 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[8]~32 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 62 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.682 ns) + CELL(0.150 ns) 6.098 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|StageOut\[57\]~636 17 COMB LCCOMB_X55_Y31_N0 1 " "Info: 17: + IC(0.682 ns) + CELL(0.150 ns) = 6.098 ns; Loc. = LCCOMB_X55_Y31_N0; Fanout = 1; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|StageOut\[57\]~636'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.832 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[8]~32 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[57]~636 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 79 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 6.182 ns demo:inst\|counter\[1\] 18 REG LCFF_X55_Y31_N1 3 " "Info: 18: + IC(0.000 ns) + CELL(0.084 ns) = 6.182 ns; Loc. = LCFF_X55_Y31_N1; Fanout = 3; REG Node = 'demo:inst\|counter\[1\]'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.084 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[57]~636 demo:inst|counter[1] } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 82 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.514 ns ( 56.84 % ) " "Info: Total cell delay = 3.514 ns ( 56.84 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.668 ns ( 43.16 % ) " "Info: Total interconnect delay = 2.668 ns ( 43.16 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "6.182 ns" { demo:inst|counter[3] demo:inst|Add0~101 demo:inst|Add0~102 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[3]~19 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[4]~21 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[5]~23 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[6]~25 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[7]~26 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[49]~22 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[2]~21 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[3]~23 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[4]~25 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[5]~27 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[6]~29 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[7]~31 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[8]~32 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[57]~636 demo:inst|counter[1] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "6.182 ns" { demo:inst|counter[3] demo:inst|Add0~101 demo:inst|Add0~102 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[3]~19 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[4]~21 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[5]~23 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[6]~25 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[7]~26 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[49]~22 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[2]~21 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[3]~23 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[4]~25 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[5]~27 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[6]~29 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[7]~31 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[8]~32 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[57]~636 demo:inst|counter[1] } { 0.000ns 0.741ns 0.000ns 0.277ns 0.000ns 0.000ns 0.000ns 0.000ns 0.705ns 0.263ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.682ns 0.000ns } { 0.000ns 0.414ns 0.410ns 0.414ns 0.071ns 0.071ns 0.071ns 0.410ns 0.150ns 0.504ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.410ns 0.150ns 0.084ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[1] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[1] } { 0.000ns 1.091ns 1.022ns } { 0.000ns 0.000ns 0.537ns } "" } } { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[3] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[3] } { 0.000ns 1.091ns 1.022ns } { 0.000ns 0.000ns 0.537ns } "" } } { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "6.182 ns" { demo:inst|counter[3] demo:inst|Add0~101 demo:inst|Add0~102 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[3]~19 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[4]~21 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[5]~23 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[6]~25 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[7]~26 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[49]~22 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[2]~21 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[3]~23 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[4]~25 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[5]~27 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[6]~29 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[7]~31 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[8]~32 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[57]~636 demo:inst|counter[1] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "6.182 ns" { demo:inst|counter[3] demo:inst|Add0~101 demo:inst|Add0~102 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[3]~19 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[4]~21 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[5]~23 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[6]~25 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[7]~26 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[49]~22 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[2]~21 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[3]~23 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[4]~25 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[5]~27 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[6]~29 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[7]~31 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[8]~32 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[57]~636 demo:inst|counter[1] } { 0.000ns 0.741ns 0.000ns 0.277ns 0.000ns 0.000ns 0.000ns 0.000ns 0.705ns 0.263ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.682ns 0.000ns } { 0.000ns 0.414ns 0.410ns 0.414ns 0.071ns 0.071ns 0.071ns 0.410ns 0.150ns 0.504ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.410ns 0.150ns 0.084ns } "" } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
+{ "Info" "ITAN_NO_REG2REG_EXIST" "CLK " "Info: No valid register-to-register data paths exist for clock \"CLK\"" { } { } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
+{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "pll:inst1\|altpll:altpll_component\|_clk0 register demo:inst\|knightlight\[5\] register demo:inst\|knightlight\[5\] 391 ps " "Info: Minimum slack time is 391 ps for clock \"pll:inst1\|altpll:altpll_component\|_clk0\" between source register \"demo:inst\|knightlight\[5\]\" and destination register \"demo:inst\|knightlight\[5\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.407 ns + Shortest register register " "Info: + Shortest register to register delay is 0.407 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns demo:inst\|knightlight\[5\] 1 REG LCFF_X33_Y27_N29 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X33_Y27_N29; Fanout = 5; REG Node = 'demo:inst\|knightlight\[5\]'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "" { demo:inst|knightlight[5] } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 40 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.323 ns) 0.323 ns demo:inst\|knightlight~1268 2 COMB LCCOMB_X33_Y27_N28 1 " "Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X33_Y27_N28; Fanout = 1; COMB Node = 'demo:inst\|knightlight~1268'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.323 ns" { demo:inst|knightlight[5] demo:inst|knightlight~1268 } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.407 ns demo:inst\|knightlight\[5\] 3 REG LCFF_X33_Y27_N29 5 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X33_Y27_N29; Fanout = 5; REG Node = 'demo:inst\|knightlight\[5\]'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.084 ns" { demo:inst|knightlight~1268 demo:inst|knightlight[5] } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 40 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.407 ns ( 100.00 % ) " "Info: Total cell delay = 0.407 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.407 ns" { demo:inst|knightlight[5] demo:inst|knightlight~1268 demo:inst|knightlight[5] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "0.407 ns" { demo:inst|knightlight[5] demo:inst|knightlight~1268 demo:inst|knightlight[5] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.323ns 0.084ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.016 ns - Smallest register register " "Info: - Smallest register to register requirement is 0.016 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -2.378 ns " "Info: + Latch edge is -2.378 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination pll:inst1\|altpll:altpll_component\|_clk0 10.000 ns -2.378 ns 50 " "Info: Clock period of Destination clock \"pll:inst1\|altpll:altpll_component\|_clk0\" is 10.000 ns with offset of -2.378 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.378 ns " "Info: - Launch edge is -2.378 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source pll:inst1\|altpll:altpll_component\|_clk0 10.000 ns -2.378 ns 50 " "Info: Clock period of Source clock \"pll:inst1\|altpll:altpll_component\|_clk0\" is 10.000 ns with offset of -2.378 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} } { } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll:inst1\|altpll:altpll_component\|_clk0 destination 2.602 ns + Longest register " "Info: + Longest clock path from clock \"pll:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.602 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "" { pll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns pll:inst1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'pll:inst1\|altpll:altpll_component\|_clk0~clkctrl'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "1.091 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.974 ns) + CELL(0.537 ns) 2.602 ns demo:inst\|knightlight\[5\] 3 REG LCFF_X33_Y27_N29 5 " "Info: 3: + IC(0.974 ns) + CELL(0.537 ns) = 2.602 ns; Loc. = LCFF_X33_Y27_N29; Fanout = 5; REG Node = 'demo:inst\|knightlight\[5\]'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "1.511 ns" { pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[5] } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 40 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.64 % ) " "Info: Total cell delay = 0.537 ns ( 20.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.065 ns ( 79.36 % ) " "Info: Total interconnect delay = 2.065 ns ( 79.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[5] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[5] } { 0.000ns 1.091ns 0.974ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll:inst1\|altpll:altpll_component\|_clk0 source 2.602 ns - Shortest register " "Info: - Shortest clock path from clock \"pll:inst1\|altpll:altpll_component\|_clk0\" to source register is 2.602 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "" { pll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns pll:inst1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'pll:inst1\|altpll:altpll_component\|_clk0~clkctrl'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "1.091 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.974 ns) + CELL(0.537 ns) 2.602 ns demo:inst\|knightlight\[5\] 3 REG LCFF_X33_Y27_N29 5 " "Info: 3: + IC(0.974 ns) + CELL(0.537 ns) = 2.602 ns; Loc. = LCFF_X33_Y27_N29; Fanout = 5; REG Node = 'demo:inst\|knightlight\[5\]'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "1.511 ns" { pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[5] } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 40 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.64 % ) " "Info: Total cell delay = 0.537 ns ( 20.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.065 ns ( 79.36 % ) " "Info: Total interconnect delay = 2.065 ns ( 79.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[5] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[5] } { 0.000ns 1.091ns 0.974ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[5] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[5] } { 0.000ns 1.091ns 0.974ns } { 0.000ns 0.000ns 0.537ns } "" } } { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[5] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[5] } { 0.000ns 1.091ns 0.974ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" { } { { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 40 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" { } { { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 40 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[5] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[5] } { 0.000ns 1.091ns 0.974ns } { 0.000ns 0.000ns 0.537ns } "" } } { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[5] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[5] } { 0.000ns 1.091ns 0.974ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.407 ns" { demo:inst|knightlight[5] demo:inst|knightlight~1268 demo:inst|knightlight[5] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "0.407 ns" { demo:inst|knightlight[5] demo:inst|knightlight~1268 demo:inst|knightlight[5] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.323ns 0.084ns } "" } } { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[5] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[5] } { 0.000ns 1.091ns 0.974ns } { 0.000ns 0.000ns 0.537ns } "" } } { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[5] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[5] } { 0.000ns 1.091ns 0.974ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
+{ "Info" "ITDB_TSU_RESULT" "demo:inst\|knightlight\[7\] RESET CLK 7.774 ns register " "Info: tsu for register \"demo:inst\|knightlight\[7\]\" (data pin = \"RESET\", clock pin = \"CLK\") is 7.774 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.034 ns + Longest pin register " "Info: + Longest pin to register delay is 8.034 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.850 ns) 0.850 ns RESET 1 PIN PIN_B3 16 " "Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_B3; Fanout = 16; PIN Node = 'RESET'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "" { RESET } "NODE_NAME" } } { "../src/demo_top.bdf" "" { Schematic "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo_top.bdf" { { 296 416 584 312 "RESET" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.674 ns) + CELL(0.510 ns) 8.034 ns demo:inst\|knightlight\[7\] 2 REG LCFF_X33_Y27_N15 4 " "Info: 2: + IC(6.674 ns) + CELL(0.510 ns) = 8.034 ns; Loc. = LCFF_X33_Y27_N15; Fanout = 4; REG Node = 'demo:inst\|knightlight\[7\]'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "7.184 ns" { RESET demo:inst|knightlight[7] } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 40 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.360 ns ( 16.93 % ) " "Info: Total cell delay = 1.360 ns ( 16.93 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.674 ns ( 83.07 % ) " "Info: Total interconnect delay = 6.674 ns ( 83.07 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "8.034 ns" { RESET demo:inst|knightlight[7] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "8.034 ns" { RESET RESET~combout demo:inst|knightlight[7] } { 0.000ns 0.000ns 6.674ns } { 0.000ns 0.850ns 0.510ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" { } { { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 40 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_PLL_OFFSET" "CLK pll:inst1\|altpll:altpll_component\|_clk0 -2.378 ns - " "Info: - Offset between input clock \"CLK\" and output clock \"pll:inst1\|altpll:altpll_component\|_clk0\" is -2.378 ns" { } { { "../src/demo_top.bdf" "" { Schematic "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo_top.bdf" { { 56 136 304 72 "CLK" "" } } } } { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } } } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll:inst1\|altpll:altpll_component\|_clk0 destination 2.602 ns - Shortest register " "Info: - Shortest clock path from clock \"pll:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.602 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "" { pll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns pll:inst1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'pll:inst1\|altpll:altpll_component\|_clk0~clkctrl'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "1.091 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.974 ns) + CELL(0.537 ns) 2.602 ns demo:inst\|knightlight\[7\] 3 REG LCFF_X33_Y27_N15 4 " "Info: 3: + IC(0.974 ns) + CELL(0.537 ns) = 2.602 ns; Loc. = LCFF_X33_Y27_N15; Fanout = 4; REG Node = 'demo:inst\|knightlight\[7\]'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "1.511 ns" { pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[7] } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 40 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.64 % ) " "Info: Total cell delay = 0.537 ns ( 20.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.065 ns ( 79.36 % ) " "Info: Total interconnect delay = 2.065 ns ( 79.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[7] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[7] } { 0.000ns 1.091ns 0.974ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "8.034 ns" { RESET demo:inst|knightlight[7] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "8.034 ns" { RESET RESET~combout demo:inst|knightlight[7] } { 0.000ns 0.000ns 6.674ns } { 0.000ns 0.850ns 0.510ns } "" } } { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[7] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[7] } { 0.000ns 1.091ns 0.974ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
+{ "Info" "ITDB_FULL_TCO_RESULT" "CLK LEDS\[0\] demo:inst\|knightlight\[0\] 9.507 ns register " "Info: tco from clock \"CLK\" to destination pin \"LEDS\[0\]\" through register \"demo:inst\|knightlight\[0\]\" is 9.507 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "CLK pll:inst1\|altpll:altpll_component\|_clk0 -2.378 ns + " "Info: + Offset between input clock \"CLK\" and output clock \"pll:inst1\|altpll:altpll_component\|_clk0\" is -2.378 ns" { } { { "../src/demo_top.bdf" "" { Schematic "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo_top.bdf" { { 56 136 304 72 "CLK" "" } } } } { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } } } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll:inst1\|altpll:altpll_component\|_clk0 source 2.648 ns + Longest register " "Info: + Longest clock path from clock \"pll:inst1\|altpll:altpll_component\|_clk0\" to source register is 2.648 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "" { pll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns pll:inst1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'pll:inst1\|altpll:altpll_component\|_clk0~clkctrl'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "1.091 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.020 ns) + CELL(0.537 ns) 2.648 ns demo:inst\|knightlight\[0\] 3 REG LCFF_X54_Y31_N19 4 " "Info: 3: + IC(1.020 ns) + CELL(0.537 ns) = 2.648 ns; Loc. = LCFF_X54_Y31_N19; Fanout = 4; REG Node = 'demo:inst\|knightlight\[0\]'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "1.557 ns" { pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[0] } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 40 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.28 % ) " "Info: Total cell delay = 0.537 ns ( 20.28 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.111 ns ( 79.72 % ) " "Info: Total interconnect delay = 2.111 ns ( 79.72 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.648 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[0] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.648 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[0] } { 0.000ns 1.091ns 1.020ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" { } { { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 40 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.987 ns + Longest register pin " "Info: + Longest register to pin delay is 8.987 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns demo:inst\|knightlight\[0\] 1 REG LCFF_X54_Y31_N19 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X54_Y31_N19; Fanout = 4; REG Node = 'demo:inst\|knightlight\[0\]'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "" { demo:inst|knightlight[0] } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 40 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.365 ns) + CELL(2.622 ns) 8.987 ns LEDS\[0\] 2 PIN PIN_W5 0 " "Info: 2: + IC(6.365 ns) + CELL(2.622 ns) = 8.987 ns; Loc. = PIN_W5; Fanout = 0; PIN Node = 'LEDS\[0\]'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "8.987 ns" { demo:inst|knightlight[0] LEDS[0] } "NODE_NAME" } } { "../src/demo_top.bdf" "" { Schematic "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo_top.bdf" { { 144 896 1072 160 "LEDS\[7..0\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.622 ns ( 29.18 % ) " "Info: Total cell delay = 2.622 ns ( 29.18 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.365 ns ( 70.82 % ) " "Info: Total interconnect delay = 6.365 ns ( 70.82 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "8.987 ns" { demo:inst|knightlight[0] LEDS[0] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "8.987 ns" { demo:inst|knightlight[0] LEDS[0] } { 0.000ns 6.365ns } { 0.000ns 2.622ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.648 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[0] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.648 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[0] } { 0.000ns 1.091ns 1.020ns } { 0.000ns 0.000ns 0.537ns } "" } } { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "8.987 ns" { demo:inst|knightlight[0] LEDS[0] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "8.987 ns" { demo:inst|knightlight[0] LEDS[0] } { 0.000ns 6.365ns } { 0.000ns 2.622ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
+{ "Info" "ITDB_TH_RESULT" "demo:inst\|counter\[0\] RESET CLK -7.313 ns register " "Info: th for register \"demo:inst\|counter\[0\]\" (data pin = \"RESET\", clock pin = \"CLK\") is -7.313 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "CLK pll:inst1\|altpll:altpll_component\|_clk0 -2.378 ns + " "Info: + Offset between input clock \"CLK\" and output clock \"pll:inst1\|altpll:altpll_component\|_clk0\" is -2.378 ns" { } { { "../src/demo_top.bdf" "" { Schematic "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo_top.bdf" { { 56 136 304 72 "CLK" "" } } } } { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } } } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll:inst1\|altpll:altpll_component\|_clk0 destination 2.650 ns + Longest register " "Info: + Longest clock path from clock \"pll:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.650 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "" { pll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns pll:inst1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'pll:inst1\|altpll:altpll_component\|_clk0~clkctrl'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "1.091 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.022 ns) + CELL(0.537 ns) 2.650 ns demo:inst\|counter\[0\] 3 REG LCFF_X55_Y31_N29 5 " "Info: 3: + IC(1.022 ns) + CELL(0.537 ns) = 2.650 ns; Loc. = LCFF_X55_Y31_N29; Fanout = 5; REG Node = 'demo:inst\|counter\[0\]'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "1.559 ns" { pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[0] } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 82 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.26 % ) " "Info: Total cell delay = 0.537 ns ( 20.26 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.113 ns ( 79.74 % ) " "Info: Total interconnect delay = 2.113 ns ( 79.74 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[0] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[0] } { 0.000ns 1.091ns 1.022ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" { } { { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 82 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.851 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.851 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.850 ns) 0.850 ns RESET 1 PIN PIN_B3 16 " "Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_B3; Fanout = 16; PIN Node = 'RESET'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "" { RESET } "NODE_NAME" } } { "../src/demo_top.bdf" "" { Schematic "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo_top.bdf" { { 296 416 584 312 "RESET" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.491 ns) + CELL(0.510 ns) 7.851 ns demo:inst\|counter\[0\] 2 REG LCFF_X55_Y31_N29 5 " "Info: 2: + IC(6.491 ns) + CELL(0.510 ns) = 7.851 ns; Loc. = LCFF_X55_Y31_N29; Fanout = 5; REG Node = 'demo:inst\|counter\[0\]'" { } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "7.001 ns" { RESET demo:inst|counter[0] } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 82 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.360 ns ( 17.32 % ) " "Info: Total cell delay = 1.360 ns ( 17.32 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.491 ns ( 82.68 % ) " "Info: Total interconnect delay = 6.491 ns ( 82.68 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "7.851 ns" { RESET demo:inst|counter[0] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "7.851 ns" { RESET RESET~combout demo:inst|counter[0] } { 0.000ns 0.000ns 6.491ns } { 0.000ns 0.850ns 0.510ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[0] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[0] } { 0.000ns 1.091ns 1.022ns } { 0.000ns 0.000ns 0.537ns } "" } } { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "7.851 ns" { RESET demo:inst|counter[0] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "7.851 ns" { RESET RESET~combout demo:inst|counter[0] } { 0.000ns 0.000ns 6.491ns } { 0.000ns 0.850ns 0.510ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
+{ "Info" "ITAN_REQUIREMENTS_MET_SLOW" "" "Info: All timing requirements were met for slow timing model timing analysis. See Report window for more details." { } { } 0 0 "All timing requirements were met for slow timing model timing analysis. See Report window for more details." 0 0}
+{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 30 19:53:32 2009 " "Info: Processing ended: Mon Mar 30 19:53:32 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
--- /dev/null
+--lpm_divide DEVICE_FAMILY="Cyclone II" LPM_DREPRESENTATION="UNSIGNED" LPM_NREPRESENTATION="UNSIGNED" LPM_WIDTHD=25 LPM_WIDTHN=25 OPTIMIZE_FOR_SPEED=5 denom numer remain CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF"
+--VERSION_BEGIN 7.0 cbx_cycloneii 2006:09:30:03:03:26:SJ cbx_lpm_abs 2006:04:25:22:52:42:SJ cbx_lpm_add_sub 2006:10:11:06:03:24:SJ cbx_lpm_divide 2006:01:19:01:01:10:SJ cbx_mgl 2006:10:28:00:08:48:SJ cbx_stratix 2006:09:18:18:47:42:SJ cbx_stratixii 2006:10:13:22:01:30:SJ cbx_util_mgl 2006:11:03:18:32:30:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2007 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+
+FUNCTION sign_div_unsign_dnh (denominator[24..0], numerator[24..0])
+RETURNS ( quotient[24..0], remainder[24..0]);
+
+--synthesis_resources = lut 371
+SUBDESIGN lpm_divide_68m
+(
+ denom[24..0] : input;
+ numer[24..0] : input;
+ quotient[24..0] : output;
+ remain[24..0] : output;
+)
+VARIABLE
+ divider : sign_div_unsign_dnh;
+ numer_tmp[24..0] : WIRE;
+
+BEGIN
+ divider.denominator[] = denom[];
+ divider.numerator[] = numer_tmp[];
+ numer_tmp[] = numer[];
+ quotient[] = divider.quotient[];
+ remain[] = divider.remainder[];
+END;
+--VALID FILE
--- /dev/null
+--lpm_divide DEVICE_FAMILY="Cyclone II" LPM_DREPRESENTATION="UNSIGNED" LPM_NREPRESENTATION="UNSIGNED" LPM_WIDTHD=8 LPM_WIDTHN=8 OPTIMIZE_FOR_SPEED=5 denom numer remain CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF"
+--VERSION_BEGIN 7.0 cbx_cycloneii 2006:09:30:03:03:26:SJ cbx_lpm_abs 2006:04:25:22:52:42:SJ cbx_lpm_add_sub 2006:10:11:06:03:24:SJ cbx_lpm_divide 2006:01:19:01:01:10:SJ cbx_mgl 2006:10:28:00:08:48:SJ cbx_stratix 2006:09:18:18:47:42:SJ cbx_stratixii 2006:10:13:22:01:30:SJ cbx_util_mgl 2006:11:03:18:32:30:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2007 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+
+FUNCTION sign_div_unsign_fkh (denominator[7..0], numerator[7..0])
+RETURNS ( quotient[7..0], remainder[7..0]);
+
+--synthesis_resources = lut 48
+SUBDESIGN lpm_divide_85m
+(
+ denom[7..0] : input;
+ numer[7..0] : input;
+ quotient[7..0] : output;
+ remain[7..0] : output;
+)
+VARIABLE
+ divider : sign_div_unsign_fkh;
+ numer_tmp[7..0] : WIRE;
+
+BEGIN
+ divider.denominator[] = denom[];
+ divider.numerator[] = numer_tmp[];
+ numer_tmp[] = numer[];
+ quotient[] = divider.quotient[];
+ remain[] = divider.remainder[];
+END;
+--VALID FILE
--- /dev/null
+--sign_div_unsign DEN_REPRESENTATION="UNSIGNED" DEN_WIDTH=25 LPM_PIPELINE=0 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="UNSIGNED" NUM_WIDTH=25 SKIP_BITS=0 denominator numerator quotient remainder
+--VERSION_BEGIN 7.0 cbx_cycloneii 2006:09:30:03:03:26:SJ cbx_lpm_abs 2006:04:25:22:52:42:SJ cbx_lpm_add_sub 2006:10:11:06:03:24:SJ cbx_lpm_divide 2006:01:19:01:01:10:SJ cbx_mgl 2006:10:28:00:08:48:SJ cbx_stratix 2006:09:18:18:47:42:SJ cbx_stratixii 2006:10:13:22:01:30:SJ cbx_util_mgl 2006:11:03:18:32:30:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2007 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+
+FUNCTION alt_u_div_s5f (denominator[24..0], numerator[24..0])
+RETURNS ( den_out[24..0], quotient[24..0], remainder[24..0]);
+
+--synthesis_resources = lut 371
+SUBDESIGN sign_div_unsign_dnh
+(
+ denominator[24..0] : input;
+ numerator[24..0] : input;
+ quotient[24..0] : output;
+ remainder[24..0] : output;
+)
+VARIABLE
+ divider : alt_u_div_s5f;
+ adder_result_int[25..0] : WIRE;
+ adder_cin : WIRE;
+ adder_dataa[24..0] : WIRE;
+ adder_datab[24..0] : WIRE;
+ adder_result[24..0] : WIRE;
+ gnd_wire : WIRE;
+ norm_num[24..0] : WIRE;
+ protect_quotient[24..0] : WIRE;
+ protect_remainder[24..0] : WIRE;
+
+BEGIN
+ divider.denominator[] = denominator[];
+ divider.numerator[] = norm_num[];
+ adder_result_int[] = (adder_dataa[], 0) - (adder_datab[], !adder_cin);
+ adder_result[] = adder_result_int[25..1];
+ adder_cin = gnd_wire;
+ adder_dataa[] = denominator[];
+ adder_datab[] = protect_remainder[];
+ gnd_wire = B"0";
+ norm_num[] = numerator[];
+ protect_quotient[] = divider.quotient[];
+ protect_remainder[] = divider.remainder[];
+ quotient[] = protect_quotient[];
+ remainder[] = protect_remainder[];
+END;
+--VALID FILE
--- /dev/null
+--sign_div_unsign DEN_REPRESENTATION="UNSIGNED" DEN_WIDTH=8 LPM_PIPELINE=0 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="UNSIGNED" NUM_WIDTH=8 SKIP_BITS=0 denominator numerator quotient remainder
+--VERSION_BEGIN 7.0 cbx_cycloneii 2006:09:30:03:03:26:SJ cbx_lpm_abs 2006:04:25:22:52:42:SJ cbx_lpm_add_sub 2006:10:11:06:03:24:SJ cbx_lpm_divide 2006:01:19:01:01:10:SJ cbx_mgl 2006:10:28:00:08:48:SJ cbx_stratix 2006:09:18:18:47:42:SJ cbx_stratixii 2006:10:13:22:01:30:SJ cbx_util_mgl 2006:11:03:18:32:30:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2007 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+
+FUNCTION alt_u_div_00f (denominator[7..0], numerator[7..0])
+RETURNS ( den_out[7..0], quotient[7..0], remainder[7..0]);
+
+--synthesis_resources = lut 48
+SUBDESIGN sign_div_unsign_fkh
+(
+ denominator[7..0] : input;
+ numerator[7..0] : input;
+ quotient[7..0] : output;
+ remainder[7..0] : output;
+)
+VARIABLE
+ divider : alt_u_div_00f;
+ adder_result_int[8..0] : WIRE;
+ adder_cin : WIRE;
+ adder_dataa[7..0] : WIRE;
+ adder_datab[7..0] : WIRE;
+ adder_result[7..0] : WIRE;
+ gnd_wire : WIRE;
+ norm_num[7..0] : WIRE;
+ protect_quotient[7..0] : WIRE;
+ protect_remainder[7..0] : WIRE;
+
+BEGIN
+ divider.denominator[] = denominator[];
+ divider.numerator[] = norm_num[];
+ adder_result_int[] = (adder_dataa[], 0) - (adder_datab[], !adder_cin);
+ adder_result[] = adder_result_int[8..1];
+ adder_cin = gnd_wire;
+ adder_dataa[] = denominator[];
+ adder_datab[] = protect_remainder[];
+ gnd_wire = B"0";
+ norm_num[] = numerator[];
+ protect_quotient[] = divider.quotient[];
+ protect_remainder[] = divider.remainder[];
+ quotient[] = protect_quotient[];
+ remainder[] = protect_remainder[];
+END;
+--VALID FILE
--- /dev/null
+Assembler report for demo
+Mon Mar 30 19:53:29 2009
+Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Assembler Summary
+ 3. Assembler Settings
+ 4. Assembler Generated Files
+ 5. Assembler Device Options: demo.sof
+ 6. Assembler Device Options: demo.pof
+ 7. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2007 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary ;
++-----------------------+---------------------------------------+
+; Assembler Status ; Successful - Mon Mar 30 19:53:29 2009 ;
+; Revision Name ; demo ;
+; Top-level Entity Name ; demo_top ;
+; Family ; Cyclone II ;
+; Device ; EP2C35F484C6 ;
++-----------------------+---------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Assembler Settings ;
++--------------------------------------------------------------------------------+----------+---------------+
+; Option ; Setting ; Default Value ;
++--------------------------------------------------------------------------------+----------+---------------+
+; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
+; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
+; Generate an uncompressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
+; Generate compressed bitstreams ; On ; On ;
+; Compression mode ; Off ; Off ;
+; Clock source for configuration device ; Internal ; Internal ;
+; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
+; Divide clock frequency by ; 1 ; 1 ;
+; JTAG user code for target device ; Ffffffff ; Ffffffff ;
+; Configuration device ; Auto ; Auto ;
+; JTAG user code for configuration device ; Ffffffff ; Ffffffff ;
+; Configuration device auto user code ; Off ; Off ;
+; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
+; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ;
+; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
+; Hexadecimal Output File start address ; 0 ; 0 ;
+; Hexadecimal Output File count direction ; Up ; Up ;
+; Release clears before tri-states ; Off ; Off ;
+; Auto-restart configuration after error ; On ; On ;
+; Maintain Compatibility with All Cyclone II M4K Versions ; On ; On ;
+; Use smart compilation ; Off ; Off ;
++--------------------------------------------------------------------------------+----------+---------------+
+
+
++---------------------------+
+; Assembler Generated Files ;
++---------------------------+
+; File Name ;
++---------------------------+
+; demo.sof ;
+; demo.pof ;
++---------------------------+
+
+
++------------------------------------+
+; Assembler Device Options: demo.sof ;
++----------------+-------------------+
+; Option ; Setting ;
++----------------+-------------------+
+; Device ; EP2C35F484C6 ;
+; JTAG usercode ; 0xFFFFFFFF ;
+; Checksum ; 0x002F59CC ;
++----------------+-------------------+
+
+
++------------------------------------+
+; Assembler Device Options: demo.pof ;
++--------------------+---------------+
+; Option ; Setting ;
++--------------------+---------------+
+; Device ; EPCS16 ;
+; JTAG usercode ; 0x00000000 ;
+; Checksum ; 0x1C74DD1C ;
+; Compression Ratio ; 3 ;
++--------------------+---------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II Assembler
+ Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
+ Info: Processing started: Mon Mar 30 19:53:02 2009
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off demo -c demo
+Info: Writing out detailed assembly data for power analysis
+Info: Assembler is generating device programming files
+Info: Quartus II Assembler was successful. 0 errors, 0 warnings
+ Info: Processing ended: Mon Mar 30 19:53:29 2009
+ Info: Elapsed time: 00:00:27
+
+
--- /dev/null
+Mon Mar 30 19:53:38 2009
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+
+<pin_planner>
+ <pin_info>
+ </pin_info>
+ <buses>
+ </buses>
+ <group_file_association>
+ </group_file_association>
+ <pin_planner_file_specifies>
+ </pin_planner_file_specifies>
+</pin_planner>
--- /dev/null
+EDA Netlist Writer report for demo
+Mon Mar 30 19:53:36 2009
+Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. EDA Netlist Writer Summary
+ 3. Simulation Settings
+ 4. Simulation Generated Files
+ 5. EDA Netlist Writer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2007 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++-------------------------------------------------------------------+
+; EDA Netlist Writer Summary ;
++---------------------------+---------------------------------------+
+; EDA Netlist Writer Status ; Successful - Mon Mar 30 19:53:36 2009 ;
+; Revision Name ; demo ;
+; Top-level Entity Name ; demo_top ;
+; Family ; Cyclone II ;
+; Simulation Files Creation ; Successful ;
++---------------------------+---------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Simulation Settings ;
++--------------------------------------------------------------------------------------------+-----------------+
+; Option ; Setting ;
++--------------------------------------------------------------------------------------------+-----------------+
+; Tool Name ; ModelSim (VHDL) ;
+; Generate netlist for functional simulation only ; Off ;
+; Time scale ; 1 ps ;
+; Truncate long hierarchy paths ; Off ;
+; Map illegal HDL characters ; Off ;
+; Flatten buses into individual nodes ; Off ;
+; Maintain hierarchy ; Off ;
+; Bring out device-wide set/reset signals as ports ; Off ;
+; Enable glitch filtering ; Off ;
+; Do not write top level VHDL entity ; Off ;
+; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off ;
+; Architecture name in VHDL output netlist ; structure ;
++--------------------------------------------------------------------------------------------+-----------------+
+
+
++-----------------------------------------------------------------------------------------------------------------+
+; Simulation Generated Files ;
++-----------------------------------------------------------------------------------------------------------------+
+; Generated Files ;
++-----------------------------------------------------------------------------------------------------------------+
+; /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/simulation/modelsim/demo.vho ;
+; /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/simulation/modelsim/demo_vhd.sdo ;
++-----------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------+
+; EDA Netlist Writer Messages ;
++-----------------------------+
+Info: *******************************************************************
+Info: Running Quartus II EDA Netlist Writer
+ Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
+ Info: Processing started: Mon Mar 30 19:53:35 2009
+Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off demo -c demo
+Info: Generated files "demo.vho" and "demo_vhd.sdo" in directory "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/simulation/modelsim/" for EDA simulation tool
+Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings
+ Info: Processing ended: Mon Mar 30 19:53:36 2009
+ Info: Elapsed time: 00:00:01
+
+
--- /dev/null
+Fitter report for demo
+Mon Mar 30 19:52:59 2009
+Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Fitter Summary
+ 3. Fitter Settings
+ 4. Pin-Out File
+ 5. Fitter Resource Usage Summary
+ 6. Input Pins
+ 7. Output Pins
+ 8. I/O Bank Usage
+ 9. All Package Pins
+ 10. PLL Summary
+ 11. PLL Usage
+ 12. Output Pin Default Load For Reported TCO
+ 13. Fitter Resource Utilization by Entity
+ 14. Delay Chain Summary
+ 15. Pad To Core Delay Chain Fanout
+ 16. Control Signals
+ 17. Global & Other Fast Signals
+ 18. Non-Global High Fan-Out Signals
+ 19. Interconnect Usage Summary
+ 20. LAB Logic Elements
+ 21. LAB-wide Signals
+ 22. LAB Signals Sourced
+ 23. LAB Signals Sourced Out
+ 24. LAB Distinct Inputs
+ 25. Fitter Device Options
+ 26. Fitter Messages
+ 27. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2007 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++------------------------------------------------------------------------------+
+; Fitter Summary ;
++------------------------------------+-----------------------------------------+
+; Fitter Status ; Successful - Mon Mar 30 19:52:59 2009 ;
+; Quartus II Version ; 7.0 Build 33 02/05/2007 SJ Full Version ;
+; Revision Name ; demo ;
+; Top-level Entity Name ; demo_top ;
+; Family ; Cyclone II ;
+; Device ; EP2C35F484C6 ;
+; Timing Models ; Final ;
+; Total logic elements ; 65 / 33,216 ( < 1 % ) ;
+; Total combinational functions ; 65 / 33,216 ( < 1 % ) ;
+; Dedicated logic registers ; 16 / 33,216 ( < 1 % ) ;
+; Total registers ; 16 ;
+; Total pins ; 10 / 322 ( 3 % ) ;
+; Total virtual pins ; 0 ;
+; Total memory bits ; 0 / 483,840 ( 0 % ) ;
+; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % ) ;
+; Total PLLs ; 1 / 4 ( 25 % ) ;
++------------------------------------+-----------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings ;
++--------------------------------------------------------+--------------------------------+--------------------------------+
+; Option ; Setting ; Default Value ;
++--------------------------------------------------------+--------------------------------+--------------------------------+
+; Device ; EP2C35F484C6 ; ;
+; Fit Attempts to Skip ; 0 ; 0.0 ;
+; Always Enable Input Buffers ; Off ; Off ;
+; Router Timing Optimization Level ; Normal ; Normal ;
+; Placement Effort Multiplier ; 1.0 ; 1.0 ;
+; Router Effort Multiplier ; 1.0 ; 1.0 ;
+; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
+; Optimize Fast-Corner Timing ; Off ; Off ;
+; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
+; Optimize Timing ; Normal compilation ; Normal compilation ;
+; Optimize IOC Register Placement for Timing ; On ; On ;
+; Limit to One Fitting Attempt ; Off ; Off ;
+; Final Placement Optimizations ; Automatically ; Automatically ;
+; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
+; Fitter Initial Placement Seed ; 1 ; 1 ;
+; PCI I/O ; Off ; Off ;
+; Weak Pull-Up Resistor ; Off ; Off ;
+; Enable Bus-Hold Circuitry ; Off ; Off ;
+; Auto Global Memory Control Signals ; Off ; Off ;
+; Auto Packed Registers -- Stratix II/III/Cyclone II/III ; Auto ; Auto ;
+; Auto Delay Chains ; On ; On ;
+; Auto Merge PLLs ; On ; On ;
+; Ignore PLL Mode When Merging PLLs ; Off ; Off ;
+; Perform Physical Synthesis for Combinational Logic ; Off ; Off ;
+; Perform Register Duplication ; Off ; Off ;
+; Perform Register Retiming ; Off ; Off ;
+; Perform Asynchronous Signal Pipelining ; Off ; Off ;
+; Fitter Effort ; Auto Fit ; Auto Fit ;
+; Physical Synthesis Effort Level ; Normal ; Normal ;
+; Auto Global Clock ; On ; On ;
+; Auto Global Register Control Signals ; On ; On ;
+; Stop After Congestion Map Generation ; Off ; Off ;
+; Use smart compilation ; Off ; Off ;
++--------------------------------------------------------+--------------------------------+--------------------------------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/demo.pin.
+
+
++---------------------------------------------------------------------+
+; Fitter Resource Usage Summary ;
++---------------------------------------------+-----------------------+
+; Resource ; Usage ;
++---------------------------------------------+-----------------------+
+; Total logic elements ; 65 / 33,216 ( < 1 % ) ;
+; -- Combinational with no register ; 49 ;
+; -- Register only ; 0 ;
+; -- Combinational with a register ; 16 ;
+; ; ;
+; Logic element usage by number of LUT inputs ; ;
+; -- 4 input functions ; 11 ;
+; -- 3 input functions ; 23 ;
+; -- <=2 input functions ; 31 ;
+; -- Register only ; 0 ;
+; ; ;
+; Logic elements by mode ; ;
+; -- normal mode ; 48 ;
+; -- arithmetic mode ; 17 ;
+; ; ;
+; Total registers* ; 16 / 34,134 ( < 1 % ) ;
+; -- Dedicated logic registers ; 16 / 33,216 ( < 1 % ) ;
+; -- I/O registers ; 0 / 918 ( 0 % ) ;
+; ; ;
+; Total LABs: partially or completely used ; 5 / 2,076 ( < 1 % ) ;
+; User inserted logic elements ; 0 ;
+; Virtual pins ; 0 ;
+; I/O pins ; 10 / 322 ( 3 % ) ;
+; -- Clock pins ; 1 / 8 ( 13 % ) ;
+; Global signals ; 1 ;
+; M4Ks ; 0 / 105 ( 0 % ) ;
+; Total memory bits ; 0 / 483,840 ( 0 % ) ;
+; Total RAM block bits ; 0 / 483,840 ( 0 % ) ;
+; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % ) ;
+; PLLs ; 1 / 4 ( 25 % ) ;
+; Global clocks ; 1 / 16 ( 6 % ) ;
+; Average interconnect usage ; 0% ;
+; Peak interconnect usage ; 0% ;
+; Maximum fan-out node ; RESET ;
+; Maximum fan-out ; 16 ;
+; Highest non-global fan-out signal ; RESET ;
+; Highest non-global fan-out ; 16 ;
+; Total fan-out ; 226 ;
+; Average fan-out ; 2.35 ;
++---------------------------------------------+-----------------------+
+* Register count does not include registers inside RAM blocks or DSP blocks.
+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins ;
++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+; CLK ; M1 ; 1 ; 0 ; 18 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; RESET ; B3 ; 3 ; 1 ; 36 ; 3 ; 16 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins ;
++---------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ;
++---------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
+; LEDS[0] ; W5 ; 1 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; LEDS[1] ; W4 ; 1 ; 0 ; 4 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; LEDS[2] ; W3 ; 1 ; 0 ; 4 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; LEDS[3] ; W2 ; 1 ; 0 ; 6 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; LEDS[4] ; W1 ; 1 ; 0 ; 6 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; LEDS[5] ; V2 ; 1 ; 0 ; 7 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; LEDS[6] ; V1 ; 1 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; LEDS[7] ; U1 ; 1 ; 0 ; 9 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
++---------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
+
+
++-----------------------------------------------------------+
+; I/O Bank Usage ;
++----------+-----------------+---------------+--------------+
+; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
++----------+-----------------+---------------+--------------+
+; 1 ; 9 / 46 ( 20 % ) ; 3.3V ; -- ;
+; 2 ; 2 / 39 ( 5 % ) ; 3.3V ; -- ;
+; 3 ; 1 / 39 ( 3 % ) ; 3.3V ; -- ;
+; 4 ; 0 / 36 ( 0 % ) ; 3.3V ; -- ;
+; 5 ; 0 / 44 ( 0 % ) ; 3.3V ; -- ;
+; 6 ; 1 / 43 ( 2 % ) ; 3.3V ; -- ;
+; 7 ; 0 / 36 ( 0 % ) ; 3.3V ; -- ;
+; 8 ; 0 / 39 ( 0 % ) ; 3.3V ; -- ;
++----------+-----------------+---------------+--------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins ;
++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A2 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; A3 ; 485 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; A4 ; 484 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; A5 ; 482 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; A6 ; 480 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; A7 ; 460 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; A8 ; 458 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; A9 ; 448 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; A10 ; 440 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; A11 ; 434 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; A12 ; 430 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
+; A13 ; 428 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; A14 ; 423 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; A15 ; 414 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; A16 ; 412 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; A17 ; 404 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; A18 ; 380 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; A19 ; 378 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; A20 ; 376 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; A21 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA3 ; 131 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; AA4 ; 134 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; AA5 ; 138 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; AA6 ; 151 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; AA7 ; 158 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; AA8 ; 170 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; AA9 ; 176 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; AA10 ; 182 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; AA11 ; 184 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; AA12 ; 190 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; AA13 ; 195 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; AA14 ; 204 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; AA15 ; 206 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; AA16 ; 208 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; AA17 ; 214 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; AA18 ; 228 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; AA19 ; 242 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; AA20 ; 244 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; AA21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA22 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB2 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AB3 ; 132 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; AB4 ; 133 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; AB5 ; 137 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; AB6 ; 150 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; AB7 ; 157 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; AB8 ; 169 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; AB9 ; 175 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; AB10 ; 181 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; AB11 ; 183 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; AB12 ; 189 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; AB13 ; 194 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; AB14 ; 203 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; AB15 ; 205 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; AB16 ; 207 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; AB17 ; 213 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; AB18 ; 227 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; AB19 ; 241 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; AB20 ; 243 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; AB21 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B1 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B3 ; 486 ; 3 ; RESET ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; B4 ; 483 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; B5 ; 481 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; B6 ; 479 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; B7 ; 459 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; B8 ; 457 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; B9 ; 447 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; B10 ; 439 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; B11 ; 433 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; B12 ; 429 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
+; B13 ; 427 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; B14 ; 422 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; B15 ; 413 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; B16 ; 411 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; B17 ; 403 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; B18 ; 379 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; B19 ; 377 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; B20 ; 375 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; B21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B22 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; C1 ; 8 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; C2 ; 9 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; C3 ; 1 ; 2 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; C4 ; 0 ; 2 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; C5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C6 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; C7 ; 474 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; C8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C9 ; 464 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; C10 ; 445 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; C11 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; C12 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; C13 ; 415 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; C14 ; 398 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; C15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C16 ; 388 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; C17 ; 374 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; C18 ; 373 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; C19 ; 367 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; C20 ; 368 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; C21 ; 360 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; C22 ; 361 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; D1 ; 26 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; D2 ; 27 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; D3 ; 2 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; D4 ; 3 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; D5 ; 4 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; D6 ; 5 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; D7 ; 466 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; D8 ; 463 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; D9 ; 454 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; D10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; D11 ; 436 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; D12 ; 431 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
+; D13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; D14 ; 408 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; D15 ; 397 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; D16 ; 389 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; D17 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; D18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; D19 ; 369 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; D20 ; 370 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; D21 ; 351 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; D22 ; 352 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; E1 ; 32 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; E2 ; 33 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; E3 ; 6 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; E4 ; 7 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; E5 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; E6 ; ; ; VCCA_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; E7 ; 472 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; E8 ; 462 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; E9 ; 453 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; E10 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; E11 ; 435 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; E12 ; 432 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
+; E13 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; E14 ; 407 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; E15 ; 390 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; E16 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
+; E17 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
+; E18 ; 372 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; E19 ; 371 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; E20 ; 358 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; E21 ; 349 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; E22 ; 350 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; F1 ; 34 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; F2 ; 35 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; F3 ; 25 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; F4 ; 15 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; F5 ; ; ; GND_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ;
+; F6 ; ; ; GND_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ;
+; F7 ; ; ; GNDA_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ;
+; F8 ; 467 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; F9 ; 461 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; F10 ; 442 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; F11 ; 441 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; F12 ; 418 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; F13 ; 410 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; F14 ; 409 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; F15 ; 400 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; F16 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; F17 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; F18 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
+; F19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F20 ; 359 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; F21 ; 342 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; F22 ; 343 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; G1 ; 45 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; G2 ; 46 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; G3 ; 28 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; G5 ; 17 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; G6 ; 16 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; G7 ; 475 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; G8 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; G9 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; G10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; G11 ; 438 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; G12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; G13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; G14 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; G15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; G16 ; 381 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; G17 ; 353 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; G18 ; 354 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; G19 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; G20 ; 357 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; G21 ; 338 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; G22 ; 339 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; H1 ; 50 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; H2 ; 51 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; H3 ; 44 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; H4 ; 29 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; H5 ; 30 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; H6 ; 31 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; H7 ; 476 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; H8 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; H9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; H10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; H11 ; 437 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; H12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; H13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; H14 ; 391 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; H15 ; 382 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; H16 ; 334 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; H17 ; 346 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; H18 ; 345 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; H19 ; 324 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; H20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; H21 ; 318 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; H22 ; 319 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; J1 ; 55 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; J2 ; 56 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; J3 ; 53 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; J4 ; 54 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; J5 ; 48 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; J6 ; 47 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; J7 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; J8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; J11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; J12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; J13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; J14 ; 392 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; J15 ; 335 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; J16 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; J17 ; 333 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; J18 ; 331 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; J19 ; 330 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; J20 ; 323 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; J21 ; 314 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; J22 ; 315 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; K1 ; 63 ; 2 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
+; K2 ; 58 ; 2 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
+; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K4 ; 62 ; 2 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ;
+; K5 ; 57 ; 2 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
+; K6 ; 59 ; 2 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
+; K7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K8 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; K15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K17 ; 317 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; K18 ; 322 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; K19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K20 ; 325 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; K21 ; 312 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; K22 ; 313 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; L1 ; 64 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; L2 ; 65 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; L3 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; L4 ; 66 ; 2 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
+; L5 ; 60 ; 2 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
+; L6 ; 61 ; 2 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ;
+; L7 ; 52 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; L8 ; 49 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; L9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; L10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; L17 ; 316 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; L18 ; 311 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; L19 ; 310 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; L20 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; L21 ; 308 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; L22 ; 309 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; M1 ; 67 ; 1 ; CLK ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; M2 ; 68 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; M3 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; M4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M5 ; 69 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; M6 ; 70 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; M7 ; 76 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; M8 ; 75 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; M15 ; 294 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; M16 ; 293 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; M17 ; 301 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
+; M18 ; 305 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; M19 ; 304 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; M20 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; M21 ; 306 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; M22 ; 307 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; N1 ; 71 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; N2 ; 72 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; N3 ; 81 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; N4 ; 82 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; N5 ; 78 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; N6 ; 77 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; N7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; N10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; N15 ; 290 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; N16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N17 ; 300 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
+; N18 ; 299 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
+; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N20 ; 298 ; 6 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
+; N21 ; 302 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; N22 ; 303 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; P1 ; 73 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; P2 ; 74 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; P3 ; 83 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; P4 ; 98 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; P5 ; 88 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; P6 ; 89 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; P7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; P8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; P12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; P14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; P15 ; 289 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; P16 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; P17 ; 277 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; P18 ; 278 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; P19 ; 292 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; P20 ; 291 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; P21 ; 295 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; P22 ; 296 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; R1 ; 90 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; R2 ; 91 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R4 ; 99 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; R5 ; 104 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; R6 ; 105 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; R7 ; 87 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; R8 ; 86 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; R11 ; 178 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; R12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R14 ; 225 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; R15 ; 226 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; R16 ; 235 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; R17 ; 265 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; R18 ; 275 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; R19 ; 276 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; R20 ; 288 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; R21 ; 283 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; R22 ; 284 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; T1 ; 96 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; T2 ; 97 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; T3 ; 112 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; T4 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; T5 ; 110 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; T6 ; 111 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; T7 ; 142 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; T8 ; 141 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; T9 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T11 ; 177 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; T12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; T13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T14 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; T15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; T16 ; 236 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; T17 ; ; ; GND_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ;
+; T18 ; 252 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; T19 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T21 ; 281 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; T22 ; 282 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; U1 ; 101 ; 1 ; LEDS[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; U2 ; 102 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; U3 ; 113 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; U4 ; 129 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; U5 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
+; U6 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; U7 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; U8 ; 145 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; U9 ; 163 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; U10 ; 164 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; U11 ; 185 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
+; U12 ; 186 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
+; U13 ; 199 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; U14 ; 217 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; U15 ; 237 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; U16 ; ; ; VCCA_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; U17 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; U18 ; 251 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; U19 ; 253 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; U20 ; 259 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; U21 ; 273 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; U22 ; 274 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; V1 ; 108 ; 1 ; LEDS[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; V2 ; 109 ; 1 ; LEDS[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; V3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V4 ; 130 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; V5 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
+; V6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V7 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
+; V8 ; 153 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; V9 ; 156 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; V10 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; V11 ; 180 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; V12 ; 188 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
+; V13 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; V14 ; 210 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; V15 ; 238 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; V16 ; ; ; GNDA_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ;
+; V17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V18 ; ; ; GND_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ;
+; V19 ; 246 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; V20 ; 254 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; V21 ; 271 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; V22 ; 272 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; W1 ; 114 ; 1 ; LEDS[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; W2 ; 115 ; 1 ; LEDS[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; W3 ; 122 ; 1 ; LEDS[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; W4 ; 123 ; 1 ; LEDS[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; W5 ; 128 ; 1 ; LEDS[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; W6 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; W7 ; 154 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; W8 ; 155 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; W9 ; 160 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; W10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W11 ; 179 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; W12 ; 187 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
+; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W14 ; 209 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; W15 ; 220 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; W16 ; 240 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; W17 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; W18 ; 250 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W20 ; 247 ; 6 ; ~LVDS150p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; W21 ; 260 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; W22 ; 261 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; Y1 ; 116 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; Y2 ; 117 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; Y3 ; 126 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; Y4 ; 127 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; Y5 ; 135 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; Y6 ; 136 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; Y7 ; 143 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; Y8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y9 ; 159 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; Y10 ; 172 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; Y11 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; Y12 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; Y13 ; 202 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; Y14 ; 219 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y16 ; 229 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; Y17 ; 239 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; Y18 ; 245 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; Y19 ; 248 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; Y20 ; 249 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; Y21 ; 268 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; Y22 ; 269 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+
+
++--------------------------------------------------------------------------+
+; PLL Summary ;
++----------------------------------+---------------------------------------+
+; Name ; pll:inst1|altpll:altpll_component|pll ;
++----------------------------------+---------------------------------------+
+; PLL mode ; Normal ;
+; Compensate clock ; clock0 ;
+; Self reset on gated loss of lock ; Off ;
+; Gate lock counter ; -- ;
+; Input frequency 0 ; 25.0 MHz ;
+; Input frequency 1 ; -- ;
+; Nominal PFD frequency ; 25.0 MHz ;
+; Nominal VCO frequency ; 800.0 MHz ;
+; VCO post scale ; -- ;
+; VCO multiply ; -- ;
+; VCO divide ; -- ;
+; Freq min lock ; 15.63 MHz ;
+; Freq max lock ; 31.25 MHz ;
+; M VCO Tap ; 0 ;
+; M Initial ; 1 ;
+; M value ; 32 ;
+; N value ; 1 ;
+; Preserve counter order ; Off ;
+; PLL location ; PLL_1 ;
+; Inclk0 signal ; CLK ;
+; Inclk1 signal ; -- ;
+; Inclk0 signal type ; Dedicated Pin ;
+; Inclk1 signal type ; -- ;
++----------------------------------+---------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; PLL Usage ;
++-----------------------------------------+--------------+------+-----+------------------+-------------+------------+---------+---------------+------------+---------+---------+
+; Name ; Output Clock ; Mult ; Div ; Output Frequency ; Phase Shift ; Duty Cycle ; Counter ; Counter Value ; High / Low ; Initial ; VCO Tap ;
++-----------------------------------------+--------------+------+-----+------------------+-------------+------------+---------+---------------+------------+---------+---------+
+; pll:inst1|altpll:altpll_component|_clk0 ; clock0 ; 4 ; 1 ; 100.0 MHz ; 0 (0 ps) ; 50/50 ; C0 ; 8 ; 4/4 Even ; 1 ; 0 ;
++-----------------------------------------+--------------+------+-----+------------------+-------------+------------+---------+---------------+------------+---------+---------+
+
+
++-------------------------------------------------------------------------------+
+; Output Pin Default Load For Reported TCO ;
++----------------------------------+-------+------------------------------------+
+; I/O Standard ; Load ; Termination Resistance ;
++----------------------------------+-------+------------------------------------+
+; 3.3-V LVTTL ; 0 pF ; Not Available ;
+; 3.3-V LVCMOS ; 0 pF ; Not Available ;
+; 2.5 V ; 0 pF ; Not Available ;
+; 1.8 V ; 0 pF ; Not Available ;
+; 1.5 V ; 0 pF ; Not Available ;
+; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ;
+; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ;
+; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
+; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
+; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
+; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
+; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ;
+; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ;
+; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ;
+; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ;
+; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ;
+; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ;
+; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ;
+; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ;
+; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ;
+; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ;
+; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ;
+; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ;
+; LVDS ; 0 pF ; 100 Ohm (Differential) ;
+; mini-LVDS ; 0 pF ; 100 Ohm (Differential) ;
+; RSDS ; 0 pF ; 100 Ohm (Differential) ;
+; Simple RSDS ; 0 pF ; Not Available ;
+; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ;
++----------------------------------+-------+------------------------------------+
+Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity ;
++-------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------------------------------------------------------------------------------------------------------+
+; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ;
++-------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------------------------------------------------------------------------------------------------------+
+; |demo_top ; 65 (0) ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 ; 0 ; 49 (0) ; 0 (0) ; 16 (0) ; |demo_top ;
+; |demo:inst| ; 65 (36) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 49 (20) ; 0 (0) ; 16 (9) ; |demo_top|demo:inst ;
+; |lpm_divide:Mod0| ; 36 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 29 (0) ; 0 (0) ; 7 (0) ; |demo_top|demo:inst|lpm_divide:Mod0 ;
+; |lpm_divide_85m:auto_generated| ; 36 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 29 (0) ; 0 (0) ; 7 (0) ; |demo_top|demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated ;
+; |sign_div_unsign_fkh:divider| ; 36 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 29 (0) ; 0 (0) ; 7 (0) ; |demo_top|demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider ;
+; |alt_u_div_00f:divider| ; 36 (36) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 29 (29) ; 0 (0) ; 7 (7) ; |demo_top|demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider ;
+; |pll:inst1| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |demo_top|pll:inst1 ;
+; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |demo_top|pll:inst1|altpll:altpll_component ;
++-------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------------------------------------------------------------------------------------------------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++----------------------------------------------------------------------------------+
+; Delay Chain Summary ;
++---------+----------+---------------+---------------+-----------------------+-----+
+; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ;
++---------+----------+---------------+---------------+-----------------------+-----+
+; LEDS[7] ; Output ; -- ; -- ; -- ; -- ;
+; LEDS[6] ; Output ; -- ; -- ; -- ; -- ;
+; LEDS[5] ; Output ; -- ; -- ; -- ; -- ;
+; LEDS[4] ; Output ; -- ; -- ; -- ; -- ;
+; LEDS[3] ; Output ; -- ; -- ; -- ; -- ;
+; LEDS[2] ; Output ; -- ; -- ; -- ; -- ;
+; LEDS[1] ; Output ; -- ; -- ; -- ; -- ;
+; LEDS[0] ; Output ; -- ; -- ; -- ; -- ;
+; RESET ; Input ; 6 ; 6 ; -- ; -- ;
+; CLK ; Input ; -- ; -- ; -- ; -- ;
++---------+----------+---------------+---------------+-----------------------+-----+
+
+
++---------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout ;
++---------------------------------+-------------------+---------+
+; Source Pin / Fanout ; Pad To Core Index ; Setting ;
++---------------------------------+-------------------+---------+
+; RESET ; ; ;
+; - demo:inst|knightlight[7] ; 1 ; 6 ;
+; - demo:inst|knightlight[6] ; 1 ; 6 ;
+; - demo:inst|knightlight[5] ; 1 ; 6 ;
+; - demo:inst|knightlight[4] ; 1 ; 6 ;
+; - demo:inst|knightlight[3] ; 1 ; 6 ;
+; - demo:inst|knightlight[2] ; 1 ; 6 ;
+; - demo:inst|knightlight[1] ; 1 ; 6 ;
+; - demo:inst|knightlight[0] ; 1 ; 6 ;
+; - demo:inst|counter[3] ; 1 ; 6 ;
+; - demo:inst|counter[2] ; 1 ; 6 ;
+; - demo:inst|counter[1] ; 1 ; 6 ;
+; - demo:inst|counter[0] ; 1 ; 6 ;
+; - demo:inst|counter[4] ; 1 ; 6 ;
+; - demo:inst|counter[5] ; 1 ; 6 ;
+; - demo:inst|counter[6] ; 1 ; 6 ;
+; - demo:inst|ledstate ; 1 ; 6 ;
+; CLK ; ; ;
++---------------------------------+-------------------+---------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals ;
++-----------------------------------------+----------+---------+-------------------------+--------+----------------------+------------------+---------------------------+
+; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++-----------------------------------------+----------+---------+-------------------------+--------+----------------------+------------------+---------------------------+
+; CLK ; PIN_M1 ; 1 ; Clock ; no ; -- ; -- ; -- ;
+; RESET ; PIN_B3 ; 16 ; Sync. clear, Sync. load ; no ; -- ; -- ; -- ;
+; pll:inst1|altpll:altpll_component|_clk0 ; PLL_1 ; 16 ; Clock ; yes ; Global Clock ; GCLK3 ; -- ;
++-----------------------------------------+----------+---------+-------------------------+--------+----------------------+------------------+---------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Global & Other Fast Signals ;
++-----------------------------------------+----------+---------+----------------------+------------------+---------------------------+
+; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++-----------------------------------------+----------+---------+----------------------+------------------+---------------------------+
+; pll:inst1|altpll:altpll_component|_clk0 ; PLL_1 ; 16 ; Global Clock ; GCLK3 ; -- ;
++-----------------------------------------+----------+---------+----------------------+------------------+---------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------+
+; Non-Global High Fan-Out Signals ;
++--------------------------------------------------------------------------------------------------------------------------------------+---------+
+; Name ; Fan-Out ;
++--------------------------------------------------------------------------------------------------------------------------------------+---------+
+; RESET ; 16 ;
+; demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[7]~26 ; 14 ;
+; demo:inst|ledstate ; 11 ;
+; demo:inst|Equal1~59 ; 9 ;
+; demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[8]~32 ; 7 ;
+; demo:inst|knightlight[2] ; 6 ;
+; demo:inst|knightlight[3] ; 6 ;
+; demo:inst|knightlight[1] ; 5 ;
+; demo:inst|knightlight[4] ; 5 ;
+; demo:inst|knightlight[5] ; 5 ;
+; demo:inst|knightlight[6] ; 5 ;
+; demo:inst|counter[0] ; 4 ;
+; demo:inst|knightlight[0] ; 4 ;
+; demo:inst|knightlight[7] ; 4 ;
+; demo:inst|Add0~98 ; 3 ;
+; demo:inst|Add0~96 ; 3 ;
+; demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[50]~29 ; 2 ;
+; demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[50]~21 ; 2 ;
+; demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[51]~28 ; 2 ;
+; demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[51]~20 ; 2 ;
+; demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[52]~27 ; 2 ;
+; demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[52]~19 ; 2 ;
+; demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[53]~26 ; 2 ;
+; demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[53]~18 ; 2 ;
+; demo:inst|Add0~108 ; 2 ;
+; demo:inst|Add0~106 ; 2 ;
+; demo:inst|Add0~104 ; 2 ;
+; demo:inst|Add0~102 ; 2 ;
+; demo:inst|Add0~100 ; 2 ;
+; demo:inst|counter[4] ; 2 ;
+; demo:inst|counter[6] ; 2 ;
+; demo:inst|counter[5] ; 2 ;
+; demo:inst|counter[2] ; 2 ;
+; demo:inst|counter[3] ; 2 ;
+; demo:inst|counter[1] ; 2 ;
+; CLK ; 1 ;
+; demo:inst|ledstate_next~436 ; 1 ;
+; demo:inst|ledstate_next~435 ; 1 ;
+; demo:inst|ledstate_next~434 ; 1 ;
+; demo:inst|ledstate_next~433 ; 1 ;
+; demo:inst|ledstate_next~432 ; 1 ;
+; demo:inst|ledstate_next~431 ; 1 ;
+; demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[60]~642 ; 1 ;
+; demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[62]~641 ; 1 ;
+; demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[61]~640 ; 1 ;
+; demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[58]~639 ; 1 ;
+; demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[59]~638 ; 1 ;
+; demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[56]~637 ; 1 ;
+; demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[57]~636 ; 1 ;
+; demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[49]~30 ; 1 ;
++--------------------------------------------------------------------------------------------------------------------------------------+---------+
+
+
++----------------------------------------------------+
+; Interconnect Usage Summary ;
++----------------------------+-----------------------+
+; Interconnect Resource Type ; Usage ;
++----------------------------+-----------------------+
+; Block interconnects ; 64 / 94,460 ( < 1 % ) ;
+; C16 interconnects ; 11 / 3,315 ( < 1 % ) ;
+; C4 interconnects ; 51 / 60,840 ( < 1 % ) ;
+; Direct links ; 27 / 94,460 ( < 1 % ) ;
+; Global clocks ; 1 / 16 ( 6 % ) ;
+; Local interconnects ; 41 / 33,216 ( < 1 % ) ;
+; R24 interconnects ; 16 / 3,091 ( < 1 % ) ;
+; R4 interconnects ; 79 / 81,294 ( < 1 % ) ;
++----------------------------+-----------------------+
+
+
++---------------------------------------------------------------------------+
+; LAB Logic Elements ;
++---------------------------------------------+-----------------------------+
+; Number of Logic Elements (Average = 13.00) ; Number of LABs (Total = 5) ;
++---------------------------------------------+-----------------------------+
+; 1 ; 0 ;
+; 2 ; 0 ;
+; 3 ; 0 ;
+; 4 ; 0 ;
+; 5 ; 0 ;
+; 6 ; 0 ;
+; 7 ; 0 ;
+; 8 ; 0 ;
+; 9 ; 1 ;
+; 10 ; 1 ;
+; 11 ; 0 ;
+; 12 ; 0 ;
+; 13 ; 0 ;
+; 14 ; 1 ;
+; 15 ; 0 ;
+; 16 ; 2 ;
++---------------------------------------------+-----------------------------+
+
+
++------------------------------------------------------------------+
+; LAB-wide Signals ;
++------------------------------------+-----------------------------+
+; LAB-wide Signals (Average = 1.60) ; Number of LABs (Total = 5) ;
++------------------------------------+-----------------------------+
+; 1 Clock ; 4 ;
+; 1 Sync. clear ; 3 ;
+; 1 Sync. load ; 1 ;
++------------------------------------+-----------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Signals Sourced ;
++----------------------------------------------+-----------------------------+
+; Number of Signals Sourced (Average = 16.00) ; Number of LABs (Total = 5) ;
++----------------------------------------------+-----------------------------+
+; 0 ; 0 ;
+; 1 ; 0 ;
+; 2 ; 0 ;
+; 3 ; 0 ;
+; 4 ; 0 ;
+; 5 ; 0 ;
+; 6 ; 0 ;
+; 7 ; 0 ;
+; 8 ; 0 ;
+; 9 ; 0 ;
+; 10 ; 1 ;
+; 11 ; 0 ;
+; 12 ; 1 ;
+; 13 ; 0 ;
+; 14 ; 0 ;
+; 15 ; 0 ;
+; 16 ; 0 ;
+; 17 ; 0 ;
+; 18 ; 0 ;
+; 19 ; 2 ;
+; 20 ; 1 ;
++----------------------------------------------+-----------------------------+
+
+
++-------------------------------------------------------------------------------+
+; LAB Signals Sourced Out ;
++-------------------------------------------------+-----------------------------+
+; Number of Signals Sourced Out (Average = 8.40) ; Number of LABs (Total = 5) ;
++-------------------------------------------------+-----------------------------+
+; 0 ; 0 ;
+; 1 ; 0 ;
+; 2 ; 0 ;
+; 3 ; 0 ;
+; 4 ; 0 ;
+; 5 ; 0 ;
+; 6 ; 3 ;
+; 7 ; 0 ;
+; 8 ; 1 ;
+; 9 ; 0 ;
+; 10 ; 0 ;
+; 11 ; 0 ;
+; 12 ; 0 ;
+; 13 ; 0 ;
+; 14 ; 0 ;
+; 15 ; 0 ;
+; 16 ; 1 ;
++-------------------------------------------------+-----------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Distinct Inputs ;
++----------------------------------------------+-----------------------------+
+; Number of Distinct Inputs (Average = 10.00) ; Number of LABs (Total = 5) ;
++----------------------------------------------+-----------------------------+
+; 0 ; 0 ;
+; 1 ; 0 ;
+; 2 ; 0 ;
+; 3 ; 0 ;
+; 4 ; 0 ;
+; 5 ; 0 ;
+; 6 ; 1 ;
+; 7 ; 0 ;
+; 8 ; 0 ;
+; 9 ; 1 ;
+; 10 ; 1 ;
+; 11 ; 1 ;
+; 12 ; 0 ;
+; 13 ; 0 ;
+; 14 ; 1 ;
++----------------------------------------------+-----------------------------+
+
+
++-------------------------------------------------------------------------+
+; Fitter Device Options ;
++----------------------------------------------+--------------------------+
+; Option ; Setting ;
++----------------------------------------------+--------------------------+
+; Enable user-supplied start-up clock (CLKUSR) ; Off ;
+; Enable device-wide reset (DEV_CLRn) ; Off ;
+; Enable device-wide output enable (DEV_OE) ; Off ;
+; Enable INIT_DONE output ; Off ;
+; Configuration scheme ; Active Serial ;
+; Error detection CRC ; Off ;
+; nCEO ; As output driving ground ;
+; Reserve all unused pins ; As input tri-stated ;
+; Base pin-out file on sameframe device ; Off ;
++----------------------------------------------+--------------------------+
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Info: *******************************************************************
+Info: Running Quartus II Fitter
+ Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
+ Info: Processing started: Mon Mar 30 19:52:45 2009
+Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off demo -c demo
+Info: Selected device EP2C35F484C6 for design "demo"
+Info: Implemented PLL "pll:inst1|altpll:altpll_component|pll" as Cyclone II PLL type
+ Info: Implementing clock multiplication of 4, clock division of 1, and phase shift of 0 degrees (0 ps) for pll:inst1|altpll:altpll_component|_clk0 port
+Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Info: Fitter is using the Classic Timing Analyzer
+Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements
+Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
+ Info: Previous placement does not exist for 92 of 92 atoms in partition Top
+Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+ Info: Device EP2C15AF484C6 is compatible
+ Info: Device EP2C20F484C6 is compatible
+ Info: Device EP2C50F484C6 is compatible
+Info: Fitter converted 3 user pins into dedicated programming pins
+ Info: Pin ~ASDO~ is reserved at location C4
+ Info: Pin ~nCSO~ is reserved at location C3
+ Info: Pin ~LVDS150p/nCEO~ is reserved at location W20
+Info: Automatically promoted node pll:inst1|altpll:altpll_component|_clk0 (placed in counter C0 of PLL_1)
+ Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3
+Info: Starting register packing
+Info: Finished register packing: elapsed time is 00:00:01
+ Extra Info: No registers were packed into other blocks
+Info: Fitter placement preparation operations beginning
+Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info: Fitter placement operations beginning
+Info: Fitter placement was successful
+Info: Fitter placement operations ending: elapsed time is 00:00:00
+Info: Estimated most critical path is register to register delay of 6.881 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X57_Y31; Fanout = 3; REG Node = 'demo:inst|counter[3]'
+ Info: 2: + IC(0.914 ns) + CELL(0.414 ns) = 1.328 ns; Loc. = LAB_X55_Y31; Fanout = 2; COMB Node = 'demo:inst|Add0~101'
+ Info: 3: + IC(0.000 ns) + CELL(0.410 ns) = 1.738 ns; Loc. = LAB_X55_Y31; Fanout = 3; COMB Node = 'demo:inst|Add0~102'
+ Info: 4: + IC(0.397 ns) + CELL(0.414 ns) = 2.549 ns; Loc. = LAB_X55_Y31; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[3]~19'
+ Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 2.620 ns; Loc. = LAB_X55_Y31; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[4]~21'
+ Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 2.691 ns; Loc. = LAB_X55_Y31; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[5]~23'
+ Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 2.762 ns; Loc. = LAB_X55_Y31; Fanout = 1; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[6]~25'
+ Info: 8: + IC(0.000 ns) + CELL(0.410 ns) = 3.172 ns; Loc. = LAB_X55_Y31; Fanout = 14; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[7]~26'
+ Info: 9: + IC(0.587 ns) + CELL(0.437 ns) = 4.196 ns; Loc. = LAB_X57_Y31; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[49]~22'
+ Info: 10: + IC(0.397 ns) + CELL(0.414 ns) = 5.007 ns; Loc. = LAB_X57_Y31; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[2]~21'
+ Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 5.078 ns; Loc. = LAB_X57_Y31; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[3]~23'
+ Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 5.149 ns; Loc. = LAB_X57_Y31; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[4]~25'
+ Info: 13: + IC(0.000 ns) + CELL(0.071 ns) = 5.220 ns; Loc. = LAB_X57_Y31; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[5]~27'
+ Info: 14: + IC(0.000 ns) + CELL(0.071 ns) = 5.291 ns; Loc. = LAB_X57_Y31; Fanout = 1; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[6]~29'
+ Info: 15: + IC(0.000 ns) + CELL(0.071 ns) = 5.362 ns; Loc. = LAB_X57_Y31; Fanout = 1; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[7]~31'
+ Info: 16: + IC(0.000 ns) + CELL(0.410 ns) = 5.772 ns; Loc. = LAB_X57_Y31; Fanout = 7; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[8]~32'
+ Info: 17: + IC(0.875 ns) + CELL(0.150 ns) = 6.797 ns; Loc. = LAB_X55_Y31; Fanout = 1; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[57]~636'
+ Info: 18: + IC(0.000 ns) + CELL(0.084 ns) = 6.881 ns; Loc. = LAB_X55_Y31; Fanout = 3; REG Node = 'demo:inst|counter[1]'
+ Info: Total cell delay = 3.711 ns ( 53.93 % )
+ Info: Total interconnect delay = 3.170 ns ( 46.07 % )
+Info: Fitter routing operations beginning
+Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%
+ Info: The peak interconnect region extends from location X22_Y12 to location X32_Y23
+Info: Fitter routing operations ending: elapsed time is 00:00:00
+Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
+ Info: Optimizations that may affect the design's routability were skipped
+ Info: Optimizations that may affect the design's timing were skipped
+Info: Started post-fitting delay annotation
+Warning: Found 8 output pins without output pin load capacitance assignment
+ Info: Pin "LEDS[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "LEDS[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "LEDS[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "LEDS[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "LEDS[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "LEDS[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "LEDS[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "LEDS[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+Info: Delay annotation completed successfully
+Info: Quartus II Fitter was successful. 0 errors, 1 warning
+ Info: Processing ended: Mon Mar 30 19:52:59 2009
+ Info: Elapsed time: 00:00:14
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/demo.fit.smsg.
+
+
--- /dev/null
+Info: *******************************************************************
+Info: Running Quartus II Fitter
+ Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
+ Info: Processing started: Mon Mar 30 19:52:45 2009
+Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off demo -c demo
+Info: Selected device EP2C35F484C6 for design "demo"
+Info: Implemented PLL "pll:inst1|altpll:altpll_component|pll" as Cyclone II PLL type
+ Info: Implementing clock multiplication of 4, clock division of 1, and phase shift of 0 degrees (0 ps) for pll:inst1|altpll:altpll_component|_clk0 port
+Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Info: Fitter is using the Classic Timing Analyzer
+Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements
+Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
+ Info: Previous placement does not exist for 92 of 92 atoms in partition Top
+Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+ Info: Device EP2C15AF484C6 is compatible
+ Info: Device EP2C20F484C6 is compatible
+ Info: Device EP2C50F484C6 is compatible
+Info: Fitter converted 3 user pins into dedicated programming pins
+ Info: Pin ~ASDO~ is reserved at location C4
+ Info: Pin ~nCSO~ is reserved at location C3
+ Info: Pin ~LVDS150p/nCEO~ is reserved at location W20
+Info: Automatically promoted node pll:inst1|altpll:altpll_component|_clk0 (placed in counter C0 of PLL_1)
+ Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3
+Info: Starting register packing
+Info: Finished register packing: elapsed time is 00:00:01
+ Extra Info: No registers were packed into other blocks
+Info: Fitter placement preparation operations beginning
+Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info: Fitter placement operations beginning
+Info: Fitter placement was successful
+Info: Fitter placement operations ending: elapsed time is 00:00:00
+Info: Estimated most critical path is register to register delay of 6.881 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X57_Y31; Fanout = 3; REG Node = 'demo:inst|counter[3]'
+ Info: 2: + IC(0.914 ns) + CELL(0.414 ns) = 1.328 ns; Loc. = LAB_X55_Y31; Fanout = 2; COMB Node = 'demo:inst|Add0~101'
+ Info: 3: + IC(0.000 ns) + CELL(0.410 ns) = 1.738 ns; Loc. = LAB_X55_Y31; Fanout = 3; COMB Node = 'demo:inst|Add0~102'
+ Info: 4: + IC(0.397 ns) + CELL(0.414 ns) = 2.549 ns; Loc. = LAB_X55_Y31; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[3]~19'
+ Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 2.620 ns; Loc. = LAB_X55_Y31; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[4]~21'
+ Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 2.691 ns; Loc. = LAB_X55_Y31; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[5]~23'
+ Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 2.762 ns; Loc. = LAB_X55_Y31; Fanout = 1; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[6]~25'
+ Info: 8: + IC(0.000 ns) + CELL(0.410 ns) = 3.172 ns; Loc. = LAB_X55_Y31; Fanout = 14; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[7]~26'
+ Info: 9: + IC(0.587 ns) + CELL(0.437 ns) = 4.196 ns; Loc. = LAB_X57_Y31; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[49]~22'
+ Info: 10: + IC(0.397 ns) + CELL(0.414 ns) = 5.007 ns; Loc. = LAB_X57_Y31; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[2]~21'
+ Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 5.078 ns; Loc. = LAB_X57_Y31; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[3]~23'
+ Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 5.149 ns; Loc. = LAB_X57_Y31; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[4]~25'
+ Info: 13: + IC(0.000 ns) + CELL(0.071 ns) = 5.220 ns; Loc. = LAB_X57_Y31; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[5]~27'
+ Info: 14: + IC(0.000 ns) + CELL(0.071 ns) = 5.291 ns; Loc. = LAB_X57_Y31; Fanout = 1; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[6]~29'
+ Info: 15: + IC(0.000 ns) + CELL(0.071 ns) = 5.362 ns; Loc. = LAB_X57_Y31; Fanout = 1; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[7]~31'
+ Info: 16: + IC(0.000 ns) + CELL(0.410 ns) = 5.772 ns; Loc. = LAB_X57_Y31; Fanout = 7; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[8]~32'
+ Info: 17: + IC(0.875 ns) + CELL(0.150 ns) = 6.797 ns; Loc. = LAB_X55_Y31; Fanout = 1; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[57]~636'
+ Info: 18: + IC(0.000 ns) + CELL(0.084 ns) = 6.881 ns; Loc. = LAB_X55_Y31; Fanout = 3; REG Node = 'demo:inst|counter[1]'
+ Info: Total cell delay = 3.711 ns ( 53.93 % )
+ Info: Total interconnect delay = 3.170 ns ( 46.07 % )
+Info: Fitter routing operations beginning
+Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%
+ Info: The peak interconnect region extends from location X22_Y12 to location X32_Y23
+Info: Fitter routing operations ending: elapsed time is 00:00:00
+Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
+ Info: Optimizations that may affect the design's routability were skipped
+ Info: Optimizations that may affect the design's timing were skipped
+Info: Started post-fitting delay annotation
+Warning: Found 8 output pins without output pin load capacitance assignment
+ Info: Pin "LEDS[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "LEDS[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "LEDS[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "LEDS[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "LEDS[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "LEDS[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "LEDS[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "LEDS[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+Info: Delay annotation completed successfully
+Info: Quartus II Fitter was successful. 0 errors, 1 warning
+ Info: Processing ended: Mon Mar 30 19:52:59 2009
+ Info: Elapsed time: 00:00:14
--- /dev/null
+Fitter Status : Successful - Mon Mar 30 19:52:59 2009
+Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version
+Revision Name : demo
+Top-level Entity Name : demo_top
+Family : Cyclone II
+Device : EP2C35F484C6
+Timing Models : Final
+Total logic elements : 65 / 33,216 ( < 1 % )
+ Total combinational functions : 65 / 33,216 ( < 1 % )
+ Dedicated logic registers : 16 / 33,216 ( < 1 % )
+Total registers : 16
+Total pins : 10 / 322 ( 3 % )
+Total virtual pins : 0
+Total memory bits : 0 / 483,840 ( 0 % )
+Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % )
+Total PLLs : 1 / 4 ( 25 % )
--- /dev/null
+Flow report for demo
+Mon Mar 30 19:53:36 2009
+Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Flow Summary
+ 3. Flow Settings
+ 4. Flow Non-Default Global Settings
+ 5. Flow Elapsed Time
+ 6. Flow Log
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2007 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++------------------------------------------------------------------------------+
+; Flow Summary ;
++------------------------------------+-----------------------------------------+
+; Flow Status ; Successful - Mon Mar 30 19:53:36 2009 ;
+; Quartus II Version ; 7.0 Build 33 02/05/2007 SJ Full Version ;
+; Revision Name ; demo ;
+; Top-level Entity Name ; demo_top ;
+; Family ; Cyclone II ;
+; Device ; EP2C35F484C6 ;
+; Timing Models ; Final ;
+; Met timing requirements ; Yes ;
+; Total logic elements ; 65 / 33,216 ( < 1 % ) ;
+; Total combinational functions ; 65 / 33,216 ( < 1 % ) ;
+; Dedicated logic registers ; 16 / 33,216 ( < 1 % ) ;
+; Total registers ; 16 ;
+; Total pins ; 10 / 322 ( 3 % ) ;
+; Total virtual pins ; 0 ;
+; Total memory bits ; 0 / 483,840 ( 0 % ) ;
+; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % ) ;
+; Total PLLs ; 1 / 4 ( 25 % ) ;
++------------------------------------+-----------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings ;
++-------------------+---------------------+
+; Option ; Setting ;
++-------------------+---------------------+
+; Start date & time ; 03/30/2009 19:52:35 ;
+; Main task ; Compilation ;
+; Revision Name ; demo ;
++-------------------+---------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings ;
++--------------------------------------------+-----------------------+---------------+-------------+----------------+
+; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
++--------------------------------------------+-----------------------+---------------+-------------+----------------+
+; EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ; On ; -- ; -- ; eda_simulation ;
+; EDA_OUTPUT_DATA_FORMAT ; Vhdl ; -- ; -- ; eda_simulation ;
+; EDA_SIMULATION_RUN_SCRIPT ; ../sim/demo_tb_rtl.do ; -- ; -- ; eda_simulation ;
+; EDA_SIMULATION_TOOL ; ModelSim (VHDL) ; <None> ; -- ; -- ;
+; EDA_TEST_BENCH_ENABLE_STATUS ; NOT_USED ; -- ; -- ; eda_simulation ;
+; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; demo_top ; Top ;
+; TOP_LEVEL_ENTITY ; demo_top ; demo ; -- ; -- ;
++--------------------------------------------+-----------------------+---------------+-------------+----------------+
+
+
++----------------------------------------+
+; Flow Elapsed Time ;
++-------------------------+--------------+
+; Module Name ; Elapsed Time ;
++-------------------------+--------------+
+; Analysis & Synthesis ; 00:00:03 ;
+; Partition Merge ; 00:00:01 ;
+; Fitter ; 00:00:14 ;
+; Assembler ; 00:00:27 ;
+; Classic Timing Analyzer ; 00:00:01 ;
+; EDA Netlist Writer ; 00:00:01 ;
+; Total ; 00:00:47 ;
++-------------------------+--------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off demo -c demo
+quartus_cdb --read_settings_files=off --write_settings_files=off demo -c demo --merge=on
+quartus_fit --read_settings_files=off --write_settings_files=off demo -c demo
+quartus_asm --read_settings_files=off --write_settings_files=off demo -c demo
+quartus_tan --read_settings_files=off --write_settings_files=off demo -c demo --timing_analysis_only
+quartus_eda --read_settings_files=off --write_settings_files=off demo -c demo
+
+
+
--- /dev/null
+Analysis & Synthesis report for demo
+Mon Mar 30 19:52:38 2009
+Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Analysis & Synthesis Summary
+ 3. Analysis & Synthesis Settings
+ 4. Analysis & Synthesis Source Files Read
+ 5. Analysis & Synthesis Resource Usage Summary
+ 6. Analysis & Synthesis Resource Utilization by Entity
+ 7. General Register Statistics
+ 8. Multiplexer Restructuring Statistics (Restructuring Performed)
+ 9. Parameter Settings for User Entity Instance: pll:inst1|altpll:altpll_component
+ 10. Parameter Settings for Inferred Entity Instance: demo:inst|lpm_divide:Mod0
+ 11. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2007 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary ;
++------------------------------------+-----------------------------------------+
+; Analysis & Synthesis Status ; Successful - Mon Mar 30 19:52:38 2009 ;
+; Quartus II Version ; 7.0 Build 33 02/05/2007 SJ Full Version ;
+; Revision Name ; demo ;
+; Top-level Entity Name ; demo_top ;
+; Family ; Cyclone II ;
+; Total logic elements ; 73 ;
+; Total combinational functions ; 73 ;
+; Dedicated logic registers ; 16 ;
+; Total registers ; N/A until Partition Merge ;
+; Total pins ; N/A until Partition Merge ;
+; Total virtual pins ; N/A until Partition Merge ;
+; Total memory bits ; N/A until Partition Merge ;
+; Embedded Multiplier 9-bit elements ; N/A until Partition Merge ;
+; Total PLLs ; N/A until Partition Merge ;
++------------------------------------+-----------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings ;
++--------------------------------------------------------------------+--------------------+--------------------+
+; Option ; Setting ; Default Value ;
++--------------------------------------------------------------------+--------------------+--------------------+
+; Device ; EP2C35F484C6 ; ;
+; Top-level entity name ; demo_top ; demo ;
+; Family name ; Cyclone II ; Stratix ;
+; Type of Retiming Performed During Resynthesis ; Full ; ;
+; Resynthesis Optimization Effort ; Normal ; ;
+; Physical Synthesis Level for Resynthesis ; Normal ; ;
+; Use Generated Physical Constraints File ; On ; ;
+; Restructure Multiplexers ; Auto ; Auto ;
+; Create Debugging Nodes for IP Cores ; Off ; Off ;
+; Preserve fewer node names ; On ; On ;
+; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
+; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
+; VHDL Version ; VHDL93 ; VHDL93 ;
+; State Machine Processing ; Auto ; Auto ;
+; Safe State Machine ; Off ; Off ;
+; Extract Verilog State Machines ; On ; On ;
+; Extract VHDL State Machines ; On ; On ;
+; Ignore Verilog initial constructs ; Off ; Off ;
+; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
+; DSP Block Balancing ; Auto ; Auto ;
+; NOT Gate Push-Back ; On ; On ;
+; Power-Up Don't Care ; On ; On ;
+; Remove Redundant Logic Cells ; Off ; Off ;
+; Remove Duplicate Registers ; On ; On ;
+; Ignore CARRY Buffers ; Off ; Off ;
+; Ignore CASCADE Buffers ; Off ; Off ;
+; Ignore GLOBAL Buffers ; Off ; Off ;
+; Ignore ROW GLOBAL Buffers ; Off ; Off ;
+; Ignore LCELL Buffers ; Off ; Off ;
+; Ignore SOFT Buffers ; On ; On ;
+; Limit AHDL Integers to 32 Bits ; Off ; Off ;
+; Optimization Technique -- Cyclone II ; Balanced ; Balanced ;
+; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70 ; 70 ;
+; Auto Carry Chains ; On ; On ;
+; Auto Open-Drain Pins ; On ; On ;
+; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
+; Perform gate-level register retiming ; Off ; Off ;
+; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
+; Auto ROM Replacement ; On ; On ;
+; Auto RAM Replacement ; On ; On ;
+; Auto Shift Register Replacement ; On ; On ;
+; Auto Clock Enable Replacement ; On ; On ;
+; Allow Synchronous Control Signals ; On ; On ;
+; Force Use of Synchronous Clear Signals ; Off ; Off ;
+; Auto RAM to Logic Cell Conversion ; Off ; Off ;
+; Auto Resource Sharing ; Off ; Off ;
+; Allow Any RAM Size For Recognition ; Off ; Off ;
+; Allow Any ROM Size For Recognition ; Off ; Off ;
+; Allow Any Shift Register Size For Recognition ; Off ; Off ;
+; Ignore translate_off and synthesis_off directives ; Off ; Off ;
+; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
+; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
+; Retiming Meta-Stability Register Sequence Length ; 2 ; 2 ;
+; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
+; HDL message level ; Level2 ; Level2 ;
+; Suppress Register Optimization Related Messages ; Off ; Off ;
+; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
+; Use smart compilation ; Off ; Off ;
++--------------------------------------------------------------------+--------------------+--------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read ;
++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------------------------------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------------------------------+
+; ../src/demo_pkg.vhd ; yes ; User VHDL File ; /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo_pkg.vhd ;
+; ../src/demo.vhd ; yes ; User VHDL File ; /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd ;
+; ../src/pll.vhd ; yes ; User VHDL File ; /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/pll.vhd ;
+; ../src/demo_top.bdf ; yes ; User Block Diagram/Schematic File ; /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo_top.bdf ;
+; altpll.tdf ; yes ; Megafunction ; /opt/quartus/libraries/megafunctions/altpll.tdf ;
+; aglobal70.inc ; yes ; Megafunction ; /opt/quartus/libraries/megafunctions/aglobal70.inc ;
+; stratix_pll.inc ; yes ; Megafunction ; /opt/quartus/libraries/megafunctions/stratix_pll.inc ;
+; stratixii_pll.inc ; yes ; Megafunction ; /opt/quartus/libraries/megafunctions/stratixii_pll.inc ;
+; cycloneii_pll.inc ; yes ; Megafunction ; /opt/quartus/libraries/megafunctions/cycloneii_pll.inc ;
+; lpm_divide.tdf ; yes ; Megafunction ; /opt/quartus/libraries/megafunctions/lpm_divide.tdf ;
+; abs_divider.inc ; yes ; Megafunction ; /opt/quartus/libraries/megafunctions/abs_divider.inc ;
+; sign_div_unsign.inc ; yes ; Megafunction ; /opt/quartus/libraries/megafunctions/sign_div_unsign.inc ;
+; db/lpm_divide_85m.tdf ; yes ; Auto-Generated Megafunction ; /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/lpm_divide_85m.tdf ;
+; db/sign_div_unsign_fkh.tdf ; yes ; Auto-Generated Megafunction ; /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/sign_div_unsign_fkh.tdf ;
+; db/alt_u_div_00f.tdf ; yes ; Auto-Generated Megafunction ; /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf ;
+; db/add_sub_lkc.tdf ; yes ; Auto-Generated Megafunction ; /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/add_sub_lkc.tdf ;
+; db/add_sub_mkc.tdf ; yes ; Auto-Generated Megafunction ; /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/add_sub_mkc.tdf ;
++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary ;
++---------------------------------------------+-----------------------------------------+
+; Resource ; Usage ;
++---------------------------------------------+-----------------------------------------+
+; Estimated Total logic elements ; 73 ;
+; ; ;
+; Total combinational functions ; 73 ;
+; Logic element usage by number of LUT inputs ; ;
+; -- 4 input functions ; 11 ;
+; -- 3 input functions ; 23 ;
+; -- <=2 input functions ; 39 ;
+; ; ;
+; Logic elements by mode ; ;
+; -- normal mode ; 56 ;
+; -- arithmetic mode ; 17 ;
+; ; ;
+; Total registers ; 16 ;
+; -- Dedicated logic registers ; 16 ;
+; -- I/O registers ; 0 ;
+; ; ;
+; I/O pins ; 0 ;
+; Total PLLs ; 1 ;
+; Maximum fan-out node ; pll:inst1|altpll:altpll_component|_clk0 ;
+; Maximum fan-out ; 16 ;
+; Total fan-out ; 233 ;
+; Average fan-out ; 2.33 ;
++---------------------------------------------+-----------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity ;
++-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------------------------------------------+
+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
++-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------------------------------------------+
+; |demo_top ; 73 (0) ; 16 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |demo_top ;
+; |demo:inst| ; 73 (37) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |demo_top|demo:inst ;
+; |lpm_divide:Mod0| ; 36 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |demo_top|demo:inst|lpm_divide:Mod0 ;
+; |lpm_divide_85m:auto_generated| ; 36 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |demo_top|demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated ;
+; |sign_div_unsign_fkh:divider| ; 36 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |demo_top|demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider ;
+; |alt_u_div_00f:divider| ; 36 (36) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |demo_top|demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider ;
+; |pll:inst1| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |demo_top|pll:inst1 ;
+; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |demo_top|pll:inst1|altpll:altpll_component ;
++-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------------------------------------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------+
+; General Register Statistics ;
++----------------------------------------------+-------+
+; Statistic ; Value ;
++----------------------------------------------+-------+
+; Total registers ; 16 ;
+; Number of registers using Synchronous Clear ; 13 ;
+; Number of registers using Synchronous Load ; 3 ;
+; Number of registers using Asynchronous Clear ; 0 ;
+; Number of registers using Asynchronous Load ; 0 ;
+; Number of registers using Clock Enable ; 0 ;
+; Number of registers using Preset ; 0 ;
++----------------------------------------------+-------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed) ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------+
+; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; Yes ; |demo_top|demo:inst|knightlight[7] ;
+; 3:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |demo_top|demo:inst|knightlight[2] ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------+
+
+
++--------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: pll:inst1|altpll:altpll_component ;
++-------------------------------+-------------------+----------------------------+
+; Parameter Name ; Value ; Type ;
++-------------------------------+-------------------+----------------------------+
+; OPERATION_MODE ; NORMAL ; Untyped ;
+; PLL_TYPE ; AUTO ; Untyped ;
+; QUALIFY_CONF_DONE ; OFF ; Untyped ;
+; COMPENSATE_CLOCK ; CLK0 ; Untyped ;
+; SCAN_CHAIN ; LONG ; Untyped ;
+; PRIMARY_CLOCK ; INCLK0 ; Untyped ;
+; INCLK0_INPUT_FREQUENCY ; 40000 ; Signed Integer ;
+; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ;
+; GATE_LOCK_SIGNAL ; NO ; Untyped ;
+; GATE_LOCK_COUNTER ; 0 ; Untyped ;
+; LOCK_HIGH ; 1 ; Untyped ;
+; LOCK_LOW ; 1 ; Untyped ;
+; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ;
+; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ;
+; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ;
+; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ;
+; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ;
+; SKIP_VCO ; OFF ; Untyped ;
+; SWITCH_OVER_COUNTER ; 0 ; Untyped ;
+; SWITCH_OVER_TYPE ; AUTO ; Untyped ;
+; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ;
+; BANDWIDTH ; 0 ; Untyped ;
+; BANDWIDTH_TYPE ; AUTO ; Untyped ;
+; SPREAD_FREQUENCY ; 0 ; Untyped ;
+; DOWN_SPREAD ; 0 ; Untyped ;
+; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ;
+; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ;
+; CLK9_MULTIPLY_BY ; 0 ; Untyped ;
+; CLK8_MULTIPLY_BY ; 0 ; Untyped ;
+; CLK7_MULTIPLY_BY ; 0 ; Untyped ;
+; CLK6_MULTIPLY_BY ; 0 ; Untyped ;
+; CLK5_MULTIPLY_BY ; 1 ; Untyped ;
+; CLK4_MULTIPLY_BY ; 1 ; Untyped ;
+; CLK3_MULTIPLY_BY ; 1 ; Untyped ;
+; CLK2_MULTIPLY_BY ; 1 ; Untyped ;
+; CLK1_MULTIPLY_BY ; 1 ; Untyped ;
+; CLK0_MULTIPLY_BY ; 4 ; Signed Integer ;
+; CLK9_DIVIDE_BY ; 0 ; Untyped ;
+; CLK8_DIVIDE_BY ; 0 ; Untyped ;
+; CLK7_DIVIDE_BY ; 0 ; Untyped ;
+; CLK6_DIVIDE_BY ; 0 ; Untyped ;
+; CLK5_DIVIDE_BY ; 1 ; Untyped ;
+; CLK4_DIVIDE_BY ; 1 ; Untyped ;
+; CLK3_DIVIDE_BY ; 1 ; Untyped ;
+; CLK2_DIVIDE_BY ; 1 ; Untyped ;
+; CLK1_DIVIDE_BY ; 1 ; Untyped ;
+; CLK0_DIVIDE_BY ; 1 ; Signed Integer ;
+; CLK9_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK8_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK7_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK6_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK5_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK4_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK3_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK2_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK1_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK0_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK5_TIME_DELAY ; 0 ; Untyped ;
+; CLK4_TIME_DELAY ; 0 ; Untyped ;
+; CLK3_TIME_DELAY ; 0 ; Untyped ;
+; CLK2_TIME_DELAY ; 0 ; Untyped ;
+; CLK1_TIME_DELAY ; 0 ; Untyped ;
+; CLK0_TIME_DELAY ; 0 ; Untyped ;
+; CLK9_DUTY_CYCLE ; 50 ; Untyped ;
+; CLK8_DUTY_CYCLE ; 50 ; Untyped ;
+; CLK7_DUTY_CYCLE ; 50 ; Untyped ;
+; CLK6_DUTY_CYCLE ; 50 ; Untyped ;
+; CLK5_DUTY_CYCLE ; 50 ; Untyped ;
+; CLK4_DUTY_CYCLE ; 50 ; Untyped ;
+; CLK3_DUTY_CYCLE ; 50 ; Untyped ;
+; CLK2_DUTY_CYCLE ; 50 ; Untyped ;
+; CLK1_DUTY_CYCLE ; 50 ; Untyped ;
+; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ;
+; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; LOCK_WINDOW_UI ; 0.05 ; Untyped ;
+; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ;
+; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ;
+; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ;
+; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ;
+; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ;
+; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ;
+; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ;
+; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ;
+; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ;
+; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ;
+; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ;
+; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ;
+; EXTCLK3_TIME_DELAY ; 0 ; Untyped ;
+; EXTCLK2_TIME_DELAY ; 0 ; Untyped ;
+; EXTCLK1_TIME_DELAY ; 0 ; Untyped ;
+; EXTCLK0_TIME_DELAY ; 0 ; Untyped ;
+; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ;
+; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ;
+; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ;
+; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ;
+; VCO_MULTIPLY_BY ; 0 ; Untyped ;
+; VCO_DIVIDE_BY ; 0 ; Untyped ;
+; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ;
+; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ;
+; VCO_MIN ; 0 ; Untyped ;
+; VCO_MAX ; 0 ; Untyped ;
+; VCO_CENTER ; 0 ; Untyped ;
+; PFD_MIN ; 0 ; Untyped ;
+; PFD_MAX ; 0 ; Untyped ;
+; M_INITIAL ; 0 ; Untyped ;
+; M ; 0 ; Untyped ;
+; N ; 1 ; Untyped ;
+; M2 ; 1 ; Untyped ;
+; N2 ; 1 ; Untyped ;
+; SS ; 1 ; Untyped ;
+; C0_HIGH ; 0 ; Untyped ;
+; C1_HIGH ; 0 ; Untyped ;
+; C2_HIGH ; 0 ; Untyped ;
+; C3_HIGH ; 0 ; Untyped ;
+; C4_HIGH ; 0 ; Untyped ;
+; C5_HIGH ; 0 ; Untyped ;
+; C6_HIGH ; 0 ; Untyped ;
+; C7_HIGH ; 0 ; Untyped ;
+; C8_HIGH ; 0 ; Untyped ;
+; C9_HIGH ; 0 ; Untyped ;
+; C0_LOW ; 0 ; Untyped ;
+; C1_LOW ; 0 ; Untyped ;
+; C2_LOW ; 0 ; Untyped ;
+; C3_LOW ; 0 ; Untyped ;
+; C4_LOW ; 0 ; Untyped ;
+; C5_LOW ; 0 ; Untyped ;
+; C6_LOW ; 0 ; Untyped ;
+; C7_LOW ; 0 ; Untyped ;
+; C8_LOW ; 0 ; Untyped ;
+; C9_LOW ; 0 ; Untyped ;
+; C0_INITIAL ; 0 ; Untyped ;
+; C1_INITIAL ; 0 ; Untyped ;
+; C2_INITIAL ; 0 ; Untyped ;
+; C3_INITIAL ; 0 ; Untyped ;
+; C4_INITIAL ; 0 ; Untyped ;
+; C5_INITIAL ; 0 ; Untyped ;
+; C6_INITIAL ; 0 ; Untyped ;
+; C7_INITIAL ; 0 ; Untyped ;
+; C8_INITIAL ; 0 ; Untyped ;
+; C9_INITIAL ; 0 ; Untyped ;
+; C0_MODE ; BYPASS ; Untyped ;
+; C1_MODE ; BYPASS ; Untyped ;
+; C2_MODE ; BYPASS ; Untyped ;
+; C3_MODE ; BYPASS ; Untyped ;
+; C4_MODE ; BYPASS ; Untyped ;
+; C5_MODE ; BYPASS ; Untyped ;
+; C6_MODE ; BYPASS ; Untyped ;
+; C7_MODE ; BYPASS ; Untyped ;
+; C8_MODE ; BYPASS ; Untyped ;
+; C9_MODE ; BYPASS ; Untyped ;
+; C0_PH ; 0 ; Untyped ;
+; C1_PH ; 0 ; Untyped ;
+; C2_PH ; 0 ; Untyped ;
+; C3_PH ; 0 ; Untyped ;
+; C4_PH ; 0 ; Untyped ;
+; C5_PH ; 0 ; Untyped ;
+; C6_PH ; 0 ; Untyped ;
+; C7_PH ; 0 ; Untyped ;
+; C8_PH ; 0 ; Untyped ;
+; C9_PH ; 0 ; Untyped ;
+; L0_HIGH ; 1 ; Untyped ;
+; L1_HIGH ; 1 ; Untyped ;
+; G0_HIGH ; 1 ; Untyped ;
+; G1_HIGH ; 1 ; Untyped ;
+; G2_HIGH ; 1 ; Untyped ;
+; G3_HIGH ; 1 ; Untyped ;
+; E0_HIGH ; 1 ; Untyped ;
+; E1_HIGH ; 1 ; Untyped ;
+; E2_HIGH ; 1 ; Untyped ;
+; E3_HIGH ; 1 ; Untyped ;
+; L0_LOW ; 1 ; Untyped ;
+; L1_LOW ; 1 ; Untyped ;
+; G0_LOW ; 1 ; Untyped ;
+; G1_LOW ; 1 ; Untyped ;
+; G2_LOW ; 1 ; Untyped ;
+; G3_LOW ; 1 ; Untyped ;
+; E0_LOW ; 1 ; Untyped ;
+; E1_LOW ; 1 ; Untyped ;
+; E2_LOW ; 1 ; Untyped ;
+; E3_LOW ; 1 ; Untyped ;
+; L0_INITIAL ; 1 ; Untyped ;
+; L1_INITIAL ; 1 ; Untyped ;
+; G0_INITIAL ; 1 ; Untyped ;
+; G1_INITIAL ; 1 ; Untyped ;
+; G2_INITIAL ; 1 ; Untyped ;
+; G3_INITIAL ; 1 ; Untyped ;
+; E0_INITIAL ; 1 ; Untyped ;
+; E1_INITIAL ; 1 ; Untyped ;
+; E2_INITIAL ; 1 ; Untyped ;
+; E3_INITIAL ; 1 ; Untyped ;
+; L0_MODE ; BYPASS ; Untyped ;
+; L1_MODE ; BYPASS ; Untyped ;
+; G0_MODE ; BYPASS ; Untyped ;
+; G1_MODE ; BYPASS ; Untyped ;
+; G2_MODE ; BYPASS ; Untyped ;
+; G3_MODE ; BYPASS ; Untyped ;
+; E0_MODE ; BYPASS ; Untyped ;
+; E1_MODE ; BYPASS ; Untyped ;
+; E2_MODE ; BYPASS ; Untyped ;
+; E3_MODE ; BYPASS ; Untyped ;
+; L0_PH ; 0 ; Untyped ;
+; L1_PH ; 0 ; Untyped ;
+; G0_PH ; 0 ; Untyped ;
+; G1_PH ; 0 ; Untyped ;
+; G2_PH ; 0 ; Untyped ;
+; G3_PH ; 0 ; Untyped ;
+; E0_PH ; 0 ; Untyped ;
+; E1_PH ; 0 ; Untyped ;
+; E2_PH ; 0 ; Untyped ;
+; E3_PH ; 0 ; Untyped ;
+; M_PH ; 0 ; Untyped ;
+; C1_USE_CASC_IN ; OFF ; Untyped ;
+; C2_USE_CASC_IN ; OFF ; Untyped ;
+; C3_USE_CASC_IN ; OFF ; Untyped ;
+; C4_USE_CASC_IN ; OFF ; Untyped ;
+; C5_USE_CASC_IN ; OFF ; Untyped ;
+; C6_USE_CASC_IN ; OFF ; Untyped ;
+; C7_USE_CASC_IN ; OFF ; Untyped ;
+; C8_USE_CASC_IN ; OFF ; Untyped ;
+; C9_USE_CASC_IN ; OFF ; Untyped ;
+; CLK0_COUNTER ; G0 ; Untyped ;
+; CLK1_COUNTER ; G0 ; Untyped ;
+; CLK2_COUNTER ; G0 ; Untyped ;
+; CLK3_COUNTER ; G0 ; Untyped ;
+; CLK4_COUNTER ; G0 ; Untyped ;
+; CLK5_COUNTER ; G0 ; Untyped ;
+; L0_TIME_DELAY ; 0 ; Untyped ;
+; L1_TIME_DELAY ; 0 ; Untyped ;
+; G0_TIME_DELAY ; 0 ; Untyped ;
+; G1_TIME_DELAY ; 0 ; Untyped ;
+; G2_TIME_DELAY ; 0 ; Untyped ;
+; G3_TIME_DELAY ; 0 ; Untyped ;
+; E0_TIME_DELAY ; 0 ; Untyped ;
+; E1_TIME_DELAY ; 0 ; Untyped ;
+; E2_TIME_DELAY ; 0 ; Untyped ;
+; E3_TIME_DELAY ; 0 ; Untyped ;
+; M_TIME_DELAY ; 0 ; Untyped ;
+; N_TIME_DELAY ; 0 ; Untyped ;
+; EXTCLK3_COUNTER ; E3 ; Untyped ;
+; EXTCLK2_COUNTER ; E2 ; Untyped ;
+; EXTCLK1_COUNTER ; E1 ; Untyped ;
+; EXTCLK0_COUNTER ; E0 ; Untyped ;
+; ENABLE0_COUNTER ; L0 ; Untyped ;
+; ENABLE1_COUNTER ; L0 ; Untyped ;
+; CHARGE_PUMP_CURRENT ; 2 ; Untyped ;
+; LOOP_FILTER_R ; 1.000000 ; Untyped ;
+; LOOP_FILTER_C ; 5 ; Untyped ;
+; VCO_POST_SCALE ; 0 ; Untyped ;
+; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ;
+; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ;
+; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ;
+; INTENDED_DEVICE_FAMILY ; Cyclone II ; Untyped ;
+; PORT_CLKENA0 ; PORT_UNUSED ; Untyped ;
+; PORT_CLKENA1 ; PORT_UNUSED ; Untyped ;
+; PORT_CLKENA2 ; PORT_UNUSED ; Untyped ;
+; PORT_CLKENA3 ; PORT_UNUSED ; Untyped ;
+; PORT_CLKENA4 ; PORT_UNUSED ; Untyped ;
+; PORT_CLKENA5 ; PORT_UNUSED ; Untyped ;
+; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_EXTCLK0 ; PORT_UNUSED ; Untyped ;
+; PORT_EXTCLK1 ; PORT_UNUSED ; Untyped ;
+; PORT_EXTCLK2 ; PORT_UNUSED ; Untyped ;
+; PORT_EXTCLK3 ; PORT_UNUSED ; Untyped ;
+; PORT_CLKBAD0 ; PORT_UNUSED ; Untyped ;
+; PORT_CLKBAD1 ; PORT_UNUSED ; Untyped ;
+; PORT_CLK0 ; PORT_USED ; Untyped ;
+; PORT_CLK1 ; PORT_UNUSED ; Untyped ;
+; PORT_CLK2 ; PORT_UNUSED ; Untyped ;
+; PORT_CLK3 ; PORT_UNUSED ; Untyped ;
+; PORT_CLK4 ; PORT_UNUSED ; Untyped ;
+; PORT_CLK5 ; PORT_UNUSED ; Untyped ;
+; PORT_CLK6 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CLK7 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CLK8 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CLK9 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_SCANDATA ; PORT_UNUSED ; Untyped ;
+; PORT_SCANDATAOUT ; PORT_UNUSED ; Untyped ;
+; PORT_SCANDONE ; PORT_UNUSED ; Untyped ;
+; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ;
+; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ;
+; PORT_INCLK1 ; PORT_UNUSED ; Untyped ;
+; PORT_INCLK0 ; PORT_USED ; Untyped ;
+; PORT_FBIN ; PORT_UNUSED ; Untyped ;
+; PORT_PLLENA ; PORT_UNUSED ; Untyped ;
+; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ;
+; PORT_ARESET ; PORT_UNUSED ; Untyped ;
+; PORT_PFDENA ; PORT_UNUSED ; Untyped ;
+; PORT_SCANCLK ; PORT_UNUSED ; Untyped ;
+; PORT_SCANACLR ; PORT_UNUSED ; Untyped ;
+; PORT_SCANREAD ; PORT_UNUSED ; Untyped ;
+; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ;
+; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_LOCKED ; PORT_UNUSED ; Untyped ;
+; PORT_CONFIGUPDATE ; PORT_UNUSED ; Untyped ;
+; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_PHASEDONE ; PORT_UNUSED ; Untyped ;
+; PORT_PHASESTEP ; PORT_UNUSED ; Untyped ;
+; PORT_PHASEUPDOWN ; PORT_UNUSED ; Untyped ;
+; PORT_SCANCLKENA ; PORT_UNUSED ; Untyped ;
+; PORT_PHASECOUNTERSELECT ; PORT_UNUSED ; Untyped ;
+; M_TEST_SOURCE ; 5 ; Untyped ;
+; C0_TEST_SOURCE ; 5 ; Untyped ;
+; C1_TEST_SOURCE ; 5 ; Untyped ;
+; C2_TEST_SOURCE ; 5 ; Untyped ;
+; C3_TEST_SOURCE ; 5 ; Untyped ;
+; C4_TEST_SOURCE ; 5 ; Untyped ;
+; C5_TEST_SOURCE ; 5 ; Untyped ;
+; C6_TEST_SOURCE ; 0 ; Untyped ;
+; C7_TEST_SOURCE ; 0 ; Untyped ;
+; C8_TEST_SOURCE ; 0 ; Untyped ;
+; C9_TEST_SOURCE ; 0 ; Untyped ;
+; CBXI_PARAMETER ; NOTHING ; Untyped ;
+; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ;
+; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ;
+; WIDTH_CLOCK ; 6 ; Untyped ;
+; DEVICE_FAMILY ; Cyclone II ; Untyped ;
+; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
+; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
+; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
+; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
++-------------------------------+-------------------+----------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: demo:inst|lpm_divide:Mod0 ;
++------------------------+----------------+----------------------------------+
+; Parameter Name ; Value ; Type ;
++------------------------+----------------+----------------------------------+
+; LPM_WIDTHN ; 8 ; Untyped ;
+; LPM_WIDTHD ; 8 ; Untyped ;
+; LPM_NREPRESENTATION ; UNSIGNED ; Untyped ;
+; LPM_DREPRESENTATION ; UNSIGNED ; Untyped ;
+; LPM_PIPELINE ; 0 ; Untyped ;
+; LPM_REMAINDERPOSITIVE ; TRUE ; Untyped ;
+; MAXIMIZE_SPEED ; 5 ; Untyped ;
+; CBXI_PARAMETER ; lpm_divide_85m ; Untyped ;
+; CARRY_CHAIN ; MANUAL ; Untyped ;
+; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
+; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
+; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
+; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
+; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
++------------------------+----------------+----------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II Analysis & Synthesis
+ Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
+ Info: Processing started: Mon Mar 30 19:52:35 2009
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off demo -c demo
+Info: Found 1 design units, including 0 entities, in source file ../src/demo_pkg.vhd
+ Info: Found design unit 1: demo_pkg
+Info: Found 2 design units, including 1 entities, in source file ../src/demo.vhd
+ Info: Found design unit 1: demo-behav
+ Info: Found entity 1: demo
+Info: Found 2 design units, including 1 entities, in source file ../src/pll.vhd
+ Info: Found design unit 1: pll-SYN
+ Info: Found entity 1: pll
+Info: Found 1 design units, including 1 entities, in source file ../src/demo_top.bdf
+ Info: Found entity 1: demo_top
+Info: Elaborating entity "demo_top" for the top level hierarchy
+Info: Elaborating entity "demo" for hierarchy "demo:inst"
+Info: Elaborating entity "pll" for hierarchy "pll:inst1"
+Info: Found 1 design units, including 1 entities, in source file /opt/quartus/libraries/megafunctions/altpll.tdf
+ Info: Found entity 1: altpll
+Info: Elaborating entity "altpll" for hierarchy "pll:inst1|altpll:altpll_component"
+Info: Elaborated megafunction instantiation "pll:inst1|altpll:altpll_component"
+Info: Found 1 design units, including 1 entities, in source file /opt/quartus/libraries/megafunctions/lpm_divide.tdf
+ Info: Found entity 1: lpm_divide
+Info: Elaborated megafunction instantiation "demo:inst|lpm_divide:Mod0"
+Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_85m.tdf
+ Info: Found entity 1: lpm_divide_85m
+Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_fkh.tdf
+ Info: Found entity 1: sign_div_unsign_fkh
+Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_00f.tdf
+ Info: Found entity 1: alt_u_div_00f
+Info: Found 1 design units, including 1 entities, in source file db/add_sub_lkc.tdf
+ Info: Found entity 1: add_sub_lkc
+Info: Found 1 design units, including 1 entities, in source file db/add_sub_mkc.tdf
+ Info: Found entity 1: add_sub_mkc
+Info: Found the following redundant logic cells in design
+ Info: Logic cell "demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[0]~34"
+Info: Implemented 84 device resources after synthesis - the final resource count might be different
+ Info: Implemented 2 input pins
+ Info: Implemented 8 output pins
+ Info: Implemented 73 logic cells
+ Info: Implemented 1 ClockLock PLLs
+Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
+ Info: Processing ended: Mon Mar 30 19:52:38 2009
+ Info: Elapsed time: 00:00:03
+
+
--- /dev/null
+Analysis & Synthesis Status : Successful - Mon Mar 30 19:52:38 2009
+Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version
+Revision Name : demo
+Top-level Entity Name : demo_top
+Family : Cyclone II
+Total logic elements : 73
+ Total combinational functions : 73
+ Dedicated logic registers : 16
+Total registers : N/A until Partition Merge
+Total pins : N/A until Partition Merge
+Total virtual pins : N/A until Partition Merge
+Total memory bits : N/A until Partition Merge
+Embedded Multiplier 9-bit elements : N/A until Partition Merge
+Total PLLs : N/A until Partition Merge
--- /dev/null
+Partition Merge report for demo
+Mon Mar 30 19:52:42 2009
+Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Partition Merge Summary
+ 3. Partition Merge Netlist Types Used
+ 4. Partition Merge Partition Statistics
+ 5. Partition Merge Resource Usage Summary
+ 6. Partition Merge Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2007 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++------------------------------------------------------------------------------+
+; Partition Merge Summary ;
++------------------------------------+-----------------------------------------+
+; Partition Merge Status ; Successful - Mon Mar 30 19:52:42 2009 ;
+; Quartus II Version ; 7.0 Build 33 02/05/2007 SJ Full Version ;
+; Revision Name ; demo ;
+; Top-level Entity Name ; demo_top ;
+; Family ; Cyclone II ;
+; Total logic elements ; 65 ;
+; Total combinational functions ; 65 ;
+; Dedicated logic registers ; 16 ;
+; Total registers ; 16 ;
+; Total pins ; 10 ;
+; Total virtual pins ; 0 ;
+; Total memory bits ; 0 ;
+; Embedded Multiplier 9-bit elements ; 0 ;
+; Total PLLs ; 1 ;
++------------------------------------+-----------------------------------------+
+
+
++---------------------------------------------------------------------------------------+
+; Partition Merge Netlist Types Used ;
++----------------+------------------------+------------------------+--------------------+
+; Partition Name ; Netlist Type Used ; Netlist Type Requested ; Partition Contents ;
++----------------+------------------------+------------------------+--------------------+
+; Top ; Post-Synthesis Netlist ; Post-Synthesis Netlist ; ;
++----------------+------------------------+------------------------+--------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Partition Merge Partition Statistics ;
++----------------+-------------------------------+-------------+-----------------+-----------------+-------------+--------------+------------------------+-------------------------+-------------------------+--------------------------+---------------------------+------------------------+--------------------+
+; Partition Name ; Total combinational functions ; normal mode ; arithmetic mode ; Total registers ; Input Ports ; Output Ports ; Registered Input Ports ; Registered Output Ports ; Unconnected Input Ports ; Unconnected Output Ports ; Driven Ground Input Ports ; Driven VCC Input Ports ; Partition Contents ;
++----------------+-------------------------------+-------------+-----------------+-----------------+-------------+--------------+------------------------+-------------------------+-------------------------+--------------------------+---------------------------+------------------------+--------------------+
+; Top ; 73 ; 56 ; 17 ; 16 ; 2 ; 8 ; 1 ; 0 ; N/A ; N/A ; N/A ; N/A ; ;
++----------------+-------------------------------+-------------+-----------------+-----------------+-------------+--------------+------------------------+-------------------------+-------------------------+--------------------------+---------------------------+------------------------+--------------------+
+
+
++---------------------------------------------------------------------------------------+
+; Partition Merge Resource Usage Summary ;
++---------------------------------------------+-----------------------------------------+
+; Resource ; Usage ;
++---------------------------------------------+-----------------------------------------+
+; Estimated Total logic elements ; 65 ;
+; ; ;
+; Total combinational functions ; 65 ;
+; Logic element usage by number of LUT inputs ; ;
+; -- 4 input functions ; 11 ;
+; -- 3 input functions ; 23 ;
+; -- <=2 input functions ; 31 ;
+; ; ;
+; Logic elements by mode ; ;
+; -- normal mode ; 48 ;
+; -- arithmetic mode ; 17 ;
+; ; ;
+; Total registers ; 16 ;
+; -- Dedicated logic registers ; 16 ;
+; -- I/O registers ; 0 ;
+; ; ;
+; I/O pins ; 10 ;
+; Total PLLs ; 1 ;
+; Maximum fan-out node ; pll:inst1|altpll:altpll_component|_clk0 ;
+; Maximum fan-out ; 16 ;
+; Total fan-out ; 225 ;
+; Average fan-out ; 2.45 ;
++---------------------------------------------+-----------------------------------------+
+
+
++--------------------------+
+; Partition Merge Messages ;
++--------------------------+
+Info: *******************************************************************
+Info: Running Quartus II Partition Merge
+ Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
+ Info: Processing started: Mon Mar 30 19:52:41 2009
+Info: Command: quartus_cdb --read_settings_files=off --write_settings_files=off demo -c demo --merge=on
+Info: Using synthesis netlist for partition "Top"
+Info: Netlist merging resolved 1 partition(s) out of the 1 partition(s) found
+Info: Quartus II Partition Merge was successful. 0 errors, 0 warnings
+ Info: Processing ended: Mon Mar 30 19:52:42 2009
+ Info: Elapsed time: 00:00:01
+
+
--- /dev/null
+ -- Copyright (C) 1991-2007 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions
+ -- and other software and tools, and its AMPP partner logic
+ -- functions, and any output files from any of the foregoing
+ -- (including device programming or simulation files), and any
+ -- associated documentation or information are expressly subject
+ -- to the terms and conditions of the Altera Program License
+ -- Subscription Agreement, Altera MegaCore Function License
+ -- Agreement, or other applicable license agreement, including,
+ -- without limitation, that your use is for the sole purpose of
+ -- programming logic devices manufactured by Altera and sold by
+ -- Altera or its authorized distributors. Please refer to the
+ -- applicable agreement for further details.
+ --
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC : No Connect. This pin has no internal connection to the device.
+ -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
+ -- VCCIO : Dedicated power pin, which MUST be connected to VCC
+ -- of its bank.
+ -- Bank 1: 3.3V
+ -- Bank 2: 3.3V
+ -- Bank 3: 3.3V
+ -- Bank 4: 3.3V
+ -- Bank 5: 3.3V
+ -- Bank 6: 3.3V
+ -- Bank 7: 3.3V
+ -- Bank 8: 3.3V
+ -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ -- It can also be used to report unused dedicated pins. The connection
+ -- on the board for unused dedicated pins depends on whether this will
+ -- be used in a future design. One example is device migration. When
+ -- using device migration, refer to the device pin-tables. If it is a
+ -- GND pin in the pin table or if it will not be used in a future design
+ -- for another purpose the it MUST be connected to GND. If it is an unused
+ -- dedicated pin, then it can be connected to a valid signal on the board
+ -- (low, high, or toggling) if that signal is required for a different
+ -- revision of the design.
+ -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
+ -- This pin should be connected to GND. It may also be connected to a
+ -- valid signal on the board (low, high, or toggling) if that signal
+ -- is required for a different revision of the design.
+ -- GND* : Unused I/O pin. This pin can either be left unconnected or
+ -- connected to GND. Connecting this pin to GND will improve the
+ -- device's immunity to noise.
+ -- RESERVED : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
+ ---------------------------------------------------------------------------------
+
+Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version
+CHIP "demo" ASSIGNED TO AN: EP2C35F484C6
+
+Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND : A1 : gnd : : : :
+VCCIO3 : A2 : power : : 3.3V : 3 :
+RESERVED_INPUT : A3 : : : : 3 :
+RESERVED_INPUT : A4 : : : : 3 :
+RESERVED_INPUT : A5 : : : : 3 :
+RESERVED_INPUT : A6 : : : : 3 :
+RESERVED_INPUT : A7 : : : : 3 :
+RESERVED_INPUT : A8 : : : : 3 :
+RESERVED_INPUT : A9 : : : : 3 :
+RESERVED_INPUT : A10 : : : : 3 :
+RESERVED_INPUT : A11 : : : : 3 :
+GND+ : A12 : : : : 4 :
+RESERVED_INPUT : A13 : : : : 4 :
+RESERVED_INPUT : A14 : : : : 4 :
+RESERVED_INPUT : A15 : : : : 4 :
+RESERVED_INPUT : A16 : : : : 4 :
+RESERVED_INPUT : A17 : : : : 4 :
+RESERVED_INPUT : A18 : : : : 4 :
+RESERVED_INPUT : A19 : : : : 4 :
+RESERVED_INPUT : A20 : : : : 4 :
+VCCIO4 : A21 : power : : 3.3V : 4 :
+GND : A22 : gnd : : : :
+VCCIO1 : AA1 : power : : 3.3V : 1 :
+GND : AA2 : gnd : : : :
+RESERVED_INPUT : AA3 : : : : 8 :
+RESERVED_INPUT : AA4 : : : : 8 :
+RESERVED_INPUT : AA5 : : : : 8 :
+RESERVED_INPUT : AA6 : : : : 8 :
+RESERVED_INPUT : AA7 : : : : 8 :
+RESERVED_INPUT : AA8 : : : : 8 :
+RESERVED_INPUT : AA9 : : : : 8 :
+RESERVED_INPUT : AA10 : : : : 8 :
+RESERVED_INPUT : AA11 : : : : 8 :
+RESERVED_INPUT : AA12 : : : : 7 :
+RESERVED_INPUT : AA13 : : : : 7 :
+RESERVED_INPUT : AA14 : : : : 7 :
+RESERVED_INPUT : AA15 : : : : 7 :
+RESERVED_INPUT : AA16 : : : : 7 :
+RESERVED_INPUT : AA17 : : : : 7 :
+RESERVED_INPUT : AA18 : : : : 7 :
+RESERVED_INPUT : AA19 : : : : 7 :
+RESERVED_INPUT : AA20 : : : : 7 :
+GND : AA21 : gnd : : : :
+VCCIO6 : AA22 : power : : 3.3V : 6 :
+GND : AB1 : gnd : : : :
+VCCIO8 : AB2 : power : : 3.3V : 8 :
+RESERVED_INPUT : AB3 : : : : 8 :
+RESERVED_INPUT : AB4 : : : : 8 :
+RESERVED_INPUT : AB5 : : : : 8 :
+RESERVED_INPUT : AB6 : : : : 8 :
+RESERVED_INPUT : AB7 : : : : 8 :
+RESERVED_INPUT : AB8 : : : : 8 :
+RESERVED_INPUT : AB9 : : : : 8 :
+RESERVED_INPUT : AB10 : : : : 8 :
+RESERVED_INPUT : AB11 : : : : 8 :
+RESERVED_INPUT : AB12 : : : : 7 :
+RESERVED_INPUT : AB13 : : : : 7 :
+RESERVED_INPUT : AB14 : : : : 7 :
+RESERVED_INPUT : AB15 : : : : 7 :
+RESERVED_INPUT : AB16 : : : : 7 :
+RESERVED_INPUT : AB17 : : : : 7 :
+RESERVED_INPUT : AB18 : : : : 7 :
+RESERVED_INPUT : AB19 : : : : 7 :
+RESERVED_INPUT : AB20 : : : : 7 :
+VCCIO7 : AB21 : power : : 3.3V : 7 :
+GND : AB22 : gnd : : : :
+VCCIO2 : B1 : power : : 3.3V : 2 :
+GND : B2 : gnd : : : :
+RESET : B3 : input : 3.3-V LVTTL : : 3 : Y
+RESERVED_INPUT : B4 : : : : 3 :
+RESERVED_INPUT : B5 : : : : 3 :
+RESERVED_INPUT : B6 : : : : 3 :
+RESERVED_INPUT : B7 : : : : 3 :
+RESERVED_INPUT : B8 : : : : 3 :
+RESERVED_INPUT : B9 : : : : 3 :
+RESERVED_INPUT : B10 : : : : 3 :
+RESERVED_INPUT : B11 : : : : 3 :
+GND+ : B12 : : : : 4 :
+RESERVED_INPUT : B13 : : : : 4 :
+RESERVED_INPUT : B14 : : : : 4 :
+RESERVED_INPUT : B15 : : : : 4 :
+RESERVED_INPUT : B16 : : : : 4 :
+RESERVED_INPUT : B17 : : : : 4 :
+RESERVED_INPUT : B18 : : : : 4 :
+RESERVED_INPUT : B19 : : : : 4 :
+RESERVED_INPUT : B20 : : : : 4 :
+GND : B21 : gnd : : : :
+VCCIO5 : B22 : power : : 3.3V : 5 :
+RESERVED_INPUT : C1 : : : : 2 :
+RESERVED_INPUT : C2 : : : : 2 :
+~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : input : 3.3-V LVTTL : : 2 : N
+~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : input : 3.3-V LVTTL : : 2 : N
+GND : C5 : gnd : : : :
+VCCIO3 : C6 : power : : 3.3V : 3 :
+RESERVED_INPUT : C7 : : : : 3 :
+GND : C8 : gnd : : : :
+RESERVED_INPUT : C9 : : : : 3 :
+RESERVED_INPUT : C10 : : : : 3 :
+VCCIO3 : C11 : power : : 3.3V : 3 :
+VCCIO4 : C12 : power : : 3.3V : 4 :
+RESERVED_INPUT : C13 : : : : 4 :
+RESERVED_INPUT : C14 : : : : 4 :
+GND : C15 : gnd : : : :
+RESERVED_INPUT : C16 : : : : 4 :
+RESERVED_INPUT : C17 : : : : 4 :
+RESERVED_INPUT : C18 : : : : 4 :
+RESERVED_INPUT : C19 : : : : 5 :
+RESERVED_INPUT : C20 : : : : 5 :
+RESERVED_INPUT : C21 : : : : 5 :
+RESERVED_INPUT : C22 : : : : 5 :
+RESERVED_INPUT : D1 : : : : 2 :
+RESERVED_INPUT : D2 : : : : 2 :
+RESERVED_INPUT : D3 : : : : 2 :
+RESERVED_INPUT : D4 : : : : 2 :
+RESERVED_INPUT : D5 : : : : 2 :
+RESERVED_INPUT : D6 : : : : 2 :
+RESERVED_INPUT : D7 : : : : 3 :
+RESERVED_INPUT : D8 : : : : 3 :
+RESERVED_INPUT : D9 : : : : 3 :
+GND : D10 : gnd : : : :
+RESERVED_INPUT : D11 : : : : 3 :
+GND+ : D12 : : : : 3 :
+GND : D13 : gnd : : : :
+RESERVED_INPUT : D14 : : : : 4 :
+RESERVED_INPUT : D15 : : : : 4 :
+RESERVED_INPUT : D16 : : : : 4 :
+VCCIO4 : D17 : power : : 3.3V : 4 :
+GND : D18 : gnd : : : :
+RESERVED_INPUT : D19 : : : : 5 :
+RESERVED_INPUT : D20 : : : : 5 :
+RESERVED_INPUT : D21 : : : : 5 :
+RESERVED_INPUT : D22 : : : : 5 :
+RESERVED_INPUT : E1 : : : : 2 :
+RESERVED_INPUT : E2 : : : : 2 :
+RESERVED_INPUT : E3 : : : : 2 :
+RESERVED_INPUT : E4 : : : : 2 :
+VCCD_PLL3 : E5 : power : : 1.2V : :
+VCCA_PLL3 : E6 : power : : 1.2V : :
+RESERVED_INPUT : E7 : : : : 3 :
+RESERVED_INPUT : E8 : : : : 3 :
+RESERVED_INPUT : E9 : : : : 3 :
+VCCIO3 : E10 : power : : 3.3V : 3 :
+RESERVED_INPUT : E11 : : : : 3 :
+GND+ : E12 : : : : 3 :
+VCCIO4 : E13 : power : : 3.3V : 4 :
+RESERVED_INPUT : E14 : : : : 4 :
+RESERVED_INPUT : E15 : : : : 4 :
+GNDA_PLL2 : E16 : gnd : : : :
+GND_PLL2 : E17 : gnd : : : :
+RESERVED_INPUT : E18 : : : : 5 :
+RESERVED_INPUT : E19 : : : : 5 :
+RESERVED_INPUT : E20 : : : : 5 :
+RESERVED_INPUT : E21 : : : : 5 :
+RESERVED_INPUT : E22 : : : : 5 :
+RESERVED_INPUT : F1 : : : : 2 :
+RESERVED_INPUT : F2 : : : : 2 :
+RESERVED_INPUT : F3 : : : : 2 :
+RESERVED_INPUT : F4 : : : : 2 :
+GND_PLL3 : F5 : gnd : : : :
+GND_PLL3 : F6 : gnd : : : :
+GNDA_PLL3 : F7 : gnd : : : :
+RESERVED_INPUT : F8 : : : : 3 :
+RESERVED_INPUT : F9 : : : : 3 :
+RESERVED_INPUT : F10 : : : : 3 :
+RESERVED_INPUT : F11 : : : : 3 :
+RESERVED_INPUT : F12 : : : : 4 :
+RESERVED_INPUT : F13 : : : : 4 :
+RESERVED_INPUT : F14 : : : : 4 :
+RESERVED_INPUT : F15 : : : : 4 :
+VCCA_PLL2 : F16 : power : : 1.2V : :
+VCCD_PLL2 : F17 : power : : 1.2V : :
+GND_PLL2 : F18 : gnd : : : :
+GND : F19 : gnd : : : :
+RESERVED_INPUT : F20 : : : : 5 :
+RESERVED_INPUT : F21 : : : : 5 :
+RESERVED_INPUT : F22 : : : : 5 :
+RESERVED_INPUT : G1 : : : : 2 :
+RESERVED_INPUT : G2 : : : : 2 :
+RESERVED_INPUT : G3 : : : : 2 :
+GND : G4 : gnd : : : :
+RESERVED_INPUT : G5 : : : : 2 :
+RESERVED_INPUT : G6 : : : : 2 :
+RESERVED_INPUT : G7 : : : : 3 :
+VCCINT : G8 : power : : 1.2V : :
+VCCIO3 : G9 : power : : 3.3V : 3 :
+GND : G10 : gnd : : : :
+RESERVED_INPUT : G11 : : : : 3 :
+VCCINT : G12 : power : : 1.2V : :
+GND : G13 : gnd : : : :
+VCCIO4 : G14 : power : : 3.3V : 4 :
+GND : G15 : gnd : : : :
+RESERVED_INPUT : G16 : : : : 4 :
+RESERVED_INPUT : G17 : : : : 5 :
+RESERVED_INPUT : G18 : : : : 5 :
+VCCIO5 : G19 : power : : 3.3V : 5 :
+RESERVED_INPUT : G20 : : : : 5 :
+RESERVED_INPUT : G21 : : : : 5 :
+RESERVED_INPUT : G22 : : : : 5 :
+RESERVED_INPUT : H1 : : : : 2 :
+RESERVED_INPUT : H2 : : : : 2 :
+RESERVED_INPUT : H3 : : : : 2 :
+RESERVED_INPUT : H4 : : : : 2 :
+RESERVED_INPUT : H5 : : : : 2 :
+RESERVED_INPUT : H6 : : : : 2 :
+RESERVED_INPUT : H7 : : : : 3 :
+VCCINT : H8 : power : : 1.2V : :
+GND : H9 : gnd : : : :
+GND : H10 : gnd : : : :
+RESERVED_INPUT : H11 : : : : 3 :
+VCCINT : H12 : power : : 1.2V : :
+VCCINT : H13 : power : : 1.2V : :
+RESERVED_INPUT : H14 : : : : 4 :
+RESERVED_INPUT : H15 : : : : 4 :
+RESERVED_INPUT : H16 : : : : 5 :
+RESERVED_INPUT : H17 : : : : 5 :
+RESERVED_INPUT : H18 : : : : 5 :
+RESERVED_INPUT : H19 : : : : 5 :
+GND : H20 : gnd : : : :
+RESERVED_INPUT : H21 : : : : 5 :
+RESERVED_INPUT : H22 : : : : 5 :
+RESERVED_INPUT : J1 : : : : 2 :
+RESERVED_INPUT : J2 : : : : 2 :
+RESERVED_INPUT : J3 : : : : 2 :
+RESERVED_INPUT : J4 : : : : 2 :
+RESERVED_INPUT : J5 : : : : 2 :
+RESERVED_INPUT : J6 : : : : 2 :
+VCCIO2 : J7 : power : : 3.3V : 2 :
+GND : J8 : gnd : : : :
+GND : J9 : gnd : : : :
+VCCINT : J10 : power : : 1.2V : :
+VCCINT : J11 : power : : 1.2V : :
+VCCINT : J12 : power : : 1.2V : :
+VCCINT : J13 : power : : 1.2V : :
+RESERVED_INPUT : J14 : : : : 4 :
+RESERVED_INPUT : J15 : : : : 5 :
+VCCIO5 : J16 : power : : 3.3V : 5 :
+RESERVED_INPUT : J17 : : : : 5 :
+RESERVED_INPUT : J18 : : : : 5 :
+RESERVED_INPUT : J19 : : : : 5 :
+RESERVED_INPUT : J20 : : : : 5 :
+RESERVED_INPUT : J21 : : : : 5 :
+RESERVED_INPUT : J22 : : : : 5 :
+nCE : K1 : : : : 2 :
+TCK : K2 : input : : : 2 :
+GND : K3 : gnd : : : :
+DATA0 : K4 : input : : : 2 :
+TDI : K5 : input : : : 2 :
+TMS : K6 : input : : : 2 :
+GND : K7 : gnd : : : :
+VCCINT : K8 : power : : 1.2V : :
+VCCINT : K9 : power : : 1.2V : :
+GND : K10 : gnd : : : :
+GND : K11 : gnd : : : :
+GND : K12 : gnd : : : :
+GND : K13 : gnd : : : :
+VCCINT : K14 : power : : 1.2V : :
+GND : K15 : gnd : : : :
+GND : K16 : gnd : : : :
+RESERVED_INPUT : K17 : : : : 5 :
+RESERVED_INPUT : K18 : : : : 5 :
+GND : K19 : gnd : : : :
+RESERVED_INPUT : K20 : : : : 5 :
+RESERVED_INPUT : K21 : : : : 5 :
+RESERVED_INPUT : K22 : : : : 5 :
+GND+ : L1 : : : : 2 :
+GND+ : L2 : : : : 2 :
+VCCIO2 : L3 : power : : 3.3V : 2 :
+nCONFIG : L4 : : : : 2 :
+TDO : L5 : output : : : 2 :
+DCLK : L6 : : : : 2 :
+RESERVED_INPUT : L7 : : : : 2 :
+RESERVED_INPUT : L8 : : : : 2 :
+VCCINT : L9 : power : : 1.2V : :
+GND : L10 : gnd : : : :
+GND : L11 : gnd : : : :
+GND : L12 : gnd : : : :
+GND : L13 : gnd : : : :
+VCCINT : L14 : power : : 1.2V : :
+GND : L15 : gnd : : : :
+VCCINT : L16 : power : : 1.2V : :
+RESERVED_INPUT : L17 : : : : 5 :
+RESERVED_INPUT : L18 : : : : 5 :
+RESERVED_INPUT : L19 : : : : 5 :
+VCCIO5 : L20 : power : : 3.3V : 5 :
+GND+ : L21 : : : : 5 :
+GND+ : L22 : : : : 5 :
+CLK : M1 : input : 3.3-V LVTTL : : 1 : Y
+GND+ : M2 : : : : 1 :
+VCCIO1 : M3 : power : : 3.3V : 1 :
+GND : M4 : gnd : : : :
+RESERVED_INPUT : M5 : : : : 1 :
+RESERVED_INPUT : M6 : : : : 1 :
+RESERVED_INPUT : M7 : : : : 1 :
+RESERVED_INPUT : M8 : : : : 1 :
+VCCINT : M9 : power : : 1.2V : :
+GND : M10 : gnd : : : :
+GND : M11 : gnd : : : :
+GND : M12 : gnd : : : :
+GND : M13 : gnd : : : :
+VCCINT : M14 : power : : 1.2V : :
+RESERVED_INPUT : M15 : : : : 6 :
+RESERVED_INPUT : M16 : : : : 6 :
+MSEL0 : M17 : : : : 6 :
+RESERVED_INPUT : M18 : : : : 6 :
+RESERVED_INPUT : M19 : : : : 6 :
+VCCIO6 : M20 : power : : 3.3V : 6 :
+GND+ : M21 : : : : 6 :
+GND+ : M22 : : : : 6 :
+RESERVED_INPUT : N1 : : : : 1 :
+RESERVED_INPUT : N2 : : : : 1 :
+RESERVED_INPUT : N3 : : : : 1 :
+RESERVED_INPUT : N4 : : : : 1 :
+RESERVED_INPUT : N5 : : : : 1 :
+RESERVED_INPUT : N6 : : : : 1 :
+GND : N7 : gnd : : : :
+GND : N8 : gnd : : : :
+VCCINT : N9 : power : : 1.2V : :
+GND : N10 : gnd : : : :
+GND : N11 : gnd : : : :
+GND : N12 : gnd : : : :
+GND : N13 : gnd : : : :
+VCCINT : N14 : power : : 1.2V : :
+RESERVED_INPUT : N15 : : : : 6 :
+GND : N16 : gnd : : : :
+MSEL1 : N17 : : : : 6 :
+CONF_DONE : N18 : : : : 6 :
+GND : N19 : gnd : : : :
+nSTATUS : N20 : : : : 6 :
+RESERVED_INPUT : N21 : : : : 6 :
+RESERVED_INPUT : N22 : : : : 6 :
+RESERVED_INPUT : P1 : : : : 1 :
+RESERVED_INPUT : P2 : : : : 1 :
+RESERVED_INPUT : P3 : : : : 1 :
+RESERVED_INPUT : P4 : : : : 1 :
+RESERVED_INPUT : P5 : : : : 1 :
+RESERVED_INPUT : P6 : : : : 1 :
+VCCIO1 : P7 : power : : 3.3V : 1 :
+GND : P8 : gnd : : : :
+GND : P9 : gnd : : : :
+VCCINT : P10 : power : : 1.2V : :
+VCCINT : P11 : power : : 1.2V : :
+VCCINT : P12 : power : : 1.2V : :
+VCCINT : P13 : power : : 1.2V : :
+VCCINT : P14 : power : : 1.2V : :
+RESERVED_INPUT : P15 : : : : 6 :
+VCCIO6 : P16 : power : : 3.3V : 6 :
+RESERVED_INPUT : P17 : : : : 6 :
+RESERVED_INPUT : P18 : : : : 6 :
+RESERVED_INPUT : P19 : : : : 6 :
+RESERVED_INPUT : P20 : : : : 6 :
+RESERVED_INPUT : P21 : : : : 6 :
+RESERVED_INPUT : P22 : : : : 6 :
+RESERVED_INPUT : R1 : : : : 1 :
+RESERVED_INPUT : R2 : : : : 1 :
+GND : R3 : gnd : : : :
+RESERVED_INPUT : R4 : : : : 1 :
+RESERVED_INPUT : R5 : : : : 1 :
+RESERVED_INPUT : R6 : : : : 1 :
+RESERVED_INPUT : R7 : : : : 1 :
+RESERVED_INPUT : R8 : : : : 1 :
+GND : R9 : gnd : : : :
+VCCINT : R10 : power : : 1.2V : :
+RESERVED_INPUT : R11 : : : : 8 :
+VCCINT : R12 : power : : 1.2V : :
+GND : R13 : gnd : : : :
+RESERVED_INPUT : R14 : : : : 7 :
+RESERVED_INPUT : R15 : : : : 7 :
+RESERVED_INPUT : R16 : : : : 7 :
+RESERVED_INPUT : R17 : : : : 6 :
+RESERVED_INPUT : R18 : : : : 6 :
+RESERVED_INPUT : R19 : : : : 6 :
+RESERVED_INPUT : R20 : : : : 6 :
+RESERVED_INPUT : R21 : : : : 6 :
+RESERVED_INPUT : R22 : : : : 6 :
+RESERVED_INPUT : T1 : : : : 1 :
+RESERVED_INPUT : T2 : : : : 1 :
+RESERVED_INPUT : T3 : : : : 1 :
+VCCIO1 : T4 : power : : 3.3V : 1 :
+RESERVED_INPUT : T5 : : : : 1 :
+RESERVED_INPUT : T6 : : : : 1 :
+RESERVED_INPUT : T7 : : : : 8 :
+RESERVED_INPUT : T8 : : : : 8 :
+VCCIO8 : T9 : power : : 3.3V : 8 :
+GND : T10 : gnd : : : :
+RESERVED_INPUT : T11 : : : : 8 :
+VCCINT : T12 : power : : 1.2V : :
+GND : T13 : gnd : : : :
+VCCIO7 : T14 : power : : 3.3V : 7 :
+VCCINT : T15 : power : : 1.2V : :
+RESERVED_INPUT : T16 : : : : 7 :
+GND_PLL4 : T17 : gnd : : : :
+RESERVED_INPUT : T18 : : : : 6 :
+VCCIO6 : T19 : power : : 3.3V : 6 :
+GND : T20 : gnd : : : :
+RESERVED_INPUT : T21 : : : : 6 :
+RESERVED_INPUT : T22 : : : : 6 :
+LEDS[7] : U1 : output : 3.3-V LVTTL : : 1 : Y
+RESERVED_INPUT : U2 : : : : 1 :
+RESERVED_INPUT : U3 : : : : 1 :
+RESERVED_INPUT : U4 : : : : 1 :
+GND_PLL1 : U5 : gnd : : : :
+VCCD_PLL1 : U6 : power : : 1.2V : :
+VCCA_PLL1 : U7 : power : : 1.2V : :
+RESERVED_INPUT : U8 : : : : 8 :
+RESERVED_INPUT : U9 : : : : 8 :
+RESERVED_INPUT : U10 : : : : 8 :
+GND+ : U11 : : : : 8 :
+GND+ : U12 : : : : 8 :
+RESERVED_INPUT : U13 : : : : 7 :
+RESERVED_INPUT : U14 : : : : 7 :
+RESERVED_INPUT : U15 : : : : 7 :
+VCCA_PLL4 : U16 : power : : 1.2V : :
+VCCD_PLL4 : U17 : power : : 1.2V : :
+RESERVED_INPUT : U18 : : : : 6 :
+RESERVED_INPUT : U19 : : : : 6 :
+RESERVED_INPUT : U20 : : : : 6 :
+RESERVED_INPUT : U21 : : : : 6 :
+RESERVED_INPUT : U22 : : : : 6 :
+LEDS[6] : V1 : output : 3.3-V LVTTL : : 1 : Y
+LEDS[5] : V2 : output : 3.3-V LVTTL : : 1 : Y
+GND : V3 : gnd : : : :
+RESERVED_INPUT : V4 : : : : 1 :
+GND_PLL1 : V5 : gnd : : : :
+GND : V6 : gnd : : : :
+GNDA_PLL1 : V7 : gnd : : : :
+RESERVED_INPUT : V8 : : : : 8 :
+RESERVED_INPUT : V9 : : : : 8 :
+VCCIO8 : V10 : power : : 3.3V : 8 :
+RESERVED_INPUT : V11 : : : : 8 :
+GND+ : V12 : : : : 7 :
+VCCIO7 : V13 : power : : 3.3V : 7 :
+RESERVED_INPUT : V14 : : : : 7 :
+RESERVED_INPUT : V15 : : : : 7 :
+GNDA_PLL4 : V16 : gnd : : : :
+GND : V17 : gnd : : : :
+GND_PLL4 : V18 : gnd : : : :
+RESERVED_INPUT : V19 : : : : 6 :
+RESERVED_INPUT : V20 : : : : 6 :
+RESERVED_INPUT : V21 : : : : 6 :
+RESERVED_INPUT : V22 : : : : 6 :
+LEDS[4] : W1 : output : 3.3-V LVTTL : : 1 : Y
+LEDS[3] : W2 : output : 3.3-V LVTTL : : 1 : Y
+LEDS[2] : W3 : output : 3.3-V LVTTL : : 1 : Y
+LEDS[1] : W4 : output : 3.3-V LVTTL : : 1 : Y
+LEDS[0] : W5 : output : 3.3-V LVTTL : : 1 : Y
+VCCIO8 : W6 : power : : 3.3V : 8 :
+RESERVED_INPUT : W7 : : : : 8 :
+RESERVED_INPUT : W8 : : : : 8 :
+RESERVED_INPUT : W9 : : : : 8 :
+GND : W10 : gnd : : : :
+RESERVED_INPUT : W11 : : : : 8 :
+GND+ : W12 : : : : 7 :
+GND : W13 : gnd : : : :
+RESERVED_INPUT : W14 : : : : 7 :
+RESERVED_INPUT : W15 : : : : 7 :
+RESERVED_INPUT : W16 : : : : 7 :
+VCCIO7 : W17 : power : : 3.3V : 7 :
+RESERVED_INPUT : W18 : : : : 6 :
+GND : W19 : gnd : : : :
+~LVDS150p/nCEO~ : W20 : output : 3.3-V LVTTL : : 6 : N
+RESERVED_INPUT : W21 : : : : 6 :
+RESERVED_INPUT : W22 : : : : 6 :
+RESERVED_INPUT : Y1 : : : : 1 :
+RESERVED_INPUT : Y2 : : : : 1 :
+RESERVED_INPUT : Y3 : : : : 1 :
+RESERVED_INPUT : Y4 : : : : 1 :
+RESERVED_INPUT : Y5 : : : : 8 :
+RESERVED_INPUT : Y6 : : : : 8 :
+RESERVED_INPUT : Y7 : : : : 8 :
+GND : Y8 : gnd : : : :
+RESERVED_INPUT : Y9 : : : : 8 :
+RESERVED_INPUT : Y10 : : : : 8 :
+VCCIO8 : Y11 : power : : 3.3V : 8 :
+VCCIO7 : Y12 : power : : 3.3V : 7 :
+RESERVED_INPUT : Y13 : : : : 7 :
+RESERVED_INPUT : Y14 : : : : 7 :
+GND : Y15 : gnd : : : :
+RESERVED_INPUT : Y16 : : : : 7 :
+RESERVED_INPUT : Y17 : : : : 7 :
+RESERVED_INPUT : Y18 : : : : 6 :
+RESERVED_INPUT : Y19 : : : : 6 :
+RESERVED_INPUT : Y20 : : : : 6 :
+RESERVED_INPUT : Y21 : : : : 6 :
+RESERVED_INPUT : Y22 : : : : 6 :
--- /dev/null
+# Copyright (C) 1991-2007 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+
+
+
+QUARTUS_VERSION = "7.0"
+DATE = "17:09:40 March 24, 2009"
+
+
+# Revisions
+
+PROJECT_REVISION = "demo"
--- /dev/null
+# Copyright (C) 1991-2007 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+
+
+# The default values for assignments are stored in the file
+# demo_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+# assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+set_global_assignment -name DEVICE EP2C35F484C6
+set_global_assignment -name FAMILY "Cyclone II"
+set_global_assignment -name TOP_LEVEL_ENTITY demo_top
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:09:40 MARCH 24, 2009"
+set_global_assignment -name LAST_QUARTUS_VERSION 7.0
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"
+set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id eda_simulation
+set_global_assignment -name EDA_SIMULATION_RUN_SCRIPT ../sim/demo_tb_rtl.do -section_id eda_simulation
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
+set_global_assignment -name VHDL_FILE ../src/demo_pkg.vhd
+set_global_assignment -name VHDL_FILE ../src/demo.vhd
+set_global_assignment -name VHDL_FILE ../src/pll.vhd
+set_global_assignment -name BDF_FILE ../src/demo_top.bdf
+set_location_assignment PIN_M1 -to CLK
+set_location_assignment PIN_B3 -to RESET
+set_location_assignment PIN_W5 -to LEDS[0]
+set_location_assignment PIN_W4 -to LEDS[1]
+set_location_assignment PIN_W3 -to LEDS[2]
+set_location_assignment PIN_W2 -to LEDS[3]
+set_location_assignment PIN_W1 -to LEDS[4]
+set_location_assignment PIN_V2 -to LEDS[5]
+set_location_assignment PIN_V1 -to LEDS[6]
+set_location_assignment PIN_U1 -to LEDS[7]
\ No newline at end of file
--- /dev/null
+
+
+[ProjectWorkspace]
+ptn_Child1=Frames
+
+[ProjectWorkspace.Frames]
+ptn_Child1=ChildFrames
+
+[ProjectWorkspace.Frames.ChildFrames]
+ptn_Child1=Document-0
+ptn_Child2=Document-1
\ No newline at end of file
--- /dev/null
+Classic Timing Analyzer report for demo
+Mon Mar 30 19:53:32 2009
+Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Timing Analyzer Summary
+ 3. Timing Analyzer Settings
+ 4. Clock Settings Summary
+ 5. Clock Setup: 'pll:inst1|altpll:altpll_component|_clk0'
+ 6. Clock Hold: 'pll:inst1|altpll:altpll_component|_clk0'
+ 7. tsu
+ 8. tco
+ 9. th
+ 10. Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2007 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Timing Analyzer Summary ;
++--------------------------------------------------------+----------+-----------------------------------+----------------------------------+--------------------------+--------------------------+-----------------------------------------+-----------------------------------------+--------------+
+; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
++--------------------------------------------------------+----------+-----------------------------------+----------------------------------+--------------------------+--------------------------+-----------------------------------------+-----------------------------------------+--------------+
+; Worst-case tsu ; N/A ; None ; 7.774 ns ; RESET ; demo:inst|knightlight[5] ; -- ; CLK ; 0 ;
+; Worst-case tco ; N/A ; None ; 9.507 ns ; demo:inst|knightlight[0] ; LEDS[0] ; CLK ; -- ; 0 ;
+; Worst-case th ; N/A ; None ; -7.313 ns ; RESET ; demo:inst|counter[2] ; -- ; CLK ; 0 ;
+; Clock Setup: 'pll:inst1|altpll:altpll_component|_clk0' ; 3.604 ns ; 100.00 MHz ( period = 10.000 ns ) ; 156.35 MHz ( period = 6.396 ns ) ; demo:inst|counter[3] ; demo:inst|counter[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0 ;
+; Clock Hold: 'pll:inst1|altpll:altpll_component|_clk0' ; 0.391 ns ; 100.00 MHz ( period = 10.000 ns ) ; N/A ; demo:inst|knightlight[5] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0 ;
+; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
++--------------------------------------------------------+----------+-----------------------------------+----------------------------------+--------------------------+--------------------------+-----------------------------------------+-----------------------------------------+--------------+
+
+
++------------------------------------------------------------------------------------------------------+
+; Timing Analyzer Settings ;
++-------------------------------------------------------+--------------------+------+----+-------------+
+; Option ; Setting ; From ; To ; Entity Name ;
++-------------------------------------------------------+--------------------+------+----+-------------+
+; Device Name ; EP2C35F484C6 ; ; ; ;
+; Timing Models ; Final ; ; ; ;
+; Default hold multicycle ; Same as Multicycle ; ; ; ;
+; Cut paths between unrelated clock domains ; On ; ; ; ;
+; Cut off read during write signal paths ; On ; ; ; ;
+; Cut off feedback from I/O pins ; On ; ; ; ;
+; Report Combined Fast/Slow Timing ; Off ; ; ; ;
+; Ignore Clock Settings ; Off ; ; ; ;
+; Analyze latches as synchronous elements ; On ; ; ; ;
+; Enable Recovery/Removal analysis ; Off ; ; ; ;
+; Enable Clock Latency ; Off ; ; ; ;
+; Number of source nodes to report per destination node ; 10 ; ; ; ;
+; Number of destination nodes to report ; 10 ; ; ; ;
+; Number of paths to report ; 200 ; ; ; ;
+; Report Minimum Timing Checks ; Off ; ; ; ;
+; Use Fast Timing Models ; Off ; ; ; ;
+; Report IO Paths Separately ; Off ; ; ; ;
++-------------------------------------------------------+--------------------+------+----+-------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Settings Summary ;
++-----------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
+; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
++-----------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
+; pll:inst1|altpll:altpll_component|_clk0 ; ; PLL output ; 100.0 MHz ; 0.000 ns ; 0.000 ns ; CLK ; 4 ; 1 ; -2.378 ns ; ;
+; CLK ; ; User Pin ; 25.0 MHz ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
++-----------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Setup: 'pll:inst1|altpll:altpll_component|_clk0' ;
++----------+---------------------------------------------+--------------------------+--------------------------+-----------------------------------------+-----------------------------------------+-----------------------------+---------------------------+-------------------------+
+; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
++----------+---------------------------------------------+--------------------------+--------------------------+-----------------------------------------+-----------------------------------------+-----------------------------+---------------------------+-------------------------+
+; 3.604 ns ; 156.35 MHz ( period = 6.396 ns ) ; demo:inst|counter[3] ; demo:inst|counter[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 6.182 ns ;
+; 3.606 ns ; 156.40 MHz ( period = 6.394 ns ) ; demo:inst|counter[3] ; demo:inst|counter[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 6.180 ns ;
+; 3.607 ns ; 156.42 MHz ( period = 6.393 ns ) ; demo:inst|counter[3] ; demo:inst|counter[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 6.179 ns ;
+; 3.608 ns ; 156.45 MHz ( period = 6.392 ns ) ; demo:inst|counter[0] ; demo:inst|counter[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 6.178 ns ;
+; 3.610 ns ; 156.49 MHz ( period = 6.390 ns ) ; demo:inst|counter[0] ; demo:inst|counter[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 6.176 ns ;
+; 3.611 ns ; 156.52 MHz ( period = 6.389 ns ) ; demo:inst|counter[0] ; demo:inst|counter[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 6.175 ns ;
+; 3.725 ns ; 159.36 MHz ( period = 6.275 ns ) ; demo:inst|counter[4] ; demo:inst|counter[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 6.061 ns ;
+; 3.727 ns ; 159.41 MHz ( period = 6.273 ns ) ; demo:inst|counter[4] ; demo:inst|counter[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 6.059 ns ;
+; 3.728 ns ; 159.44 MHz ( period = 6.272 ns ) ; demo:inst|counter[4] ; demo:inst|counter[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 6.058 ns ;
+; 3.753 ns ; 160.08 MHz ( period = 6.247 ns ) ; demo:inst|counter[5] ; demo:inst|counter[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 6.033 ns ;
+; 3.755 ns ; 160.13 MHz ( period = 6.245 ns ) ; demo:inst|counter[5] ; demo:inst|counter[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 6.031 ns ;
+; 3.756 ns ; 160.15 MHz ( period = 6.244 ns ) ; demo:inst|counter[5] ; demo:inst|counter[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 6.030 ns ;
+; 3.809 ns ; 161.52 MHz ( period = 6.191 ns ) ; demo:inst|counter[1] ; demo:inst|counter[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.977 ns ;
+; 3.811 ns ; 161.58 MHz ( period = 6.189 ns ) ; demo:inst|counter[1] ; demo:inst|counter[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.975 ns ;
+; 3.812 ns ; 161.60 MHz ( period = 6.188 ns ) ; demo:inst|counter[1] ; demo:inst|counter[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.974 ns ;
+; 3.863 ns ; 162.95 MHz ( period = 6.137 ns ) ; demo:inst|counter[6] ; demo:inst|counter[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.923 ns ;
+; 3.865 ns ; 163.00 MHz ( period = 6.135 ns ) ; demo:inst|counter[6] ; demo:inst|counter[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.921 ns ;
+; 3.866 ns ; 163.03 MHz ( period = 6.134 ns ) ; demo:inst|counter[6] ; demo:inst|counter[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.920 ns ;
+; 3.903 ns ; 164.02 MHz ( period = 6.097 ns ) ; demo:inst|counter[3] ; demo:inst|counter[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.883 ns ;
+; 3.907 ns ; 164.12 MHz ( period = 6.093 ns ) ; demo:inst|counter[0] ; demo:inst|counter[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.879 ns ;
+; 3.979 ns ; 166.09 MHz ( period = 6.021 ns ) ; demo:inst|counter[2] ; demo:inst|counter[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.807 ns ;
+; 3.981 ns ; 166.14 MHz ( period = 6.019 ns ) ; demo:inst|counter[2] ; demo:inst|counter[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.805 ns ;
+; 3.982 ns ; 166.17 MHz ( period = 6.018 ns ) ; demo:inst|counter[2] ; demo:inst|counter[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.804 ns ;
+; 4.012 ns ; 167.00 MHz ( period = 5.988 ns ) ; demo:inst|counter[3] ; demo:inst|counter[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.774 ns ;
+; 4.013 ns ; 167.03 MHz ( period = 5.987 ns ) ; demo:inst|counter[3] ; demo:inst|counter[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.773 ns ;
+; 4.015 ns ; 167.08 MHz ( period = 5.985 ns ) ; demo:inst|counter[3] ; demo:inst|counter[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.771 ns ;
+; 4.016 ns ; 167.11 MHz ( period = 5.984 ns ) ; demo:inst|counter[0] ; demo:inst|counter[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.770 ns ;
+; 4.017 ns ; 167.14 MHz ( period = 5.983 ns ) ; demo:inst|counter[0] ; demo:inst|counter[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.769 ns ;
+; 4.019 ns ; 167.20 MHz ( period = 5.981 ns ) ; demo:inst|counter[0] ; demo:inst|counter[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.767 ns ;
+; 4.024 ns ; 167.34 MHz ( period = 5.976 ns ) ; demo:inst|counter[4] ; demo:inst|counter[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.762 ns ;
+; 4.052 ns ; 168.12 MHz ( period = 5.948 ns ) ; demo:inst|counter[5] ; demo:inst|counter[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.734 ns ;
+; 4.108 ns ; 169.72 MHz ( period = 5.892 ns ) ; demo:inst|counter[1] ; demo:inst|counter[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.678 ns ;
+; 4.133 ns ; 170.44 MHz ( period = 5.867 ns ) ; demo:inst|counter[4] ; demo:inst|counter[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.653 ns ;
+; 4.134 ns ; 170.47 MHz ( period = 5.866 ns ) ; demo:inst|counter[4] ; demo:inst|counter[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.652 ns ;
+; 4.136 ns ; 170.53 MHz ( period = 5.864 ns ) ; demo:inst|counter[4] ; demo:inst|counter[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.650 ns ;
+; 4.161 ns ; 171.26 MHz ( period = 5.839 ns ) ; demo:inst|counter[5] ; demo:inst|counter[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.625 ns ;
+; 4.162 ns ; 171.29 MHz ( period = 5.838 ns ) ; demo:inst|counter[5] ; demo:inst|counter[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.624 ns ;
+; 4.162 ns ; 171.29 MHz ( period = 5.838 ns ) ; demo:inst|counter[6] ; demo:inst|counter[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.624 ns ;
+; 4.164 ns ; 171.35 MHz ( period = 5.836 ns ) ; demo:inst|counter[5] ; demo:inst|counter[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.622 ns ;
+; 4.217 ns ; 172.92 MHz ( period = 5.783 ns ) ; demo:inst|counter[1] ; demo:inst|counter[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.569 ns ;
+; 4.218 ns ; 172.95 MHz ( period = 5.782 ns ) ; demo:inst|counter[1] ; demo:inst|counter[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.568 ns ;
+; 4.220 ns ; 173.01 MHz ( period = 5.780 ns ) ; demo:inst|counter[1] ; demo:inst|counter[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.566 ns ;
+; 4.271 ns ; 174.55 MHz ( period = 5.729 ns ) ; demo:inst|counter[6] ; demo:inst|counter[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.515 ns ;
+; 4.272 ns ; 174.58 MHz ( period = 5.728 ns ) ; demo:inst|counter[6] ; demo:inst|counter[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.514 ns ;
+; 4.274 ns ; 174.64 MHz ( period = 5.726 ns ) ; demo:inst|counter[6] ; demo:inst|counter[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.512 ns ;
+; 4.278 ns ; 174.76 MHz ( period = 5.722 ns ) ; demo:inst|counter[2] ; demo:inst|counter[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.508 ns ;
+; 4.387 ns ; 178.16 MHz ( period = 5.613 ns ) ; demo:inst|counter[2] ; demo:inst|counter[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.399 ns ;
+; 4.388 ns ; 178.19 MHz ( period = 5.612 ns ) ; demo:inst|counter[2] ; demo:inst|counter[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.398 ns ;
+; 4.390 ns ; 178.25 MHz ( period = 5.610 ns ) ; demo:inst|counter[2] ; demo:inst|counter[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 5.396 ns ;
+; 4.740 ns ; 190.11 MHz ( period = 5.260 ns ) ; demo:inst|counter[4] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 4.998 ns ;
+; 4.959 ns ; 198.37 MHz ( period = 5.041 ns ) ; demo:inst|counter[3] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 4.779 ns ;
+; 5.075 ns ; 203.05 MHz ( period = 4.925 ns ) ; demo:inst|counter[6] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 4.663 ns ;
+; 5.098 ns ; 204.00 MHz ( period = 4.902 ns ) ; demo:inst|knightlight[3] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 4.688 ns ;
+; 5.177 ns ; 207.34 MHz ( period = 4.823 ns ) ; demo:inst|counter[0] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 4.561 ns ;
+; 5.337 ns ; 214.45 MHz ( period = 4.663 ns ) ; demo:inst|counter[1] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 4.401 ns ;
+; 5.484 ns ; 221.43 MHz ( period = 4.516 ns ) ; demo:inst|counter[2] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 4.254 ns ;
+; 5.491 ns ; 221.78 MHz ( period = 4.509 ns ) ; demo:inst|counter[5] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 4.247 ns ;
+; 5.761 ns ; 235.90 MHz ( period = 4.239 ns ) ; demo:inst|counter[4] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.977 ns ;
+; 5.763 ns ; 236.02 MHz ( period = 4.237 ns ) ; demo:inst|counter[4] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.975 ns ;
+; 5.764 ns ; 236.07 MHz ( period = 4.236 ns ) ; demo:inst|counter[4] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.974 ns ;
+; 5.980 ns ; 248.76 MHz ( period = 4.020 ns ) ; demo:inst|counter[3] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.758 ns ;
+; 5.982 ns ; 248.88 MHz ( period = 4.018 ns ) ; demo:inst|counter[3] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.756 ns ;
+; 5.983 ns ; 248.94 MHz ( period = 4.017 ns ) ; demo:inst|counter[3] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.755 ns ;
+; 6.008 ns ; 250.50 MHz ( period = 3.992 ns ) ; demo:inst|counter[4] ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.730 ns ;
+; 6.009 ns ; 250.56 MHz ( period = 3.991 ns ) ; demo:inst|counter[4] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.729 ns ;
+; 6.039 ns ; 252.46 MHz ( period = 3.961 ns ) ; demo:inst|knightlight[2] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.740 ns ; 3.701 ns ;
+; 6.096 ns ; 256.15 MHz ( period = 3.904 ns ) ; demo:inst|counter[6] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.642 ns ;
+; 6.098 ns ; 256.28 MHz ( period = 3.902 ns ) ; demo:inst|counter[6] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.640 ns ;
+; 6.099 ns ; 256.34 MHz ( period = 3.901 ns ) ; demo:inst|counter[6] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.639 ns ;
+; 6.198 ns ; 263.02 MHz ( period = 3.802 ns ) ; demo:inst|counter[0] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.540 ns ;
+; 6.200 ns ; 263.16 MHz ( period = 3.800 ns ) ; demo:inst|counter[0] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.538 ns ;
+; 6.201 ns ; 263.23 MHz ( period = 3.799 ns ) ; demo:inst|counter[0] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.537 ns ;
+; 6.227 ns ; 265.04 MHz ( period = 3.773 ns ) ; demo:inst|counter[3] ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.511 ns ;
+; 6.228 ns ; 265.11 MHz ( period = 3.772 ns ) ; demo:inst|counter[3] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.510 ns ;
+; 6.343 ns ; 273.45 MHz ( period = 3.657 ns ) ; demo:inst|counter[6] ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.395 ns ;
+; 6.344 ns ; 273.52 MHz ( period = 3.656 ns ) ; demo:inst|counter[6] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.394 ns ;
+; 6.358 ns ; 274.57 MHz ( period = 3.642 ns ) ; demo:inst|counter[1] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.380 ns ;
+; 6.360 ns ; 274.73 MHz ( period = 3.640 ns ) ; demo:inst|counter[1] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.378 ns ;
+; 6.361 ns ; 274.80 MHz ( period = 3.639 ns ) ; demo:inst|counter[1] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.377 ns ;
+; 6.445 ns ; 281.29 MHz ( period = 3.555 ns ) ; demo:inst|counter[0] ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.293 ns ;
+; 6.446 ns ; 281.37 MHz ( period = 3.554 ns ) ; demo:inst|counter[0] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.292 ns ;
+; 6.505 ns ; 286.12 MHz ( period = 3.495 ns ) ; demo:inst|counter[2] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.233 ns ;
+; 6.507 ns ; 286.29 MHz ( period = 3.493 ns ) ; demo:inst|counter[2] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.231 ns ;
+; 6.508 ns ; 286.37 MHz ( period = 3.492 ns ) ; demo:inst|counter[2] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.230 ns ;
+; 6.512 ns ; 286.70 MHz ( period = 3.488 ns ) ; demo:inst|counter[5] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.226 ns ;
+; 6.514 ns ; 286.86 MHz ( period = 3.486 ns ) ; demo:inst|counter[5] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.224 ns ;
+; 6.515 ns ; 286.94 MHz ( period = 3.485 ns ) ; demo:inst|counter[5] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.223 ns ;
+; 6.531 ns ; 288.27 MHz ( period = 3.469 ns ) ; demo:inst|knightlight[3] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.832 ns ; 3.301 ns ;
+; 6.605 ns ; 294.55 MHz ( period = 3.395 ns ) ; demo:inst|counter[1] ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.133 ns ;
+; 6.606 ns ; 294.64 MHz ( period = 3.394 ns ) ; demo:inst|counter[1] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 3.132 ns ;
+; 6.686 ns ; 301.75 MHz ( period = 3.314 ns ) ; demo:inst|knightlight[2] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.740 ns ; 3.054 ns ;
+; 6.717 ns ; 304.60 MHz ( period = 3.283 ns ) ; demo:inst|knightlight[1] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.740 ns ; 3.023 ns ;
+; 6.752 ns ; 307.88 MHz ( period = 3.248 ns ) ; demo:inst|counter[2] ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 2.986 ns ;
+; 6.753 ns ; 307.98 MHz ( period = 3.247 ns ) ; demo:inst|counter[2] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 2.985 ns ;
+; 6.759 ns ; 308.55 MHz ( period = 3.241 ns ) ; demo:inst|counter[5] ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 2.979 ns ;
+; 6.760 ns ; 308.64 MHz ( period = 3.240 ns ) ; demo:inst|counter[5] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.738 ns ; 2.978 ns ;
+; 6.849 ns ; 317.36 MHz ( period = 3.151 ns ) ; demo:inst|ledstate ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.832 ns ; 2.983 ns ;
+; 6.862 ns ; 318.67 MHz ( period = 3.138 ns ) ; demo:inst|knightlight[0] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.740 ns ; 2.878 ns ;
+; 6.863 ns ; 318.78 MHz ( period = 3.137 ns ) ; demo:inst|ledstate ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.832 ns ; 2.969 ns ;
+; 7.127 ns ; 348.07 MHz ( period = 2.873 ns ) ; demo:inst|ledstate ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.832 ns ; 2.705 ns ;
+; 7.239 ns ; 362.19 MHz ( period = 2.761 ns ) ; demo:inst|counter[4] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 2.545 ns ;
+; 7.242 ns ; 362.58 MHz ( period = 2.758 ns ) ; demo:inst|counter[4] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 2.542 ns ;
+; 7.246 ns ; 363.11 MHz ( period = 2.754 ns ) ; demo:inst|counter[4] ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 2.538 ns ;
+; 7.458 ns ; 393.39 MHz ( period = 2.542 ns ) ; demo:inst|counter[3] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 2.326 ns ;
+; 7.461 ns ; 393.86 MHz ( period = 2.539 ns ) ; demo:inst|counter[3] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 2.323 ns ;
+; 7.465 ns ; 394.48 MHz ( period = 2.535 ns ) ; demo:inst|counter[3] ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 2.319 ns ;
+; 7.574 ns ; 412.20 MHz ( period = 2.426 ns ) ; demo:inst|counter[6] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 2.210 ns ;
+; 7.577 ns ; 412.71 MHz ( period = 2.423 ns ) ; demo:inst|counter[6] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 2.207 ns ;
+; 7.581 ns ; 413.39 MHz ( period = 2.419 ns ) ; demo:inst|counter[6] ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 2.203 ns ;
+; 7.676 ns ; 430.29 MHz ( period = 2.324 ns ) ; demo:inst|counter[0] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 2.108 ns ;
+; 7.679 ns ; 430.85 MHz ( period = 2.321 ns ) ; demo:inst|counter[0] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 2.105 ns ;
+; 7.683 ns ; 431.59 MHz ( period = 2.317 ns ) ; demo:inst|counter[0] ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 2.101 ns ;
+; 7.836 ns ; 462.11 MHz ( period = 2.164 ns ) ; demo:inst|counter[1] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 1.948 ns ;
+; 7.839 ns ; 462.75 MHz ( period = 2.161 ns ) ; demo:inst|counter[1] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 1.945 ns ;
+; 7.843 ns ; 463.61 MHz ( period = 2.157 ns ) ; demo:inst|counter[1] ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 1.941 ns ;
+; 7.983 ns ; 495.79 MHz ( period = 2.017 ns ) ; demo:inst|counter[2] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 1.801 ns ;
+; 7.986 ns ; 496.52 MHz ( period = 2.014 ns ) ; demo:inst|counter[2] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 1.798 ns ;
+; 7.990 ns ; 497.51 MHz ( period = 2.010 ns ) ; demo:inst|counter[2] ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 1.794 ns ;
+; 7.990 ns ; 497.51 MHz ( period = 2.010 ns ) ; demo:inst|counter[5] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 1.794 ns ;
+; 7.993 ns ; 498.26 MHz ( period = 2.007 ns ) ; demo:inst|counter[5] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 1.791 ns ;
+; 7.997 ns ; 499.25 MHz ( period = 2.003 ns ) ; demo:inst|counter[5] ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.784 ns ; 1.787 ns ;
+; 8.036 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[6] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 1.750 ns ;
+; 8.158 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[5] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 1.628 ns ;
+; 8.171 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|ledstate ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 1.615 ns ;
+; 8.227 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|ledstate ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 1.559 ns ;
+; 8.233 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[4] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 1.553 ns ;
+; 8.360 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[7] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 1.426 ns ;
+; 8.391 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[3] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 1.395 ns ;
+; 8.536 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[1] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 1.250 ns ;
+; 8.539 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[5] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 1.247 ns ;
+; 8.544 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[5] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 1.242 ns ;
+; 8.556 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[6] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 1.230 ns ;
+; 8.572 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[2] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 1.214 ns ;
+; 8.651 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|ledstate ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 1.135 ns ;
+; 8.654 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|ledstate ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 1.132 ns ;
+; 8.661 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|ledstate ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 1.125 ns ;
+; 8.670 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[7] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 1.116 ns ;
+; 8.804 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[4] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 0.982 ns ;
+; 8.818 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[4] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 0.968 ns ;
+; 8.832 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[0] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 0.954 ns ;
+; 8.878 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|ledstate ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 0.908 ns ;
+; 8.953 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[6] ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 0.833 ns ;
+; 9.038 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[1] ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 0.748 ns ;
+; 9.379 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[5] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 0.407 ns ;
+; 9.379 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[3] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 0.407 ns ;
+; 9.379 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[0] ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 0.407 ns ;
+; 9.379 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[1] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 0.407 ns ;
+; 9.379 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[2] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 0.407 ns ;
+; 9.379 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[4] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 0.407 ns ;
+; 9.379 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[6] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 0.407 ns ;
+; 9.379 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; demo:inst|knightlight[7] ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.786 ns ; 0.407 ns ;
++----------+---------------------------------------------+--------------------------+--------------------------+-----------------------------------------+-----------------------------------------+-----------------------------+---------------------------+-------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Hold: 'pll:inst1|altpll:altpll_component|_clk0' ;
++---------------+--------------------------+--------------------------+-----------------------------------------+-----------------------------------------+----------------------------+----------------------------+--------------------------+
+; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
++---------------+--------------------------+--------------------------+-----------------------------------------+-----------------------------------------+----------------------------+----------------------------+--------------------------+
+; 0.391 ns ; demo:inst|knightlight[5] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 0.407 ns ;
+; 0.391 ns ; demo:inst|knightlight[3] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 0.407 ns ;
+; 0.391 ns ; demo:inst|knightlight[0] ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 0.407 ns ;
+; 0.391 ns ; demo:inst|knightlight[1] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 0.407 ns ;
+; 0.391 ns ; demo:inst|knightlight[2] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 0.407 ns ;
+; 0.391 ns ; demo:inst|knightlight[4] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 0.407 ns ;
+; 0.391 ns ; demo:inst|counter[0] ; demo:inst|counter[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 0.407 ns ;
+; 0.391 ns ; demo:inst|knightlight[6] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 0.407 ns ;
+; 0.391 ns ; demo:inst|ledstate ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 0.407 ns ;
+; 0.391 ns ; demo:inst|knightlight[7] ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 0.407 ns ;
+; 0.732 ns ; demo:inst|knightlight[1] ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 0.748 ns ;
+; 0.817 ns ; demo:inst|knightlight[6] ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 0.833 ns ;
+; 0.892 ns ; demo:inst|ledstate ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 0.908 ns ;
+; 0.938 ns ; demo:inst|knightlight[0] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 0.954 ns ;
+; 0.952 ns ; demo:inst|knightlight[4] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 0.968 ns ;
+; 0.966 ns ; demo:inst|knightlight[4] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 0.982 ns ;
+; 1.100 ns ; demo:inst|knightlight[7] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 1.116 ns ;
+; 1.109 ns ; demo:inst|ledstate ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 1.125 ns ;
+; 1.116 ns ; demo:inst|ledstate ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 1.132 ns ;
+; 1.119 ns ; demo:inst|ledstate ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 1.135 ns ;
+; 1.198 ns ; demo:inst|knightlight[2] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 1.214 ns ;
+; 1.214 ns ; demo:inst|knightlight[6] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 1.230 ns ;
+; 1.226 ns ; demo:inst|knightlight[5] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 1.242 ns ;
+; 1.231 ns ; demo:inst|knightlight[5] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 1.247 ns ;
+; 1.234 ns ; demo:inst|knightlight[1] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 1.250 ns ;
+; 1.337 ns ; demo:inst|counter[1] ; demo:inst|counter[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 1.353 ns ;
+; 1.379 ns ; demo:inst|knightlight[3] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 1.395 ns ;
+; 1.410 ns ; demo:inst|knightlight[7] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 1.426 ns ;
+; 1.518 ns ; demo:inst|counter[2] ; demo:inst|counter[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 1.534 ns ;
+; 1.536 ns ; demo:inst|counter[0] ; demo:inst|counter[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 1.552 ns ;
+; 1.537 ns ; demo:inst|knightlight[4] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 1.553 ns ;
+; 1.543 ns ; demo:inst|ledstate ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 1.559 ns ;
+; 1.612 ns ; demo:inst|knightlight[5] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 1.628 ns ;
+; 1.734 ns ; demo:inst|knightlight[6] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 1.750 ns ;
+; 1.773 ns ; demo:inst|counter[5] ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 1.787 ns ;
+; 1.777 ns ; demo:inst|counter[5] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 1.791 ns ;
+; 1.780 ns ; demo:inst|counter[2] ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 1.794 ns ;
+; 1.780 ns ; demo:inst|counter[5] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 1.794 ns ;
+; 1.784 ns ; demo:inst|counter[2] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 1.798 ns ;
+; 1.787 ns ; demo:inst|counter[2] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 1.801 ns ;
+; 1.927 ns ; demo:inst|counter[1] ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 1.941 ns ;
+; 1.931 ns ; demo:inst|counter[1] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 1.945 ns ;
+; 1.934 ns ; demo:inst|counter[1] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 1.948 ns ;
+; 1.967 ns ; demo:inst|knightlight[3] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 1.983 ns ;
+; 2.000 ns ; demo:inst|counter[1] ; demo:inst|counter[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 2.016 ns ;
+; 2.087 ns ; demo:inst|counter[0] ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 2.101 ns ;
+; 2.091 ns ; demo:inst|counter[0] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 2.105 ns ;
+; 2.094 ns ; demo:inst|counter[0] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 2.108 ns ;
+; 2.189 ns ; demo:inst|counter[6] ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 2.203 ns ;
+; 2.193 ns ; demo:inst|counter[6] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 2.207 ns ;
+; 2.196 ns ; demo:inst|counter[6] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 2.210 ns ;
+; 2.201 ns ; demo:inst|counter[0] ; demo:inst|counter[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 2.217 ns ;
+; 2.305 ns ; demo:inst|counter[3] ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 2.319 ns ;
+; 2.309 ns ; demo:inst|counter[3] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 2.323 ns ;
+; 2.312 ns ; demo:inst|counter[3] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 2.326 ns ;
+; 2.524 ns ; demo:inst|counter[4] ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 2.538 ns ;
+; 2.528 ns ; demo:inst|counter[4] ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 2.542 ns ;
+; 2.531 ns ; demo:inst|counter[4] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.014 ns ; 2.545 ns ;
+; 2.643 ns ; demo:inst|ledstate ; demo:inst|knightlight[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.062 ns ; 2.705 ns ;
+; 2.790 ns ; demo:inst|counter[6] ; demo:inst|counter[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 2.806 ns ;
+; 2.907 ns ; demo:inst|ledstate ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.062 ns ; 2.969 ns ;
+; 2.908 ns ; demo:inst|knightlight[0] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.030 ns ; 2.878 ns ;
+; 2.921 ns ; demo:inst|ledstate ; demo:inst|knightlight[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.062 ns ; 2.983 ns ;
+; 2.931 ns ; demo:inst|counter[5] ; demo:inst|counter[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 2.947 ns ;
+; 2.948 ns ; demo:inst|counter[2] ; demo:inst|counter[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 2.964 ns ;
+; 2.986 ns ; demo:inst|counter[2] ; demo:inst|counter[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.002 ns ;
+; 3.010 ns ; demo:inst|counter[5] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 2.978 ns ;
+; 3.011 ns ; demo:inst|counter[5] ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 2.979 ns ;
+; 3.017 ns ; demo:inst|counter[2] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 2.985 ns ;
+; 3.018 ns ; demo:inst|counter[2] ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 2.986 ns ;
+; 3.019 ns ; demo:inst|counter[2] ; demo:inst|counter[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.035 ns ;
+; 3.046 ns ; demo:inst|counter[3] ; demo:inst|counter[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.062 ns ;
+; 3.053 ns ; demo:inst|knightlight[1] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.030 ns ; 3.023 ns ;
+; 3.084 ns ; demo:inst|knightlight[2] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.030 ns ; 3.054 ns ;
+; 3.093 ns ; demo:inst|counter[4] ; demo:inst|counter[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.109 ns ;
+; 3.118 ns ; demo:inst|counter[1] ; demo:inst|counter[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.134 ns ;
+; 3.150 ns ; demo:inst|counter[2] ; demo:inst|counter[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.166 ns ;
+; 3.156 ns ; demo:inst|counter[1] ; demo:inst|counter[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.172 ns ;
+; 3.164 ns ; demo:inst|counter[1] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.132 ns ;
+; 3.165 ns ; demo:inst|counter[1] ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.133 ns ;
+; 3.175 ns ; demo:inst|counter[5] ; demo:inst|counter[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.191 ns ;
+; 3.189 ns ; demo:inst|counter[1] ; demo:inst|counter[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.205 ns ;
+; 3.203 ns ; demo:inst|counter[4] ; demo:inst|counter[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.219 ns ;
+; 3.239 ns ; demo:inst|knightlight[3] ; demo:inst|knightlight[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.062 ns ; 3.301 ns ;
+; 3.255 ns ; demo:inst|counter[5] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.223 ns ;
+; 3.256 ns ; demo:inst|counter[5] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.224 ns ;
+; 3.258 ns ; demo:inst|counter[5] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.226 ns ;
+; 3.262 ns ; demo:inst|counter[2] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.230 ns ;
+; 3.263 ns ; demo:inst|counter[2] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.231 ns ;
+; 3.265 ns ; demo:inst|counter[2] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.233 ns ;
+; 3.274 ns ; demo:inst|counter[4] ; demo:inst|counter[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.290 ns ;
+; 3.319 ns ; demo:inst|counter[0] ; demo:inst|counter[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.335 ns ;
+; 3.320 ns ; demo:inst|counter[1] ; demo:inst|counter[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.336 ns ;
+; 3.323 ns ; demo:inst|counter[3] ; demo:inst|counter[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.339 ns ;
+; 3.324 ns ; demo:inst|counter[0] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.292 ns ;
+; 3.325 ns ; demo:inst|counter[0] ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.293 ns ;
+; 3.337 ns ; demo:inst|knightlight[2] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.030 ns ; 3.307 ns ;
+; 3.357 ns ; demo:inst|counter[0] ; demo:inst|counter[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.373 ns ;
+; 3.390 ns ; demo:inst|counter[0] ; demo:inst|counter[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.406 ns ;
+; 3.394 ns ; demo:inst|counter[3] ; demo:inst|counter[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.410 ns ;
+; 3.409 ns ; demo:inst|counter[1] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.377 ns ;
+; 3.410 ns ; demo:inst|counter[1] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.378 ns ;
+; 3.412 ns ; demo:inst|counter[1] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.380 ns ;
+; 3.426 ns ; demo:inst|counter[6] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.394 ns ;
+; 3.427 ns ; demo:inst|counter[6] ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.395 ns ;
+; 3.521 ns ; demo:inst|counter[0] ; demo:inst|counter[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.537 ns ;
+; 3.525 ns ; demo:inst|counter[3] ; demo:inst|counter[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.541 ns ;
+; 3.542 ns ; demo:inst|counter[3] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.510 ns ;
+; 3.543 ns ; demo:inst|counter[3] ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.511 ns ;
+; 3.569 ns ; demo:inst|counter[0] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.537 ns ;
+; 3.570 ns ; demo:inst|counter[0] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.538 ns ;
+; 3.572 ns ; demo:inst|counter[0] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.540 ns ;
+; 3.671 ns ; demo:inst|counter[6] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.639 ns ;
+; 3.672 ns ; demo:inst|counter[6] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.640 ns ;
+; 3.674 ns ; demo:inst|counter[6] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.642 ns ;
+; 3.761 ns ; demo:inst|counter[4] ; demo:inst|knightlight[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.729 ns ;
+; 3.762 ns ; demo:inst|counter[4] ; demo:inst|knightlight[7] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.730 ns ;
+; 3.787 ns ; demo:inst|counter[3] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.755 ns ;
+; 3.788 ns ; demo:inst|counter[3] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.756 ns ;
+; 3.790 ns ; demo:inst|counter[3] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.758 ns ;
+; 3.815 ns ; demo:inst|counter[6] ; demo:inst|counter[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.831 ns ;
+; 3.817 ns ; demo:inst|counter[6] ; demo:inst|counter[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.833 ns ;
+; 3.818 ns ; demo:inst|counter[6] ; demo:inst|counter[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.834 ns ;
+; 3.823 ns ; demo:inst|counter[4] ; demo:inst|counter[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.839 ns ;
+; 3.875 ns ; demo:inst|counter[5] ; demo:inst|counter[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.891 ns ;
+; 3.878 ns ; demo:inst|counter[5] ; demo:inst|counter[4] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 3.894 ns ;
+; 4.006 ns ; demo:inst|counter[4] ; demo:inst|knightlight[5] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.974 ns ;
+; 4.007 ns ; demo:inst|counter[4] ; demo:inst|knightlight[3] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.975 ns ;
+; 4.009 ns ; demo:inst|counter[4] ; demo:inst|knightlight[6] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 3.977 ns ;
+; 4.217 ns ; demo:inst|counter[2] ; demo:inst|counter[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 4.233 ns ;
+; 4.220 ns ; demo:inst|counter[2] ; demo:inst|counter[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 4.236 ns ;
+; 4.223 ns ; demo:inst|counter[6] ; demo:inst|counter[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 4.239 ns ;
+; 4.224 ns ; demo:inst|counter[6] ; demo:inst|counter[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 4.240 ns ;
+; 4.226 ns ; demo:inst|counter[6] ; demo:inst|counter[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 4.242 ns ;
+; 4.231 ns ; demo:inst|counter[4] ; demo:inst|counter[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 4.247 ns ;
+; 4.232 ns ; demo:inst|counter[4] ; demo:inst|counter[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 4.248 ns ;
+; 4.234 ns ; demo:inst|counter[4] ; demo:inst|counter[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 4.250 ns ;
+; 4.279 ns ; demo:inst|counter[5] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 4.247 ns ;
+; 4.283 ns ; demo:inst|counter[5] ; demo:inst|counter[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 4.299 ns ;
+; 4.284 ns ; demo:inst|counter[5] ; demo:inst|counter[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 4.300 ns ;
+; 4.286 ns ; demo:inst|counter[5] ; demo:inst|counter[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 4.302 ns ;
+; 4.286 ns ; demo:inst|counter[2] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 4.254 ns ;
+; 4.390 ns ; demo:inst|counter[3] ; demo:inst|counter[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 4.406 ns ;
+; 4.391 ns ; demo:inst|counter[3] ; demo:inst|counter[2] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 4.407 ns ;
+; 4.393 ns ; demo:inst|counter[3] ; demo:inst|counter[1] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 4.409 ns ;
+; 4.433 ns ; demo:inst|counter[1] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 4.401 ns ;
+; 4.458 ns ; demo:inst|counter[1] ; demo:inst|counter[0] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.016 ns ; 4.474 ns ;
+; 4.593 ns ; demo:inst|counter[0] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 4.561 ns ;
+; 4.695 ns ; demo:inst|counter[6] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 4.663 ns ;
+; 4.811 ns ; demo:inst|counter[3] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 4.779 ns ;
+; 5.030 ns ; demo:inst|counter[4] ; demo:inst|ledstate ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0.000 ns ; -0.032 ns ; 4.998 ns ;
++---------------+--------------------------+--------------------------+-----------------------------------------+-----------------------------------------+----------------------------+----------------------------+--------------------------+
+
+
++---------------------------------------------------------------------------------+
+; tsu ;
++-------+--------------+------------+-------+--------------------------+----------+
+; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
++-------+--------------+------------+-------+--------------------------+----------+
+; N/A ; None ; 7.774 ns ; RESET ; demo:inst|knightlight[7] ; CLK ;
+; N/A ; None ; 7.774 ns ; RESET ; demo:inst|ledstate ; CLK ;
+; N/A ; None ; 7.774 ns ; RESET ; demo:inst|knightlight[6] ; CLK ;
+; N/A ; None ; 7.774 ns ; RESET ; demo:inst|knightlight[4] ; CLK ;
+; N/A ; None ; 7.774 ns ; RESET ; demo:inst|knightlight[3] ; CLK ;
+; N/A ; None ; 7.774 ns ; RESET ; demo:inst|knightlight[5] ; CLK ;
+; N/A ; None ; 7.693 ns ; RESET ; demo:inst|knightlight[2] ; CLK ;
+; N/A ; None ; 7.693 ns ; RESET ; demo:inst|knightlight[1] ; CLK ;
+; N/A ; None ; 7.693 ns ; RESET ; demo:inst|knightlight[0] ; CLK ;
+; N/A ; None ; 7.545 ns ; RESET ; demo:inst|counter[6] ; CLK ;
+; N/A ; None ; 7.545 ns ; RESET ; demo:inst|counter[4] ; CLK ;
+; N/A ; None ; 7.545 ns ; RESET ; demo:inst|counter[5] ; CLK ;
+; N/A ; None ; 7.545 ns ; RESET ; demo:inst|counter[3] ; CLK ;
+; N/A ; None ; 7.543 ns ; RESET ; demo:inst|counter[0] ; CLK ;
+; N/A ; None ; 7.543 ns ; RESET ; demo:inst|counter[1] ; CLK ;
+; N/A ; None ; 7.543 ns ; RESET ; demo:inst|counter[2] ; CLK ;
++-------+--------------+------------+-------+--------------------------+----------+
+
+
++-------------------------------------------------------------------------------------+
+; tco ;
++-------+--------------+------------+--------------------------+---------+------------+
+; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
++-------+--------------+------------+--------------------------+---------+------------+
+; N/A ; None ; 9.507 ns ; demo:inst|knightlight[0] ; LEDS[0] ; CLK ;
+; N/A ; None ; 9.388 ns ; demo:inst|knightlight[2] ; LEDS[2] ; CLK ;
+; N/A ; None ; 9.171 ns ; demo:inst|knightlight[1] ; LEDS[1] ; CLK ;
+; N/A ; None ; 7.540 ns ; demo:inst|knightlight[4] ; LEDS[4] ; CLK ;
+; N/A ; None ; 7.369 ns ; demo:inst|knightlight[7] ; LEDS[7] ; CLK ;
+; N/A ; None ; 6.654 ns ; demo:inst|knightlight[3] ; LEDS[3] ; CLK ;
+; N/A ; None ; 6.178 ns ; demo:inst|knightlight[5] ; LEDS[5] ; CLK ;
+; N/A ; None ; 6.126 ns ; demo:inst|knightlight[6] ; LEDS[6] ; CLK ;
++-------+--------------+------------+--------------------------+---------+------------+
+
+
++---------------------------------------------------------------------------------------+
+; th ;
++---------------+-------------+-----------+-------+--------------------------+----------+
+; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
++---------------+-------------+-----------+-------+--------------------------+----------+
+; N/A ; None ; -7.313 ns ; RESET ; demo:inst|counter[0] ; CLK ;
+; N/A ; None ; -7.313 ns ; RESET ; demo:inst|counter[1] ; CLK ;
+; N/A ; None ; -7.313 ns ; RESET ; demo:inst|counter[2] ; CLK ;
+; N/A ; None ; -7.315 ns ; RESET ; demo:inst|counter[6] ; CLK ;
+; N/A ; None ; -7.315 ns ; RESET ; demo:inst|counter[4] ; CLK ;
+; N/A ; None ; -7.315 ns ; RESET ; demo:inst|counter[5] ; CLK ;
+; N/A ; None ; -7.315 ns ; RESET ; demo:inst|counter[3] ; CLK ;
+; N/A ; None ; -7.463 ns ; RESET ; demo:inst|knightlight[2] ; CLK ;
+; N/A ; None ; -7.463 ns ; RESET ; demo:inst|knightlight[1] ; CLK ;
+; N/A ; None ; -7.463 ns ; RESET ; demo:inst|knightlight[0] ; CLK ;
+; N/A ; None ; -7.544 ns ; RESET ; demo:inst|knightlight[7] ; CLK ;
+; N/A ; None ; -7.544 ns ; RESET ; demo:inst|ledstate ; CLK ;
+; N/A ; None ; -7.544 ns ; RESET ; demo:inst|knightlight[6] ; CLK ;
+; N/A ; None ; -7.544 ns ; RESET ; demo:inst|knightlight[4] ; CLK ;
+; N/A ; None ; -7.544 ns ; RESET ; demo:inst|knightlight[3] ; CLK ;
+; N/A ; None ; -7.544 ns ; RESET ; demo:inst|knightlight[5] ; CLK ;
++---------------+-------------+-----------+-------+--------------------------+----------+
+
+
++--------------------------+
+; Timing Analyzer Messages ;
++--------------------------+
+Info: *******************************************************************
+Info: Running Quartus II Classic Timing Analyzer
+ Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
+ Info: Processing started: Mon Mar 30 19:53:31 2009
+Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off demo -c demo --timing_analysis_only
+Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled
+Info: Found timing assignments -- calculating delays
+Info: Slack time is 3.604 ns for clock "pll:inst1|altpll:altpll_component|_clk0" between source register "demo:inst|counter[3]" and destination register "demo:inst|counter[1]"
+ Info: Fmax is 156.35 MHz (period= 6.396 ns)
+ Info: + Largest register to register requirement is 9.786 ns
+ Info: + Setup relationship between source and destination is 10.000 ns
+ Info: + Latch edge is 7.622 ns
+ Info: Clock period of Destination clock "pll:inst1|altpll:altpll_component|_clk0" is 10.000 ns with offset of -2.378 ns and duty cycle of 50
+ Info: Multicycle Setup factor for Destination register is 1
+ Info: - Launch edge is -2.378 ns
+ Info: Clock period of Source clock "pll:inst1|altpll:altpll_component|_clk0" is 10.000 ns with offset of -2.378 ns and duty cycle of 50
+ Info: Multicycle Setup factor for Source register is 1
+ Info: + Largest clock skew is 0.000 ns
+ Info: + Shortest clock path from clock "pll:inst1|altpll:altpll_component|_clk0" to destination register is 2.650 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll:inst1|altpll:altpll_component|_clk0'
+ Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'pll:inst1|altpll:altpll_component|_clk0~clkctrl'
+ Info: 3: + IC(1.022 ns) + CELL(0.537 ns) = 2.650 ns; Loc. = LCFF_X55_Y31_N1; Fanout = 3; REG Node = 'demo:inst|counter[1]'
+ Info: Total cell delay = 0.537 ns ( 20.26 % )
+ Info: Total interconnect delay = 2.113 ns ( 79.74 % )
+ Info: - Longest clock path from clock "pll:inst1|altpll:altpll_component|_clk0" to source register is 2.650 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll:inst1|altpll:altpll_component|_clk0'
+ Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'pll:inst1|altpll:altpll_component|_clk0~clkctrl'
+ Info: 3: + IC(1.022 ns) + CELL(0.537 ns) = 2.650 ns; Loc. = LCFF_X57_Y31_N31; Fanout = 3; REG Node = 'demo:inst|counter[3]'
+ Info: Total cell delay = 0.537 ns ( 20.26 % )
+ Info: Total interconnect delay = 2.113 ns ( 79.74 % )
+ Info: - Micro clock to output delay of source is 0.250 ns
+ Info: - Micro setup delay of destination is -0.036 ns
+ Info: - Longest register to register delay is 6.182 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X57_Y31_N31; Fanout = 3; REG Node = 'demo:inst|counter[3]'
+ Info: 2: + IC(0.741 ns) + CELL(0.414 ns) = 1.155 ns; Loc. = LCCOMB_X55_Y31_N18; Fanout = 2; COMB Node = 'demo:inst|Add0~101'
+ Info: 3: + IC(0.000 ns) + CELL(0.410 ns) = 1.565 ns; Loc. = LCCOMB_X55_Y31_N20; Fanout = 3; COMB Node = 'demo:inst|Add0~102'
+ Info: 4: + IC(0.277 ns) + CELL(0.414 ns) = 2.256 ns; Loc. = LCCOMB_X55_Y31_N4; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[3]~19'
+ Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 2.327 ns; Loc. = LCCOMB_X55_Y31_N6; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[4]~21'
+ Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 2.398 ns; Loc. = LCCOMB_X55_Y31_N8; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[5]~23'
+ Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 2.469 ns; Loc. = LCCOMB_X55_Y31_N10; Fanout = 1; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[6]~25'
+ Info: 8: + IC(0.000 ns) + CELL(0.410 ns) = 2.879 ns; Loc. = LCCOMB_X55_Y31_N12; Fanout = 14; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[7]~26'
+ Info: 9: + IC(0.705 ns) + CELL(0.150 ns) = 3.734 ns; Loc. = LCCOMB_X57_Y31_N10; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[49]~22'
+ Info: 10: + IC(0.263 ns) + CELL(0.504 ns) = 4.501 ns; Loc. = LCCOMB_X57_Y31_N14; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[2]~21'
+ Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 4.572 ns; Loc. = LCCOMB_X57_Y31_N16; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[3]~23'
+ Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 4.643 ns; Loc. = LCCOMB_X57_Y31_N18; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[4]~25'
+ Info: 13: + IC(0.000 ns) + CELL(0.071 ns) = 4.714 ns; Loc. = LCCOMB_X57_Y31_N20; Fanout = 2; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[5]~27'
+ Info: 14: + IC(0.000 ns) + CELL(0.071 ns) = 4.785 ns; Loc. = LCCOMB_X57_Y31_N22; Fanout = 1; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[6]~29'
+ Info: 15: + IC(0.000 ns) + CELL(0.071 ns) = 4.856 ns; Loc. = LCCOMB_X57_Y31_N24; Fanout = 1; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[7]~31'
+ Info: 16: + IC(0.000 ns) + CELL(0.410 ns) = 5.266 ns; Loc. = LCCOMB_X57_Y31_N26; Fanout = 7; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[8]~32'
+ Info: 17: + IC(0.682 ns) + CELL(0.150 ns) = 6.098 ns; Loc. = LCCOMB_X55_Y31_N0; Fanout = 1; COMB Node = 'demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[57]~636'
+ Info: 18: + IC(0.000 ns) + CELL(0.084 ns) = 6.182 ns; Loc. = LCFF_X55_Y31_N1; Fanout = 3; REG Node = 'demo:inst|counter[1]'
+ Info: Total cell delay = 3.514 ns ( 56.84 % )
+ Info: Total interconnect delay = 2.668 ns ( 43.16 % )
+Info: No valid register-to-register data paths exist for clock "CLK"
+Info: Minimum slack time is 391 ps for clock "pll:inst1|altpll:altpll_component|_clk0" between source register "demo:inst|knightlight[5]" and destination register "demo:inst|knightlight[5]"
+ Info: + Shortest register to register delay is 0.407 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X33_Y27_N29; Fanout = 5; REG Node = 'demo:inst|knightlight[5]'
+ Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X33_Y27_N28; Fanout = 1; COMB Node = 'demo:inst|knightlight~1268'
+ Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X33_Y27_N29; Fanout = 5; REG Node = 'demo:inst|knightlight[5]'
+ Info: Total cell delay = 0.407 ns ( 100.00 % )
+ Info: - Smallest register to register requirement is 0.016 ns
+ Info: + Hold relationship between source and destination is 0.000 ns
+ Info: + Latch edge is -2.378 ns
+ Info: Clock period of Destination clock "pll:inst1|altpll:altpll_component|_clk0" is 10.000 ns with offset of -2.378 ns and duty cycle of 50
+ Info: Multicycle Setup factor for Destination register is 1
+ Info: Multicycle Hold factor for Destination register is 1
+ Info: - Launch edge is -2.378 ns
+ Info: Clock period of Source clock "pll:inst1|altpll:altpll_component|_clk0" is 10.000 ns with offset of -2.378 ns and duty cycle of 50
+ Info: Multicycle Setup factor for Source register is 1
+ Info: Multicycle Hold factor for Source register is 1
+ Info: + Smallest clock skew is 0.000 ns
+ Info: + Longest clock path from clock "pll:inst1|altpll:altpll_component|_clk0" to destination register is 2.602 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll:inst1|altpll:altpll_component|_clk0'
+ Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'pll:inst1|altpll:altpll_component|_clk0~clkctrl'
+ Info: 3: + IC(0.974 ns) + CELL(0.537 ns) = 2.602 ns; Loc. = LCFF_X33_Y27_N29; Fanout = 5; REG Node = 'demo:inst|knightlight[5]'
+ Info: Total cell delay = 0.537 ns ( 20.64 % )
+ Info: Total interconnect delay = 2.065 ns ( 79.36 % )
+ Info: - Shortest clock path from clock "pll:inst1|altpll:altpll_component|_clk0" to source register is 2.602 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll:inst1|altpll:altpll_component|_clk0'
+ Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'pll:inst1|altpll:altpll_component|_clk0~clkctrl'
+ Info: 3: + IC(0.974 ns) + CELL(0.537 ns) = 2.602 ns; Loc. = LCFF_X33_Y27_N29; Fanout = 5; REG Node = 'demo:inst|knightlight[5]'
+ Info: Total cell delay = 0.537 ns ( 20.64 % )
+ Info: Total interconnect delay = 2.065 ns ( 79.36 % )
+ Info: - Micro clock to output delay of source is 0.250 ns
+ Info: + Micro hold delay of destination is 0.266 ns
+Info: tsu for register "demo:inst|knightlight[7]" (data pin = "RESET", clock pin = "CLK") is 7.774 ns
+ Info: + Longest pin to register delay is 8.034 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_B3; Fanout = 16; PIN Node = 'RESET'
+ Info: 2: + IC(6.674 ns) + CELL(0.510 ns) = 8.034 ns; Loc. = LCFF_X33_Y27_N15; Fanout = 4; REG Node = 'demo:inst|knightlight[7]'
+ Info: Total cell delay = 1.360 ns ( 16.93 % )
+ Info: Total interconnect delay = 6.674 ns ( 83.07 % )
+ Info: + Micro setup delay of destination is -0.036 ns
+ Info: - Offset between input clock "CLK" and output clock "pll:inst1|altpll:altpll_component|_clk0" is -2.378 ns
+ Info: - Shortest clock path from clock "pll:inst1|altpll:altpll_component|_clk0" to destination register is 2.602 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll:inst1|altpll:altpll_component|_clk0'
+ Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'pll:inst1|altpll:altpll_component|_clk0~clkctrl'
+ Info: 3: + IC(0.974 ns) + CELL(0.537 ns) = 2.602 ns; Loc. = LCFF_X33_Y27_N15; Fanout = 4; REG Node = 'demo:inst|knightlight[7]'
+ Info: Total cell delay = 0.537 ns ( 20.64 % )
+ Info: Total interconnect delay = 2.065 ns ( 79.36 % )
+Info: tco from clock "CLK" to destination pin "LEDS[0]" through register "demo:inst|knightlight[0]" is 9.507 ns
+ Info: + Offset between input clock "CLK" and output clock "pll:inst1|altpll:altpll_component|_clk0" is -2.378 ns
+ Info: + Longest clock path from clock "pll:inst1|altpll:altpll_component|_clk0" to source register is 2.648 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll:inst1|altpll:altpll_component|_clk0'
+ Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'pll:inst1|altpll:altpll_component|_clk0~clkctrl'
+ Info: 3: + IC(1.020 ns) + CELL(0.537 ns) = 2.648 ns; Loc. = LCFF_X54_Y31_N19; Fanout = 4; REG Node = 'demo:inst|knightlight[0]'
+ Info: Total cell delay = 0.537 ns ( 20.28 % )
+ Info: Total interconnect delay = 2.111 ns ( 79.72 % )
+ Info: + Micro clock to output delay of source is 0.250 ns
+ Info: + Longest register to pin delay is 8.987 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X54_Y31_N19; Fanout = 4; REG Node = 'demo:inst|knightlight[0]'
+ Info: 2: + IC(6.365 ns) + CELL(2.622 ns) = 8.987 ns; Loc. = PIN_W5; Fanout = 0; PIN Node = 'LEDS[0]'
+ Info: Total cell delay = 2.622 ns ( 29.18 % )
+ Info: Total interconnect delay = 6.365 ns ( 70.82 % )
+Info: th for register "demo:inst|counter[0]" (data pin = "RESET", clock pin = "CLK") is -7.313 ns
+ Info: + Offset between input clock "CLK" and output clock "pll:inst1|altpll:altpll_component|_clk0" is -2.378 ns
+ Info: + Longest clock path from clock "pll:inst1|altpll:altpll_component|_clk0" to destination register is 2.650 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll:inst1|altpll:altpll_component|_clk0'
+ Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'pll:inst1|altpll:altpll_component|_clk0~clkctrl'
+ Info: 3: + IC(1.022 ns) + CELL(0.537 ns) = 2.650 ns; Loc. = LCFF_X55_Y31_N29; Fanout = 5; REG Node = 'demo:inst|counter[0]'
+ Info: Total cell delay = 0.537 ns ( 20.26 % )
+ Info: Total interconnect delay = 2.113 ns ( 79.74 % )
+ Info: + Micro hold delay of destination is 0.266 ns
+ Info: - Shortest pin to register delay is 7.851 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_B3; Fanout = 16; PIN Node = 'RESET'
+ Info: 2: + IC(6.491 ns) + CELL(0.510 ns) = 7.851 ns; Loc. = LCFF_X55_Y31_N29; Fanout = 5; REG Node = 'demo:inst|counter[0]'
+ Info: Total cell delay = 1.360 ns ( 17.32 % )
+ Info: Total interconnect delay = 6.491 ns ( 82.68 % )
+Info: All timing requirements were met for slow timing model timing analysis. See Report window for more details.
+Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
+ Info: Processing ended: Mon Mar 30 19:53:32 2009
+ Info: Elapsed time: 00:00:01
+
+
--- /dev/null
+--------------------------------------------------------------------------------------
+Timing Analyzer Summary
+--------------------------------------------------------------------------------------
+
+Type : Worst-case tsu
+Slack : N/A
+Required Time : None
+Actual Time : 7.774 ns
+From : RESET
+To : demo:inst|knightlight[5]
+From Clock : --
+To Clock : CLK
+Failed Paths : 0
+
+Type : Worst-case tco
+Slack : N/A
+Required Time : None
+Actual Time : 9.507 ns
+From : demo:inst|knightlight[0]
+To : LEDS[0]
+From Clock : CLK
+To Clock : --
+Failed Paths : 0
+
+Type : Worst-case th
+Slack : N/A
+Required Time : None
+Actual Time : -7.313 ns
+From : RESET
+To : demo:inst|counter[2]
+From Clock : --
+To Clock : CLK
+Failed Paths : 0
+
+Type : Clock Setup: 'pll:inst1|altpll:altpll_component|_clk0'
+Slack : 3.604 ns
+Required Time : 100.00 MHz ( period = 10.000 ns )
+Actual Time : 156.35 MHz ( period = 6.396 ns )
+From : demo:inst|counter[3]
+To : demo:inst|counter[1]
+From Clock : pll:inst1|altpll:altpll_component|_clk0
+To Clock : pll:inst1|altpll:altpll_component|_clk0
+Failed Paths : 0
+
+Type : Clock Hold: 'pll:inst1|altpll:altpll_component|_clk0'
+Slack : 0.391 ns
+Required Time : 100.00 MHz ( period = 10.000 ns )
+Actual Time : N/A
+From : demo:inst|knightlight[5]
+To : demo:inst|knightlight[5]
+From Clock : pll:inst1|altpll:altpll_component|_clk0
+To Clock : pll:inst1|altpll:altpll_component|_clk0
+Failed Paths : 0
+
+Type : Total number of failed paths
+Slack :
+Required Time :
+Actual Time :
+From :
+To :
+From Clock :
+To Clock :
+Failed Paths : 0
+
+--------------------------------------------------------------------------------------
+
--- /dev/null
+Info: Start Nativelink Simulation process
+Info: NativeLink has detected VHDL design -- VHDL simulation models will be used
+
+========= EDA Simulation Settings =====================
+
+Sim Mode : RTL
+Family : cycloneii
+Quartus root : /opt/quartus/linux/
+Quartus sim root : /opt/quartus/eda/sim_lib
+Simulation Tool : modelsim
+Simulation Language : vhdl
+Version : 93
+Simulation Mode : GUI
+Sim Output File : demo.vho
+Sim SDF file : demo__vhdl.sdo
+Sim dir : simulation/modelsim
+
+=======================================================
+
+Info: Starting NativeLink simulation with ModelSim software
+Sourced NativeLink script /opt/quartus/common/tcl/internal/nativelink/modelsim.tcl
+Probing transcript
+ModelSim Info: # // ModelSim SE-64 6.3 May 4 2007 Linux 2.6.18-92.1.10.el5
+ModelSim Info: # //
+ModelSim Info: # // Copyright 1991-2007 Mentor Graphics Corporation
+ModelSim Info: # // All Rights Reserved.
+ModelSim Info: # //
+ModelSim Info: # // THIS WORK CONTAINS TRADE SECRET AND
+ModelSim Info: # // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
+ModelSim Info: # // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
+ModelSim Info: # // AND IS SUBJECT TO LICENSE TERMS.
+ModelSim Info: # //
+ModelSim Info: # do demo_run_msim_rtl_vhdl.do
+ModelSim Info: # if ![file isdirectory vhdl_libs] {
+ModelSim Info: # file mkdir vhdl_libs
+ModelSim Info: # }
+ModelSim Info: #
+ModelSim Info: # vlib vhdl_libs/lpm
+ModelSim Info: # vmap lpm vhdl_libs/lpm
+ModelSim Info: # Copying /opt/modelsim/modeltech/linux_x86_64/../modelsim.ini to modelsim.ini
+ModelSim Info: # Modifying modelsim.ini
+ModelSim Warning: # ** Warning: Copied /opt/modelsim/modeltech/linux_x86_64/../modelsim.ini to modelsim.ini.
+ModelSim Info: # Updated modelsim.ini.
+ModelSim Info: # vcom -work lpm /opt/quartus/eda/sim_lib/220pack.vhd
+ModelSim Info: # Model Technology ModelSim SE-64 vcom 6.3 Compiler 2007.05 May 4 2007
+ModelSim Info: # -- Loading package standard
+ModelSim Info: # -- Loading package std_logic_1164
+ModelSim Info: # -- Compiling package lpm_components
+ModelSim Info: # vcom -work lpm /opt/quartus/eda/sim_lib/220model.vhd
+ModelSim Info: # Model Technology ModelSim SE-64 vcom 6.3 Compiler 2007.05 May 4 2007
+ModelSim Info: # -- Loading package standard
+ModelSim Info: # -- Loading package std_logic_1164
+ModelSim Info: # -- Loading package textio
+ModelSim Info: # -- Compiling package lpm_common_conversion
+ModelSim Info: # -- Compiling package body lpm_common_conversion
+ModelSim Info: # -- Loading package lpm_common_conversion
+ModelSim Info: # -- Compiling package lpm_hint_evaluation
+ModelSim Info: # -- Compiling package body lpm_hint_evaluation
+ModelSim Info: # -- Loading package lpm_hint_evaluation
+ModelSim Info: # -- Compiling package lpm_device_families
+ModelSim Info: # -- Compiling package body lpm_device_families
+ModelSim Info: # -- Loading package lpm_device_families
+ModelSim Info: # -- Loading package std_logic_arith
+ModelSim Info: # -- Loading package std_logic_unsigned
+ModelSim Info: # -- Loading package lpm_components
+ModelSim Info: # -- Compiling entity lpm_constant
+ModelSim Info: # -- Compiling architecture lpm_syn of lpm_constant
+ModelSim Info: # -- Compiling entity lpm_inv
+ModelSim Info: # -- Compiling architecture lpm_syn of lpm_inv
+ModelSim Info: # -- Compiling entity lpm_and
+ModelSim Info: # -- Compiling architecture lpm_syn of lpm_and
+ModelSim Info: # -- Compiling entity lpm_or
+ModelSim Info: # -- Compiling architecture lpm_syn of lpm_or
+ModelSim Info: # -- Compiling entity lpm_xor
+ModelSim Info: # -- Compiling architecture lpm_syn of lpm_xor
+ModelSim Info: # -- Compiling entity lpm_bustri
+ModelSim Info: # -- Compiling architecture lpm_syn of lpm_bustri
+ModelSim Info: # -- Compiling entity lpm_mux
+ModelSim Info: # -- Compiling architecture lpm_syn of lpm_mux
+ModelSim Info: # -- Compiling entity lpm_decode
+ModelSim Info: # -- Compiling architecture lpm_syn of lpm_decode
+ModelSim Info: # -- Compiling entity lpm_clshift
+ModelSim Info: # -- Compiling architecture lpm_syn of lpm_clshift
+ModelSim Info: # -- Loading package std_logic_signed
+ModelSim Info: # -- Compiling entity lpm_add_sub_signed
+ModelSim Info: # -- Compiling architecture lpm_syn of lpm_add_sub_signed
+ModelSim Info: # -- Compiling entity lpm_add_sub_unsigned
+ModelSim Info: # -- Compiling architecture lpm_syn of lpm_add_sub_unsigned
+ModelSim Info: # -- Loading entity lpm_add_sub_signed
+ModelSim Info: # -- Loading entity lpm_add_sub_unsigned
+ModelSim Info: # -- Compiling entity lpm_add_sub
+ModelSim Info: # -- Compiling architecture lpm_syn of lpm_add_sub
+ModelSim Info: # -- Compiling entity lpm_compare_signed
+ModelSim Info: # -- Compiling architecture lpm_syn of lpm_compare_signed
+ModelSim Info: # -- Compiling entity lpm_compare_unsigned
+ModelSim Info: # -- Compiling architecture lpm_syn of lpm_compare_unsigned
+ModelSim Info: # -- Loading entity lpm_compare_signed
+ModelSim Info: # -- Loading entity lpm_compare_unsigned
+ModelSim Info: # -- Compiling entity lpm_compare
+ModelSim Info: # -- Compiling architecture lpm_syn of lpm_compare
+ModelSim Info: # -- Loading package lpm_hint_evaluation
+ModelSim Info: # -- Compiling entity lpm_mult
+ModelSim Info: # -- Compiling architecture lpm_syn of lpm_mult
+ModelSim Info: # -- Compiling entity lpm_divide
+ModelSim Info: # -- Compiling architecture behave of lpm_divide
+ModelSim Info: # -- Compiling entity lpm_abs
+ModelSim Info: # -- Compiling architecture lpm_syn of lpm_abs
+ModelSim Info: # -- Loading package lpm_common_conversion
+ModelSim Info: # -- Compiling entity lpm_counter
+ModelSim Info: # -- Compiling architecture lpm_syn of lpm_counter
+ModelSim Info: # -- Compiling entity lpm_latch
+ModelSim Info: # -- Compiling architecture lpm_syn of lpm_latch
+ModelSim Info: # -- Compiling entity lpm_ff
+ModelSim Info: # -- Compiling architecture lpm_syn of lpm_ff
+ModelSim Info: # -- Compiling entity lpm_shiftreg
+ModelSim Info: # -- Compiling architecture lpm_syn of lpm_shiftreg
+ModelSim Info: # -- Loading package lpm_device_families
+ModelSim Info: # -- Compiling entity lpm_ram_dq
+ModelSim Info: # -- Compiling architecture lpm_syn of lpm_ram_dq
+ModelSim Info: # -- Compiling entity lpm_ram_dp
+ModelSim Info: # -- Compiling architecture lpm_syn of lpm_ram_dp
+ModelSim Info: # -- Compiling entity lpm_ram_io
+ModelSim Info: # -- Compiling architecture lpm_syn of lpm_ram_io
+ModelSim Info: # -- Compiling entity lpm_rom
+ModelSim Info: # -- Compiling architecture lpm_syn of lpm_rom
+ModelSim Info: # -- Compiling entity lpm_fifo
+ModelSim Info: # -- Compiling architecture behavior of lpm_fifo
+ModelSim Info: # -- Compiling entity lpm_fifo_dc_dffpipe
+ModelSim Info: # -- Compiling architecture behavior of lpm_fifo_dc_dffpipe
+ModelSim Info: # -- Compiling entity lpm_fifo_dc_fefifo
+ModelSim Info: # -- Compiling architecture behavior of lpm_fifo_dc_fefifo
+ModelSim Info: # -- Loading entity lpm_fifo_dc_fefifo
+ModelSim Info: # -- Loading entity lpm_fifo_dc_dffpipe
+ModelSim Info: # -- Compiling entity lpm_fifo_dc_async
+ModelSim Info: # -- Compiling architecture behavior of lpm_fifo_dc_async
+ModelSim Info: # -- Loading entity lpm_fifo_dc_async
+ModelSim Info: # -- Compiling entity lpm_fifo_dc
+ModelSim Info: # -- Compiling architecture behavior of lpm_fifo_dc
+ModelSim Info: # -- Compiling entity lpm_inpad
+ModelSim Info: # -- Compiling architecture lpm_syn of lpm_inpad
+ModelSim Info: # -- Compiling entity lpm_outpad
+ModelSim Info: # -- Compiling architecture lpm_syn of lpm_outpad
+ModelSim Info: # -- Compiling entity lpm_bipad
+ModelSim Info: # -- Compiling architecture lpm_syn of lpm_bipad
+ModelSim Info: #
+ModelSim Info: # vlib vhdl_libs/altera
+ModelSim Info: # vmap altera vhdl_libs/altera
+ModelSim Info: # Modifying modelsim.ini
+ModelSim Info: # vcom -work altera /opt/quartus/eda/sim_lib/altera_primitives_components.vhd
+ModelSim Info: # Model Technology ModelSim SE-64 vcom 6.3 Compiler 2007.05 May 4 2007
+ModelSim Info: # -- Loading package standard
+ModelSim Info: # -- Loading package std_logic_1164
+ModelSim Info: # -- Loading package vital_timing
+ModelSim Info: # -- Loading package vital_primitives
+ModelSim Info: # -- Compiling package dffeas_pack
+ModelSim Info: # -- Loading package dffeas_pack
+ModelSim Info: # -- Compiling package altera_primitives_components
+ModelSim Info: # vcom -work altera /opt/quartus/eda/sim_lib/altera_primitives.vhd
+ModelSim Info: # Model Technology ModelSim SE-64 vcom 6.3 Compiler 2007.05 May 4 2007
+ModelSim Info: # -- Loading package standard
+ModelSim Info: # -- Loading package std_logic_1164
+ModelSim Info: # -- Compiling entity global
+ModelSim Info: # -- Compiling architecture behavior of global
+ModelSim Info: # -- Compiling entity carry
+ModelSim Info: # -- Compiling architecture behavior of carry
+ModelSim Info: # -- Compiling entity cascade
+ModelSim Info: # -- Compiling architecture behavior of cascade
+ModelSim Info: # -- Compiling entity carry_sum
+ModelSim Info: # -- Compiling architecture behavior of carry_sum
+ModelSim Info: # -- Compiling entity exp
+ModelSim Info: # -- Compiling architecture behavior of exp
+ModelSim Info: # -- Compiling entity soft
+ModelSim Info: # -- Compiling architecture behavior of soft
+ModelSim Info: # -- Compiling entity opndrn
+ModelSim Info: # -- Compiling architecture behavior of opndrn
+ModelSim Info: # -- Compiling entity row_global
+ModelSim Info: # -- Compiling architecture behavior of row_global
+ModelSim Info: # -- Compiling entity tri
+ModelSim Info: # -- Compiling architecture behavior of tri
+ModelSim Info: # -- Compiling entity lut_input
+ModelSim Info: # -- Compiling architecture behavior of lut_input
+ModelSim Info: # -- Compiling entity lut_output
+ModelSim Info: # -- Compiling architecture behavior of lut_output
+ModelSim Info: # -- Compiling entity latch
+ModelSim Info: # -- Compiling architecture behavior of latch
+ModelSim Info: # -- Compiling entity prim_gdff
+ModelSim Info: # -- Compiling architecture behavior of prim_gdff
+ModelSim Info: # -- Loading entity prim_gdff
+ModelSim Info: # -- Compiling entity dff
+ModelSim Info: # -- Compiling architecture behavior of dff
+ModelSim Info: # -- Compiling entity dffe
+ModelSim Info: # -- Compiling architecture behavior of dffe
+ModelSim Info: # -- Compiling entity dffea
+ModelSim Info: # -- Compiling architecture behavior of dffea
+ModelSim Info: # -- Loading package vital_timing
+ModelSim Info: # -- Loading package vital_primitives
+ModelSim Info: # -- Loading package dffeas_pack
+ModelSim Info: # -- Compiling entity dffeas
+ModelSim Info: # -- Compiling architecture vital_dffeas of dffeas
+ModelSim Info: # -- Compiling entity prim_gtff
+ModelSim Info: # -- Compiling architecture behavior of prim_gtff
+ModelSim Info: # -- Loading entity prim_gtff
+ModelSim Info: # -- Compiling entity tff
+ModelSim Info: # -- Compiling architecture behavior of tff
+ModelSim Info: # -- Compiling entity tffe
+ModelSim Info: # -- Compiling architecture behavior of tffe
+ModelSim Info: # -- Compiling entity prim_gjkff
+ModelSim Info: # -- Compiling architecture behavior of prim_gjkff
+ModelSim Info: # -- Loading entity prim_gjkff
+ModelSim Info: # -- Compiling entity jkff
+ModelSim Info: # -- Compiling architecture behavior of jkff
+ModelSim Info: # -- Compiling entity jkffe
+ModelSim Info: # -- Compiling architecture behavior of jkffe
+ModelSim Info: # -- Compiling entity prim_gsrff
+ModelSim Info: # -- Compiling architecture behavior of prim_gsrff
+ModelSim Info: # -- Loading entity prim_gsrff
+ModelSim Info: # -- Compiling entity srff
+ModelSim Info: # -- Compiling architecture behavior of srff
+ModelSim Info: # -- Compiling entity srffe
+ModelSim Info: # -- Compiling architecture behavior of srffe
+ModelSim Info: # -- Compiling entity clklock
+ModelSim Info: # -- Compiling architecture behavior of clklock
+ModelSim Info: # -- Compiling entity alt_inbuf
+ModelSim Info: # -- Compiling architecture behavior of alt_inbuf
+ModelSim Info: # -- Compiling entity alt_outbuf
+ModelSim Info: # -- Compiling architecture behavior of alt_outbuf
+ModelSim Info: # -- Compiling entity alt_outbuf_tri
+ModelSim Info: # -- Compiling architecture behavior of alt_outbuf_tri
+ModelSim Info: # -- Compiling entity alt_iobuf
+ModelSim Info: # -- Compiling architecture behavior of alt_iobuf
+ModelSim Info: # -- Compiling entity alt_inbuf_diff
+ModelSim Info: # -- Compiling architecture behavior of alt_inbuf_diff
+ModelSim Info: # -- Compiling entity alt_outbuf_diff
+ModelSim Info: # -- Compiling architecture behavior of alt_outbuf_diff
+ModelSim Info: # -- Compiling entity alt_outbuf_tri_diff
+ModelSim Info: # -- Compiling architecture behavior of alt_outbuf_tri_diff
+ModelSim Info: # -- Compiling entity alt_iobuf_diff
+ModelSim Info: # -- Compiling architecture behavior of alt_iobuf_diff
+ModelSim Info: # -- Compiling entity alt_bidir_diff
+ModelSim Info: # -- Compiling architecture behavior of alt_bidir_diff
+ModelSim Info: #
+ModelSim Info: # vlib vhdl_libs/altera_mf
+ModelSim Info: # vmap altera_mf vhdl_libs/altera_mf
+ModelSim Info: # Modifying modelsim.ini
+ModelSim Info: # vcom -work altera_mf /opt/quartus/eda/sim_lib/altera_mf_components.vhd
+ModelSim Info: # Model Technology ModelSim SE-64 vcom 6.3 Compiler 2007.05 May 4 2007
+ModelSim Info: # -- Loading package standard
+ModelSim Info: # -- Loading package std_logic_1164
+ModelSim Info: # -- Compiling package altera_mf_components
+ModelSim Info: # vcom -work altera_mf /opt/quartus/eda/sim_lib/altera_mf.vhd
+ModelSim Info: # Model Technology ModelSim SE-64 vcom 6.3 Compiler 2007.05 May 4 2007
+ModelSim Info: # -- Loading package standard
+ModelSim Info: # -- Loading package std_logic_1164
+ModelSim Info: # -- Compiling entity lcell
+ModelSim Info: # -- Compiling architecture behavior of lcell
+ModelSim Info: # -- Loading package textio
+ModelSim Info: # -- Compiling package altera_common_conversion
+ModelSim Info: # -- Compiling package body altera_common_conversion
+ModelSim Info: # -- Loading package altera_common_conversion
+ModelSim Info: # -- Compiling package altera_mf_hint_evaluation
+ModelSim Info: # -- Compiling package body altera_mf_hint_evaluation
+ModelSim Info: # -- Loading package altera_mf_hint_evaluation
+ModelSim Info: # -- Compiling package altera_device_families
+ModelSim Info: # -- Compiling package body altera_device_families
+ModelSim Info: # -- Loading package altera_device_families
+ModelSim Info: # -- Compiling package mf_pllpack
+ModelSim Info: # -- Compiling package body mf_pllpack
+ModelSim Info: # -- Loading package mf_pllpack
+ModelSim Info: # -- Compiling entity dffp
+ModelSim Info: # -- Compiling architecture behave of dffp
+ModelSim Info: # -- Compiling entity mf_m_cntr
+ModelSim Info: # -- Compiling architecture behave of mf_m_cntr
+ModelSim Info: # -- Compiling entity mf_n_cntr
+ModelSim Info: # -- Compiling architecture behave of mf_n_cntr
+ModelSim Info: # -- Compiling entity stx_scale_cntr
+ModelSim Info: # -- Compiling architecture behave of stx_scale_cntr
+ModelSim Info: # -- Compiling entity mf_pll_reg
+ModelSim Info: # -- Compiling architecture behave of mf_pll_reg
+ModelSim Info: # -- Loading package mf_pllpack
+ModelSim Info: # -- Loading entity mf_m_cntr
+ModelSim Info: # -- Loading entity mf_n_cntr
+ModelSim Info: # -- Loading entity stx_scale_cntr
+ModelSim Info: # -- Loading entity dffp
+ModelSim Info: # -- Loading entity mf_pll_reg
+ModelSim Info: # -- Compiling entity mf_stratix_pll
+ModelSim Info: # -- Compiling architecture vital_pll of mf_stratix_pll
+ModelSim Info: # -- Compiling entity arm_m_cntr
+ModelSim Info: # -- Compiling architecture behave of arm_m_cntr
+ModelSim Info: # -- Compiling entity arm_n_cntr
+ModelSim Info: # -- Compiling architecture behave of arm_n_cntr
+ModelSim Info: # -- Compiling entity arm_scale_cntr
+ModelSim Info: # -- Compiling architecture behave of arm_scale_cntr
+ModelSim Info: # -- Loading entity arm_m_cntr
+ModelSim Info: # -- Loading entity arm_n_cntr
+ModelSim Info: # -- Loading entity arm_scale_cntr
+ModelSim Info: # -- Compiling entity mf_stratixii_pll
+ModelSim Info: # -- Compiling architecture vital_pll of mf_stratixii_pll
+ModelSim Info: # -- Loading package std_logic_arith
+ModelSim Info: # -- Loading package std_logic_unsigned
+ModelSim Info: # -- Compiling entity mf_ttn_mn_cntr
+ModelSim Info: # -- Compiling architecture behave of mf_ttn_mn_cntr
+ModelSim Info: # -- Compiling entity mf_ttn_scale_cntr
+ModelSim Info: # -- Compiling architecture behave of mf_ttn_scale_cntr
+ModelSim Info: # -- Loading entity mf_ttn_mn_cntr
+ModelSim Info: # -- Loading entity mf_ttn_scale_cntr
+ModelSim Info: # -- Compiling entity mf_stratixiii_pll
+ModelSim Info: # -- Compiling architecture vital_pll of mf_stratixiii_pll
+ModelSim Info: # -- Compiling entity mf_cda_mn_cntr
+ModelSim Info: # -- Compiling architecture behave of mf_cda_mn_cntr
+ModelSim Info: # -- Compiling entity mf_cda_scale_cntr
+ModelSim Info: # -- Compiling architecture behave of mf_cda_scale_cntr
+ModelSim Info: # -- Loading entity mf_cda_mn_cntr
+ModelSim Info: # -- Loading entity mf_cda_scale_cntr
+ModelSim Info: # -- Compiling entity mf_cycloneiii_pll
+ModelSim Info: # -- Compiling architecture vital_pll of mf_cycloneiii_pll
+ModelSim Info: # -- Loading package altera_device_families
+ModelSim Info: # -- Loading entity mf_stratix_pll
+ModelSim Info: # -- Loading entity mf_stratixii_pll
+ModelSim Info: # -- Loading entity mf_stratixiii_pll
+ModelSim Info: # -- Loading entity mf_cycloneiii_pll
+ModelSim Info: # -- Compiling entity altpll
+ModelSim Info: # -- Compiling architecture behavior of altpll
+ModelSim Info: # -- Compiling entity altaccumulate
+ModelSim Info: # -- Compiling architecture behaviour of altaccumulate
+ModelSim Info: # -- Compiling entity altmult_accum
+ModelSim Info: # -- Compiling architecture behaviour of altmult_accum
+ModelSim Info: # -- Compiling entity altmult_add
+ModelSim Info: # -- Compiling architecture behaviour of altmult_add
+ModelSim Info: # -- Loading package altera_common_conversion
+ModelSim Info: # -- Compiling entity altfp_mult
+ModelSim Info: # -- Compiling architecture behavior of altfp_mult
+ModelSim Info: # -- Compiling entity altsqrt
+ModelSim Info: # -- Compiling architecture behavior of altsqrt
+ModelSim Info: # -- Compiling entity altclklock
+ModelSim Info: # -- Compiling architecture behavior of altclklock
+ModelSim Info: # -- Compiling entity altddio_in
+ModelSim Info: # -- Compiling architecture behave of altddio_in
+ModelSim Info: # -- Compiling entity altddio_out
+ModelSim Info: # -- Compiling architecture behave of altddio_out
+ModelSim Info: # -- Loading entity altddio_in
+ModelSim Info: # -- Loading entity altddio_out
+ModelSim Info: # -- Compiling entity altddio_bidir
+ModelSim Info: # -- Compiling architecture struct of altddio_bidir
+ModelSim Info: # -- Compiling entity hssi_pll
+ModelSim Info: # -- Compiling architecture behavior of hssi_pll
+ModelSim Info: # -- Compiling entity mf_ram7x20_syn
+ModelSim Info: # -- Compiling architecture hssi_ram7x20_syn of mf_ram7x20_syn
+ModelSim Info: # -- Loading entity mf_ram7x20_syn
+ModelSim Info: # -- Compiling entity hssi_fifo
+ModelSim Info: # -- Compiling architecture synchronizer of hssi_fifo
+ModelSim Info: # -- Compiling entity hssi_rx
+ModelSim Info: # -- Compiling architecture hssi_receiver of hssi_rx
+ModelSim Info: # -- Compiling entity hssi_tx
+ModelSim Info: # -- Compiling architecture transmitter of hssi_tx
+ModelSim Info: # -- Loading entity hssi_pll
+ModelSim Info: # -- Loading entity hssi_rx
+ModelSim Info: # -- Loading entity hssi_fifo
+ModelSim Info: # -- Compiling entity altcdr_rx
+ModelSim Info: # -- Compiling architecture struct of altcdr_rx
+ModelSim Info: # -- Loading entity hssi_tx
+ModelSim Info: # -- Compiling entity altcdr_tx
+ModelSim Info: # -- Compiling architecture struct of altcdr_tx
+ModelSim Info: # -- Compiling entity stratixii_lvds_rx
+ModelSim Info: # -- Compiling architecture behavior of stratixii_lvds_rx
+ModelSim Info: # -- Compiling entity flexible_lvds_rx
+ModelSim Info: # -- Compiling architecture behavior of flexible_lvds_rx
+ModelSim Info: # -- Compiling entity stratixiii_lvds_rx
+ModelSim Info: # -- Compiling architecture behavior of stratixiii_lvds_rx
+ModelSim Info: # -- Loading entity altclklock
+ModelSim Info: # -- Loading entity stratixii_lvds_rx
+ModelSim Info: # -- Loading entity flexible_lvds_rx
+ModelSim Info: # -- Loading entity stratixiii_lvds_rx
+ModelSim Info: # -- Compiling entity altlvds_rx
+ModelSim Info: # -- Compiling architecture behavior of altlvds_rx
+ModelSim Info: # -- Compiling entity stratix_tx_outclk
+ModelSim Info: # -- Compiling architecture behavior of stratix_tx_outclk
+ModelSim Info: # -- Compiling entity stratixii_tx_outclk
+ModelSim Info: # -- Compiling architecture behavior of stratixii_tx_outclk
+ModelSim Info: # -- Compiling entity flexible_lvds_tx
+ModelSim Info: # -- Compiling architecture behavior of flexible_lvds_tx
+ModelSim Info: # -- Loading entity stratix_tx_outclk
+ModelSim Info: # -- Loading entity stratixii_tx_outclk
+ModelSim Info: # -- Loading entity flexible_lvds_tx
+ModelSim Info: # -- Compiling entity altlvds_tx
+ModelSim Info: # -- Compiling architecture behavior of altlvds_tx
+ModelSim Info: # -- Compiling entity altcam
+ModelSim Info: # -- Compiling architecture behave of altcam
+ModelSim Info: # -- Compiling entity altdpram
+ModelSim Info: # -- Compiling architecture behavior of altdpram
+ModelSim Info: # -- Compiling entity altsyncram
+ModelSim Info: # -- Compiling architecture translated of altsyncram
+ModelSim Info: # -- Loading entity altsyncram
+ModelSim Info: # -- Compiling entity alt3pram
+ModelSim Info: # -- Compiling architecture behavior of alt3pram
+ModelSim Info: # -- Compiling entity altqpram
+ModelSim Info: # -- Compiling architecture behavior of altqpram
+ModelSim Info: # -- Loading package altera_mf_components
+ModelSim Info: # -- Compiling entity parallel_add
+ModelSim Info: # -- Compiling architecture behaviour of parallel_add
+ModelSim Info: # -- Compiling entity scfifo
+ModelSim Info: # -- Compiling architecture behavior of scfifo
+ModelSim Info: # -- Compiling package dcfifo_pack
+ModelSim Info: # -- Compiling package body dcfifo_pack
+ModelSim Info: # -- Loading package dcfifo_pack
+ModelSim Info: # -- Compiling entity dcfifo_dffpipe
+ModelSim Info: # -- Compiling architecture behavior of dcfifo_dffpipe
+ModelSim Info: # -- Compiling entity dcfifo_fefifo
+ModelSim Info: # -- Compiling architecture behavior of dcfifo_fefifo
+ModelSim Info: # -- Loading entity dcfifo_fefifo
+ModelSim Info: # -- Loading entity dcfifo_dffpipe
+ModelSim Info: # -- Compiling entity dcfifo_async
+ModelSim Info: # -- Compiling architecture behavior of dcfifo_async
+ModelSim Info: # -- Compiling entity dcfifo_sync
+ModelSim Info: # -- Compiling architecture behavior of dcfifo_sync
+ModelSim Info: # -- Loading package altera_mf_hint_evaluation
+ModelSim Info: # -- Compiling entity dcfifo_low_latency
+ModelSim Info: # -- Compiling architecture behavior of dcfifo_low_latency
+ModelSim Info: # -- Loading entity dcfifo_async
+ModelSim Info: # -- Loading entity dcfifo_sync
+ModelSim Info: # -- Loading entity dcfifo_low_latency
+ModelSim Info: # -- Loading package dcfifo_pack
+ModelSim Info: # -- Compiling entity dcfifo_mixed_widths
+ModelSim Info: # -- Compiling architecture behavior of dcfifo_mixed_widths
+ModelSim Info: # -- Loading entity dcfifo_mixed_widths
+ModelSim Info: # -- Compiling entity dcfifo
+ModelSim Info: # -- Compiling architecture behavior of dcfifo
+ModelSim Info: # -- Compiling entity altshift_taps
+ModelSim Info: # -- Compiling architecture behavioural of altshift_taps
+ModelSim Info: # -- Compiling entity a_graycounter
+ModelSim Info: # -- Compiling architecture behavior of a_graycounter
+ModelSim Info: # -- Compiling entity altsquare
+ModelSim Info: # -- Compiling architecture altsquare_syn of altsquare
+ModelSim Info: # -- Compiling package sld_node
+ModelSim Info: # -- Compiling package body sld_node
+ModelSim Info: # -- Loading package sld_node
+ModelSim Info: # -- Loading package sld_node
+ModelSim Info: # -- Compiling entity signal_gen
+ModelSim Info: # -- Compiling architecture simmodel of signal_gen
+ModelSim Info: # -- Compiling entity jtag_tap_controller
+ModelSim Info: # -- Compiling architecture fsm of jtag_tap_controller
+ModelSim Info: # -- Compiling entity dummy_hub
+ModelSim Info: # -- Compiling architecture behavior of dummy_hub
+ModelSim Info: # -- Loading entity signal_gen
+ModelSim Info: # -- Loading entity jtag_tap_controller
+ModelSim Info: # -- Loading entity dummy_hub
+ModelSim Info: # -- Compiling entity sld_virtual_jtag
+ModelSim Info: # -- Compiling architecture structural of sld_virtual_jtag
+ModelSim Info: # -- Compiling entity sld_signaltap
+ModelSim Info: # -- Compiling architecture sim_sld_signaltap of sld_signaltap
+ModelSim Info: # -- Compiling entity altstratixii_oct
+ModelSim Info: # -- Compiling architecture sim_altstratixii_oct of altstratixii_oct
+ModelSim Info: # -- Compiling entity altparallel_flash_loader
+ModelSim Info: # -- Compiling architecture sim_altparallel_flash_loader of altparallel_flash_loader
+ModelSim Info: # -- Compiling entity altserial_flash_loader
+ModelSim Info: # -- Compiling architecture sim_altserial_flash_loader of altserial_flash_loader
+ModelSim Info: #
+ModelSim Info: # vlib vhdl_libs/sgate
+ModelSim Info: # vmap sgate vhdl_libs/sgate
+ModelSim Info: # Modifying modelsim.ini
+ModelSim Info: # vcom -work sgate /opt/quartus/eda/sim_lib/sgate_pack.vhd
+ModelSim Info: # Model Technology ModelSim SE-64 vcom 6.3 Compiler 2007.05 May 4 2007
+ModelSim Info: # -- Loading package standard
+ModelSim Info: # -- Loading package std_logic_1164
+ModelSim Info: # -- Compiling package sgate_pack
+ModelSim Info: # -- Compiling package body sgate_pack
+ModelSim Info: # -- Loading package sgate_pack
+ModelSim Info: # vcom -work sgate /opt/quartus/eda/sim_lib/sgate.vhd
+ModelSim Info: # Model Technology ModelSim SE-64 vcom 6.3 Compiler 2007.05 May 4 2007
+ModelSim Info: # -- Loading package standard
+ModelSim Info: # -- Loading package std_logic_1164
+ModelSim Info: # -- Loading package std_logic_arith
+ModelSim Info: # -- Loading package std_logic_signed
+ModelSim Info: # -- Compiling entity oper_add
+ModelSim Info: # -- Compiling architecture sim_arch of oper_add
+ModelSim Info: # -- Compiling entity oper_addsub
+ModelSim Info: # -- Compiling architecture sim_arch of oper_addsub
+ModelSim Info: # -- Compiling entity mux21
+ModelSim Info: # -- Compiling architecture sim_arch of mux21
+ModelSim Info: # -- Compiling entity io_buf_tri
+ModelSim Info: # -- Compiling architecture sim_arch of io_buf_tri
+ModelSim Info: # -- Compiling entity io_buf_opdrn
+ModelSim Info: # -- Compiling architecture sim_arch of io_buf_opdrn
+ModelSim Info: # -- Compiling entity tri_bus
+ModelSim Info: # -- Compiling architecture sim_arch of tri_bus
+ModelSim Info: # -- Compiling entity oper_mult
+ModelSim Info: # -- Compiling architecture sim_arch of oper_mult
+ModelSim Info: # -- Loading package lpm_components
+ModelSim Info: # -- Compiling entity oper_div
+ModelSim Info: # -- Compiling architecture sim_arch of oper_div
+ModelSim Info: # -- Compiling entity oper_mod
+ModelSim Info: # -- Compiling architecture sim_arch of oper_mod
+ModelSim Info: # -- Loading package std_logic_unsigned
+ModelSim Info: # -- Compiling entity oper_left_shift
+ModelSim Info: # -- Compiling architecture sim_arch of oper_left_shift
+ModelSim Info: # -- Compiling entity oper_right_shift
+ModelSim Info: # -- Compiling architecture sim_arch of oper_right_shift
+ModelSim Info: # -- Compiling entity oper_rotate_left
+ModelSim Info: # -- Compiling architecture sim_arch of oper_rotate_left
+ModelSim Info: # -- Compiling entity oper_rotate_right
+ModelSim Info: # -- Compiling architecture sim_arch of oper_rotate_right
+ModelSim Info: # -- Compiling entity oper_less_than
+ModelSim Info: # -- Compiling architecture sim_arch of oper_less_than
+ModelSim Info: # -- Loading package sgate_pack
+ModelSim Info: # -- Compiling entity oper_mux
+ModelSim Info: # -- Compiling architecture sim_arch of oper_mux
+ModelSim Info: # -- Compiling entity oper_selector
+ModelSim Info: # -- Compiling architecture sim_arch of oper_selector
+ModelSim Info: # -- Compiling entity oper_prio_selector
+ModelSim Info: # -- Compiling architecture sim_arch of oper_prio_selector
+ModelSim Info: # -- Compiling entity oper_decoder
+ModelSim Info: # -- Compiling architecture sim_arch of oper_decoder
+ModelSim Info: # -- Compiling entity oper_bus_mux
+ModelSim Info: # -- Compiling architecture sim_arch of oper_bus_mux
+ModelSim Info: # -- Compiling entity oper_latch
+ModelSim Info: # -- Compiling architecture sim_arch of oper_latch
+ModelSim Info: #
+ModelSim Info: # vlib vhdl_libs/cycloneii
+ModelSim Info: # vmap cycloneii vhdl_libs/cycloneii
+ModelSim Info: # Modifying modelsim.ini
+ModelSim Info: # vcom -work cycloneii /opt/quartus/eda/sim_lib/cycloneii_atoms.vhd
+ModelSim Info: # Model Technology ModelSim SE-64 vcom 6.3 Compiler 2007.05 May 4 2007
+ModelSim Info: # -- Loading package standard
+ModelSim Info: # -- Loading package std_logic_1164
+ModelSim Info: # -- Loading package vital_timing
+ModelSim Info: # -- Loading package vital_primitives
+ModelSim Info: # -- Compiling package cycloneii_atom_pack
+ModelSim Info: # -- Compiling package body cycloneii_atom_pack
+ModelSim Info: # -- Loading package cycloneii_atom_pack
+ModelSim Info: # -- Compiling package cycloneii_pllpack
+ModelSim Info: # -- Compiling package body cycloneii_pllpack
+ModelSim Info: # -- Loading package cycloneii_pllpack
+ModelSim Info: # -- Loading package cycloneii_atom_pack
+ModelSim Info: # -- Compiling entity cycloneii_dffe
+ModelSim Info: # -- Compiling architecture behave of cycloneii_dffe
+ModelSim Info: # -- Compiling entity cycloneii_mux21
+ModelSim Info: # -- Compiling architecture altvital of cycloneii_mux21
+ModelSim Info: # -- Compiling entity cycloneii_mux41
+ModelSim Info: # -- Compiling architecture altvital of cycloneii_mux41
+ModelSim Info: # -- Compiling entity cycloneii_and1
+ModelSim Info: # -- Compiling architecture altvital of cycloneii_and1
+ModelSim Info: # -- Compiling entity cycloneii_ram_register
+ModelSim Info: # -- Compiling architecture reg_arch of cycloneii_ram_register
+ModelSim Info: # -- Compiling entity cycloneii_ram_pulse_generator
+ModelSim Info: # -- Compiling architecture pgen_arch of cycloneii_ram_pulse_generator
+ModelSim Info: # -- Loading entity cycloneii_ram_register
+ModelSim Info: # -- Loading entity cycloneii_ram_pulse_generator
+ModelSim Info: # -- Compiling entity cycloneii_ram_block
+ModelSim Info: # -- Compiling architecture block_arch of cycloneii_ram_block
+ModelSim Info: # -- Compiling entity cycloneii_jtag
+ModelSim Info: # -- Compiling architecture architecture_jtag of cycloneii_jtag
+ModelSim Info: # -- Compiling entity cycloneii_crcblock
+ModelSim Info: # -- Compiling architecture architecture_crcblock of cycloneii_crcblock
+ModelSim Info: # -- Compiling entity cycloneii_asmiblock
+ModelSim Info: # -- Compiling architecture architecture_asmiblock of cycloneii_asmiblock
+ModelSim Info: # -- Compiling entity cycloneii_m_cntr
+ModelSim Info: # -- Compiling architecture behave of cycloneii_m_cntr
+ModelSim Info: # -- Compiling entity cycloneii_n_cntr
+ModelSim Info: # -- Compiling architecture behave of cycloneii_n_cntr
+ModelSim Info: # -- Compiling entity cycloneii_scale_cntr
+ModelSim Info: # -- Compiling architecture behave of cycloneii_scale_cntr
+ModelSim Info: # -- Compiling entity cycloneii_pll_reg
+ModelSim Info: # -- Compiling architecture behave of cycloneii_pll_reg
+ModelSim Info: # -- Loading package textio
+ModelSim Info: # -- Loading package cycloneii_pllpack
+ModelSim Info: # -- Loading entity cycloneii_m_cntr
+ModelSim Info: # -- Loading entity cycloneii_n_cntr
+ModelSim Info: # -- Loading entity cycloneii_scale_cntr
+ModelSim Info: # -- Loading entity cycloneii_dffe
+ModelSim Info: # -- Loading entity cycloneii_pll_reg
+ModelSim Info: # -- Compiling entity cycloneii_pll
+ModelSim Info: # -- Compiling architecture vital_pll of cycloneii_pll
+ModelSim Info: # -- Compiling entity cycloneii_routing_wire
+ModelSim Info: # -- Compiling architecture behave of cycloneii_routing_wire
+ModelSim Info: # -- Loading entity cycloneii_and1
+ModelSim Info: # -- Compiling entity cycloneii_lcell_ff
+ModelSim Info: # -- Compiling architecture vital_lcell_ff of cycloneii_lcell_ff
+ModelSim Info: # -- Compiling entity cycloneii_lcell_comb
+ModelSim Info: # -- Compiling architecture vital_lcell_comb of cycloneii_lcell_comb
+ModelSim Info: # -- Loading package std_logic_arith
+ModelSim Info: # -- Compiling entity cycloneii_asynch_io
+ModelSim Info: # -- Compiling architecture behave of cycloneii_asynch_io
+ModelSim Info: # -- Loading entity cycloneii_asynch_io
+ModelSim Info: # -- Loading entity cycloneii_mux21
+ModelSim Info: # -- Compiling entity cycloneii_io
+ModelSim Info: # -- Compiling architecture structure of cycloneii_io
+ModelSim Info: # -- Loading package std_logic_unsigned
+ModelSim Info: # -- Compiling entity cycloneii_clk_delay_ctrl
+ModelSim Info: # -- Compiling architecture vital_clk_delay_ctrl of cycloneii_clk_delay_ctrl
+ModelSim Info: # -- Compiling entity cycloneii_clk_delay_cal_ctrl
+ModelSim Info: # -- Compiling architecture vital_clk_delay_cal_ctrl of cycloneii_clk_delay_cal_ctrl
+ModelSim Info: # -- Compiling entity cycloneii_mac_data_reg
+ModelSim Info: # -- Compiling architecture vital_cycloneii_mac_data_reg of cycloneii_mac_data_reg
+ModelSim Info: # -- Compiling entity cycloneii_mac_sign_reg
+ModelSim Info: # -- Compiling architecture cycloneii_mac_sign_reg of cycloneii_mac_sign_reg
+ModelSim Info: # -- Compiling entity cycloneii_mac_mult_internal
+ModelSim Info: # -- Compiling architecture vital_cycloneii_mac_mult_internal of cycloneii_mac_mult_internal
+ModelSim Info: # -- Loading entity cycloneii_mac_data_reg
+ModelSim Info: # -- Loading entity cycloneii_mac_sign_reg
+ModelSim Info: # -- Loading entity cycloneii_mac_mult_internal
+ModelSim Info: # -- Compiling entity cycloneii_mac_mult
+ModelSim Info: # -- Compiling architecture vital_cycloneii_mac_mult of cycloneii_mac_mult
+ModelSim Info: # -- Compiling entity cycloneii_mac_out
+ModelSim Info: # -- Compiling architecture vital_cycloneii_mac_out of cycloneii_mac_out
+ModelSim Info: # -- Compiling entity cycloneii_ena_reg
+ModelSim Info: # -- Compiling architecture behave of cycloneii_ena_reg
+ModelSim Info: # -- Loading entity cycloneii_ena_reg
+ModelSim Info: # -- Compiling entity cycloneii_clkctrl
+ModelSim Info: # -- Compiling architecture vital_clkctrl of cycloneii_clkctrl
+ModelSim Info: # vcom -work cycloneii /opt/quartus/eda/sim_lib/cycloneii_components.vhd
+ModelSim Info: # Model Technology ModelSim SE-64 vcom 6.3 Compiler 2007.05 May 4 2007
+ModelSim Info: # -- Loading package standard
+ModelSim Info: # -- Loading package std_logic_1164
+ModelSim Info: # -- Loading package vital_timing
+ModelSim Info: # -- Loading package vital_primitives
+ModelSim Info: # -- Loading package cycloneii_atom_pack
+ModelSim Info: # -- Compiling package cycloneii_components
+ModelSim Info: #
+ModelSim Info: # if {[file exists rtl_work]} {
+ModelSim Info: # vdel -lib rtl_work -all
+ModelSim Info: # }
+ModelSim Info: # vlib rtl_work
+ModelSim Info: # vmap work rtl_work
+ModelSim Info: # Modifying modelsim.ini
+ModelSim Info: #
+ModelSim Info: # vcom -work work /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo_pkg.vhd
+ModelSim Info: # Model Technology ModelSim SE-64 vcom 6.3 Compiler 2007.05 May 4 2007
+ModelSim Info: # -- Loading package standard
+ModelSim Info: # -- Loading package std_logic_1164
+ModelSim Info: # -- Compiling package demo_pkg
+ModelSim Info: # vcom -work work /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/pll.vhd
+ModelSim Info: # Model Technology ModelSim SE-64 vcom 6.3 Compiler 2007.05 May 4 2007
+ModelSim Info: # -- Loading package standard
+ModelSim Info: # -- Loading package std_logic_1164
+ModelSim Info: # -- Compiling entity pll
+ModelSim Info: # -- Compiling architecture syn of pll
+ModelSim Info: # vcom -work work /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo_top.vhd
+ModelSim Info: # Model Technology ModelSim SE-64 vcom 6.3 Compiler 2007.05 May 4 2007
+ModelSim Info: # -- Loading package standard
+ModelSim Info: # -- Loading package std_logic_1164
+ModelSim Info: # -- Compiling entity demo_top
+ModelSim Info: # -- Compiling architecture structure of demo_top
+ModelSim Info: # vcom -work work /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd
+ModelSim Info: # Model Technology ModelSim SE-64 vcom 6.3 Compiler 2007.05 May 4 2007
+ModelSim Info: # -- Loading package standard
+ModelSim Info: # -- Loading package std_logic_1164
+ModelSim Info: # -- Loading package numeric_std
+ModelSim Info: # -- Loading package demo_pkg
+ModelSim Info: # -- Compiling entity demo
+ModelSim Info: # -- Compiling architecture behav of demo
+ModelSim Info: #
+ModelSim Info: # do ../../../sim/demo_tb_rtl.do
+ModelSim Info: # compile testbench
+ModelSim Info: # vcom -work work ../../../sim/demo_tb.vhd
+ModelSim Info: # Model Technology ModelSim SE-64 vcom 6.3 Compiler 2007.05 May 4 2007
+ModelSim Info: # -- Loading package standard
+ModelSim Info: # -- Loading package std_logic_1164
+ModelSim Info: # -- Loading package demo_pkg
+ModelSim Info: # -- Compiling entity demo_tb
+ModelSim Info: # -- Compiling architecture behav of demo_tb
+ModelSim Info: #
+ModelSim Info: # start simulation
+ModelSim Info: # vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L cycloneii -L rtl_work -L work -voptargs="+acc" demo_tb
+ModelSim Info: # vsim -L altera -L lpm -L sgate -L altera_mf -L cycloneii -L rtl_work -L work -voptargs=\"+acc\" -t 1ps demo_tb
+ModelSim Info: # ** Note: (vsim-3812) Design is being optimized...
+ModelSim Info: # Loading std.standard
+ModelSim Info: # Loading ieee.std_logic_1164(body)
+ModelSim Info: # Loading work.demo_pkg
+ModelSim Info: # Loading work.demo_tb(behav)#1
+ModelSim Info: # Loading work.demo_top(structure)#1
+ModelSim Info: # Loading ieee.numeric_std(body)
+ModelSim Info: # Loading work.demo(behav)
+ModelSim Info: # Loading work.pll(syn)#1
+ModelSim Info: # Loading altera_mf.altera_device_families(body)
+ModelSim Info: # Loading std.textio(body)
+ModelSim Info: # Loading altera_mf.mf_pllpack(body)
+ModelSim Info: # Loading ieee.std_logic_arith(body)
+ModelSim Info: # Loading ieee.std_logic_unsigned(body)
+ModelSim Info: # Loading altera_mf.altpll(behavior)#1
+ModelSim Info: # Loading altera_mf.mf_stratixii_pll(vital_pll)#2
+ModelSim Info: # Loading altera_mf.arm_m_cntr(behave)
+ModelSim Info: # Loading altera_mf.arm_n_cntr(behave)
+ModelSim Info: # Loading altera_mf.arm_scale_cntr(behave)#1
+ModelSim Info: # view -undock wave
+ModelSim Info: # .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs.pw.wf
+ModelSim Info: #
+ModelSim Info: # add signals to waveform
+ModelSim Info: # add all testbench signals
+ModelSim Info: # add wave *
+ModelSim Info: #
+ModelSim Info: # add wave -divider PLL
+ModelSim Info: # add wave uut/pll_inst/c0
+ModelSim Info: #
+ModelSim Info: # add internal signals of unit under test
+ModelSim Info: # add wave -divider DEMO
+ModelSim Info: # add wave uut/demo_inst/counter
+ModelSim Info: # add wave uut/demo_inst/ledstate
+ModelSim Info: #
+ModelSim Info: # auto-run simulation
+ModelSim Info: # run 50 us
+ModelSim Info: # ** Note: StratixII PLL is enabled
+ModelSim Info: # Time: 0 ps Iteration: 2 Instance: /demo_tb/uut/pll_inst/altpll_component/cycloneii_altpll/m3
+ModelSim Info: # ** Note: StratixII PLL locked to incoming clock
+ModelSim Info: # Time: 220 ns Iteration: 4 Instance: /demo_tb/uut/pll_inst/altpll_component/cycloneii_altpll/m3
+ModelSim Info: # wave zoomfull
+ModelSim Info: # 0 ps
+ModelSim Info: # 52500 ns
+Info: NativeLink Simulation succeeded
+Info: Nativelink simulation process ended
--- /dev/null
+<internal_error>
+ <executable>quartus</executable>
+ <sub_system>THR</sub_system>
+ <file>/quartus/ccl/thr/thr_mutex_win32.c</file>
+ <line>306</line>
+ <callstack>
+ 0xfffffffff7fc981d: ccl_thr_win32 + 0xe81d (thr_os_error + 0xa0)
+ 0xfffffffff7fc990d: ccl_thr_win32 + 0xe90d (thr_windows_error + 0xa6)
+ 0xfffffffff7fc9cd8: ccl_thr_win32 + 0xecd8 (thr_mutex_unlock + 0x7b)
+ 0x0ce567a4: quartus + 0x4e0e7a4 (_ZN18PDB_SEGMENT_READERD1Ev + 0x74)
+ 0x0beaff91: quartus + 0x3e67f91 (_Z9pdb_read_I11PDB_ARCHIVE10RDB_REPORTEbRPT0_RT_PKc + 0xbf)
+ 0x0bebe7eb: quartus + 0x3e767eb (_ZN7DBM_PDBI10RDB_REPORTE9read_fileEPKcS3_ + 0x1fb)
+ 0x0bea55d2: quartus + 0x3e5d5d2 (_ZN10RDB_REPORT10get_reportERKN11_Dinkum_std12basic_stringIcNS0_11char_traitsIcEE17MEM_STL_ALLOCATORIcEEES8_PK10RDB_OBJECT + 0xf0)
+ 0x0bea61f6: quartus + 0x3e5e1f6 (_ZN10RDB_REPORT10get_reportERKN11_Dinkum_std12basic_stringIcNS0_11char_traitsIcEE17MEM_STL_ALLOCATORIcEEE15RDB_REPORT_TYPEPK10RDB_OBJECT + 0x44)
+ 0x0bea62ae: quartus + 0x3e5e2ae (_ZN16RDB_MANAGER_IMPL10get_reportERKN11_Dinkum_std12basic_stringIcNS0_11char_traitsIcEE17MEM_STL_ALLOCATORIcEEE15RDB_REPORT_TYPERS6_ + 0x3a)
+ 0x0bec9908: quartus + 0x3e81908 (_ZN13DBMUI_MANAGER14get_rdb_reportE15RDB_REPORT_TYPEPKc + 0x428)
+ 0x08d09aa5: quartus + 0xcc1aa5 (_ZN12PJN_H_C_TREE14get_rdb_reportEv + 0x75)
+ 0x08d070d1: quartus + 0xcbf0d1 (_ZN12PJN_H_C_TREE25get_resource_report_tableEv + 0x257)
+ 0x08d0810b: quartus + 0xcc010b (_ZN12PJN_H_C_TREE23insert_resource_columnsEv + 0x103)
+ 0x08d0301c: quartus + 0xcbb01c (_ZN12PJN_H_C_TREE22refresh_comp_hierarchyEb + 0x2c4)
+ 0x08d2bda6: quartus + 0xce3da6 (_ZN13PJN_NAVIGATOR22refresh_comp_hierarchyEv + 0x36)
+ 0x08d2be3d: quartus + 0xce3e3d (_ZN13PJN_NAVIGATOR20on_refresh_hierarchyEjl + 0x1d)
+ 0xfffffffff799832e: mfc400s + 0xcb32e (_ZN4CWnd8OnWndMsgEjjlPl + 0x22e)
+ 0xfffffffff7997d59: mfc400s + 0xcad59 (_ZN4CWnd10WindowProcEjjl + 0x39)
+ 0xfffffffff799c623: mfc400s + 0xcf623 (_Z14AfxCallWndProcP4CWndP6HWND__jjl + 0xc3)
+ 0xfffffffff799d0c3: mfc400s + 0xd00c3 (_Z10AfxWndProcP6HWND__jjl + 0x53)
+ 0xfffffffff7994e9b: mfc400s + 0xc7e9b (_Z14AfxWndProcBaseP6HWND__jjl + 0x5b)
+ 0xfffffffff72c4a51: gdiuser32 + 0x180a51 (MwCallCallWndProc + 0x171)
+ 0xfffffffff72d1891: gdiuser32 + 0x18d891 (MwIDispatchMessage + 0xa1)
+ 0xfffffffff72d1a4a: gdiuser32 + 0x18da4a (DispatchMessageA + 0x4a)
+ 0xfffffffff79f8fed: mfc400s + 0x12bfed (_ZN10CWinThread11PumpMessageEv + 0x7d)
+ 0xfffffffff799aa14: mfc400s + 0xcda14 (_ZN4CWnd12RunModalLoopEm + 0xe4)
+ 0xfffffffff79c9848: mfc400s + 0xfc848 (_ZN7CDialog7DoModalEv + 0x328)
+ 0x08a188e0: quartus + 0x9d08e0 (_ZN17MSW_IE_DLG_YES_NO7DoModalEv + 0x22)
+ 0x089d688d: quartus + 0x98e88d (_ZN11MSW_DISPLAY22internal_error_displayEN11_Dinkum_std12basic_stringIcNS0_11char_traitsIcEE17MEM_STL_ALLOCATORIcEEE + 0x5d1)
+ 0x0ce10783: quartus + 0x4dc8783 (_ZN10MSG_REPORT14internal_errorERKN11_Dinkum_std12basic_stringIcNS0_11char_traitsIcEE17MEM_STL_ALLOCATORIcEEE + 0xfb)
+ 0x0ce2a4a1: quartus + 0x4de24a1 (_ZN14MSG_ERROR_INFO8finalizeEv + 0x47)
+ 0x0ce2a6f2: quartus + 0x4de26f2 (_ZN18MSG_INTERNAL_ERROR6reportEPKcS1_S1_i + 0x72)
+ 0xfffffffff7fc981d: ccl_thr_win32 + 0xe81d (thr_os_error + 0xa0)
+ 0xfffffffff7fc990d: ccl_thr_win32 + 0xe90d (thr_windows_error + 0xa6)
+ 0xfffffffff7fc9cd8: ccl_thr_win32 + 0xecd8 (thr_mutex_unlock + 0x7b)
+ 0x0ce567a4: quartus + 0x4e0e7a4 (_ZN18PDB_SEGMENT_READERD1Ev + 0x74)
+ 0x0beaff91: quartus + 0x3e67f91 (_Z9pdb_read_I11PDB_ARCHIVE10RDB_REPORTEbRPT0_RT_PKc + 0xbf)
+ 0x0bebe7eb: quartus + 0x3e767eb (_ZN7DBM_PDBI10RDB_REPORTE9read_fileEPKcS3_ + 0x1fb)
+ 0x0bea55d2: quartus + 0x3e5d5d2 (_ZN10RDB_REPORT10get_reportERKN11_Dinkum_std12basic_stringIcNS0_11char_traitsIcEE17MEM_STL_ALLOCATORIcEEES8_PK10RDB_OBJECT + 0xf0)
+ 0x0bea61f6: quartus + 0x3e5e1f6 (_ZN10RDB_REPORT10get_reportERKN11_Dinkum_std12basic_stringIcNS0_11char_traitsIcEE17MEM_STL_ALLOCATORIcEEE15RDB_REPORT_TYPEPK10RDB_OBJECT + 0x44)
+ 0x0bea62ae: quartus + 0x3e5e2ae (_ZN16RDB_MANAGER_IMPL10get_reportERKN11_Dinkum_std12basic_stringIcNS0_11char_traitsIcEE17MEM_STL_ALLOCATORIcEEE15RDB_REPORT_TYPERS6_ + 0x3a)
+ 0x0bec9908: quartus + 0x3e81908 (_ZN13DBMUI_MANAGER14get_rdb_reportE15RDB_REPORT_TYPEPKc + 0x428)
+ 0x08a60959: quartus + 0xa18959 (_ZN8TMW_TREE25check_for_existing_reportEP14TMW_STEP_PARAM + 0x259)
+ 0x08a604e3: quartus + 0xa184e3 (_ZN8TMW_TREE28validate_view_report_commandEv + 0x79)
+ 0x08a56fe3: quartus + 0xa0efe3 (_ZN8TMW_TREE29validate_all_assignment_tasksEPb + 0x18f)
+ 0x08a57d47: quartus + 0xa0fd47 (_ZN8TMW_TREE10acf_updateEv + 0xb5)
+ 0x08a3e924: quartus + 0x9f6924 (_ZN7TMW_NTF15ntf_acf_changedEjl + 0x26)
+ 0x0ce02b27: quartus + 0x4dbab27 (_ZN17NTF_NOTIFY_TARGET19dispatch_notify_msgEPK14NTF_NOTIFY_MAPjjl + 0x57)
+ 0x0ce02b9e: quartus + 0x4dbab9e (_ZN17NTF_NOTIFY_TARGET13on_ntf_notifyEjjl + 0x34)
+ 0x0ce02dc0: quartus + 0x4dbadc0 (_ZN14NTF_NOTIFY_MGR16broadcast_notifyEjjlb + 0x96)
+ 0x0ce02e0f: quartus + 0x4dbae0f (_ZN14NTF_NOTIFY_MGR25broadcast_notify_ntf_onlyEjjlb + 0x2f)
+ 0x0cd92935: quartus + 0x4d4a935 (_ZN11ACF_MANAGER12write_unlockEb + 0x1e5)
+ 0x0cd89a59: quartus + 0x4d41a59 (_ZN19ACF_MANAGER_STORAGE11synchronizeEv + 0x789)
+ 0x0cda9ef4: quartus + 0x4d61ef4 (_ZN19ACF_MANAGER_STORAGE9read_lockEbbb + 0xa4)
+ 0x0cdaa0de: quartus + 0x4d620de (_ZN11ACF_MANAGER45has_any_settings_file_changed_since_last_readEbb + 0xfe)
+ 0x092b23e7: quartus + 0x126a3e7 (_ZN13AFC_MDI_FRAME10OnActivateEjP4CWndi + 0x1cb)
+ 0xfffffffff7998c20: mfc400s + 0xcbc20 (_ZN4CWnd8OnWndMsgEjjlPl + 0xb20)
+ 0x0894f635: quartus + 0x907635 (_ZN14PJM_MAIN_FRAME8OnWndMsgEjjlPl + 0x85)
+ 0xfffffffff7997d59: mfc400s + 0xcad59 (_ZN4CWnd10WindowProcEjjl + 0x39)
+ 0xfffffffff7e6d014: ot803as + 0x269014 (_ZN14SECMDIFrameWnd10WindowProcEjjl + 0x64)
+ 0xfffffffff799c623: mfc400s + 0xcf623 (_Z14AfxCallWndProcP4CWndP6HWND__jjl + 0xc3)
+ 0xfffffffff799d0c3: mfc400s + 0xd00c3 (_Z10AfxWndProcP6HWND__jjl + 0x53)
+ 0xfffffffff7994e9b: mfc400s + 0xc7e9b (_Z14AfxWndProcBaseP6HWND__jjl + 0x5b)
+ 0xfffffffff72c4a51: gdiuser32 + 0x180a51 (MwCallCallWndProc + 0x171)
+ 0xfffffffff72d05ca: gdiuser32 + 0x18c5ca (MwICallWindowProc + 0x7a)
+ 0xfffffffff72dca56: gdiuser32 + 0x198a56 (CallWindowProcA + 0x66)
+ 0x08963359: quartus + 0x91b359 (_ZN12CSubclassWnd10WindowProcEjjl + 0x9f)
+ 0x08960be3: quartus + 0x918be3 (_ZN16CCoolMenuManager10WindowProcEjjl + 0x199)
+ 0x08963497: quartus + 0x91b497 (_Z11HookWndProcP6HWND__jjl + 0xf1)
+ 0xfffffffff72c4a51: gdiuser32 + 0x180a51 (MwCallCallWndProc + 0x171)
+ 0xfffffffff72d17e5: gdiuser32 + 0x18d7e5 (MwInternalSendMessage + 0x45)
+ 0xfffffffff72d7a8e: gdiuser32 + 0x193a8e (xxxSendMessageTimeout + 0x27e)
+ 0xfffffffff72da021: gdiuser32 + 0x196021 (xxxSendMessage + 0x71)
+ 0xfffffffff72fcf01: gdiuser32 + 0x1b8f01 (ActivateThisWindow + 0x4a1)
+ 0xfffffffff72fda00: gdiuser32 + 0x1b9a00 (xxxActivateWindow + 0x210)
+ 0xfffffffff72da42e: gdiuser32 + 0x19642e (xxxMouseActivate + 0x11e)
+ 0xfffffffff72d6d62: gdiuser32 + 0x192d62 (MwEventSideEffects + 0x1712)
+ 0xfffffffff72d717d: gdiuser32 + 0x19317d (MwFindMatchingEventInQueue + 0x23d)
+ 0xfffffffff72db1c3: gdiuser32 + 0x1971c3 (MwGetMessageThreads + 0x643)
+ 0xfffffffff72dbbe0: gdiuser32 + 0x197be0 (GetMessageA + 0x60)
+ 0xfffffffff79f8faa: mfc400s + 0x12bfaa (_ZN10CWinThread11PumpMessageEv + 0x3a)
+ 0xfffffffff79f8aea: mfc400s + 0x12baea (_ZN10CWinThread3RunEv + 0x8a)
+ 0xfffffffff79fab59: mfc400s + 0x12db59 (_ZN7CWinApp3RunEv + 0x29)
+ 0x092ad6a9: quartus + 0x12656a9 (_ZN7AFC_APP19win_app_run_wrapperEPv + 0x1d)
+ 0xfffffffff7fc8f39: ccl_thr_win32 + 0xdf39 (thr_final_wrapper + 0xf)
+ 0x089b3372: quartus + 0x96b372 (_Z18mem_thread_wrapperPFPvS_ES_ + 0xd2)
+ 0x0cf2edb7: quartus + 0x4ee6db7 (_Z18err_thread_wrapperPFPvS_ES_ + 0x29)
+ 0xfffffffff7fc8fc7: ccl_thr_win32 + 0xdfc7 (thr_thread_wrapper + 0x2c)
+ 0x092ad810: quartus + 0x1265810 (_ZN7AFC_APP3RunEv + 0x160)
+ 0xfffffffff79a92ed: mfc400s + 0xdc2ed (_Z10AfxWinMainP11HINSTANCE__S0_Pci + 0xad)
+ 0x0cf45c33: quartus + 0x4efdc33 (WinMain + 0x53)
+ 0x089a1385: quartus + 0x959385 (main + 0x9d)
+ 0x0092bdec: c.so.6 + 0x15dec (__libc_start_main + 0xdc)
+ 0x088d6431: quartus + 0x88e431 (_ZN13SECControlBar17CalcDynamicLayoutEim + 0x91)
+ </callstack>
+ <error>
+Quartus II requested that Windows unlock a mutex, but Windows could not do so.
+Please report the full text of this message to Altera so we can investigate its causes.
+In the meantime, may wish to take the following steps to work around the problem:
+ * Disabled parallel compilation if it is enabled
+ * Ensure you have sufficient memory to run Quartus.
+ * Ensure all service packs and patches from Microsoft are installed
+
+Technical details:
+ * API: ReleaseMutex(mutex->m_os_mutex)
+ * Error: 288 (Attempt to release mutex not owned by caller)
+</error>
+ <date>Mon Mar 30 17:11:20 2009</date>
+ <version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Full Version</version>
+ <full_error>OS Failure: Windows could not unlock a mutex
+
+Quartus II requested that Windows unlock a mutex, but Windows could not do so.
+Please report the full text of this message to Altera so we can investigate its causes.
+In the meantime, may wish to take the following steps to work around the problem:
+ * Disabled parallel compilation if it is enabled
+ * Ensure you have sufficient memory to run Quartus.
+ * Ensure all service packs and patches from Microsoft are installed
+
+Technical details:
+ * API: ReleaseMutex(mutex->m_os_mutex)
+ * Error: 288 (Attempt to release mutex not owned by caller)
+
+Quartus II Version 8.1 Build 163 10/28/2008 SJ Full Version </full_error>
+</internal_error>
+
--- /dev/null
+-- Copyright (C) 1991-2007 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II"
+-- VERSION "Version 7.0 Build 33 02/05/2007 SJ Full Version"
+
+-- DATE "03/30/2009 19:53:36"
+
+--
+-- Device: Altera EP2C35F484C6 Package FBGA484
+--
+
+--
+-- This VHDL file should be used for ModelSim (VHDL) only
+--
+
+LIBRARY IEEE, cycloneii;
+USE IEEE.std_logic_1164.all;
+USE cycloneii.cycloneii_components.all;
+
+ENTITY demo_top IS
+ PORT (
+ LEDS : OUT std_logic_vector(7 DOWNTO 0);
+ CLK : IN std_logic;
+ RESET : IN std_logic
+ );
+END demo_top;
+
+ARCHITECTURE structure OF demo_top IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_LEDS : std_logic_vector(7 DOWNTO 0);
+SIGNAL ww_CLK : std_logic;
+SIGNAL ww_RESET : std_logic;
+SIGNAL \inst1|altpll_component|pll_INCLK_bus\ : std_logic_vector(1 DOWNTO 0);
+SIGNAL \inst1|altpll_component|pll_CLK_bus\ : std_logic_vector(2 DOWNTO 0);
+SIGNAL \inst1|altpll_component|_clk0~clkctrl_I_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \inst1|altpll_component|pll~CLK1\ : std_logic;
+SIGNAL \inst1|altpll_component|pll~CLK2\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~20\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~22\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[6]~24\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~22\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[6]~28\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[54]~25\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[53]~26\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[52]~27\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[50]~21\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[49]~22\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[59]~638\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[62]~641\ : std_logic;
+SIGNAL \inst|ledstate_next~434\ : std_logic;
+SIGNAL \inst|ledstate_next~435\ : std_logic;
+SIGNAL \CLK~combout\ : std_logic;
+SIGNAL \inst1|altpll_component|_clk0\ : std_logic;
+SIGNAL \inst1|altpll_component|_clk0~clkctrl\ : std_logic;
+SIGNAL \inst|Add0~101\ : std_logic;
+SIGNAL \inst|Add0~103\ : std_logic;
+SIGNAL \inst|Add0~105\ : std_logic;
+SIGNAL \inst|Add0~107\ : std_logic;
+SIGNAL \inst|Add0~108\ : std_logic;
+SIGNAL \inst|Add0~104\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~19\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~21\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~23\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[6]~25\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[48]~31\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[48]~23\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[1]~18\ : std_logic;
+SIGNAL \inst|Add0~96\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[54]~17\ : std_logic;
+SIGNAL \inst|Add0~106\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[53]~18\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[52]~19\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~16\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[50]~29\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~21\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~23\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~25\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~27\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[6]~29\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[7]~31\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[57]~636\ : std_logic;
+SIGNAL \RESET~combout\ : std_logic;
+SIGNAL \inst|Add0~97\ : std_logic;
+SIGNAL \inst|Add0~98\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[49]~30\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~20\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[58]~639\ : std_logic;
+SIGNAL \inst|Add0~99\ : std_logic;
+SIGNAL \inst|Add0~100\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~17\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~18\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[51]~28\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~24\ : std_logic;
+SIGNAL \inst|Add0~102\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[51]~20\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[60]~642\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~26\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[61]~640\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[0]~34\ : std_logic;
+SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[56]~637\ : std_logic;
+SIGNAL \inst|Equal1~58\ : std_logic;
+SIGNAL \inst|Equal1~59\ : std_logic;
+SIGNAL \inst|knightlight~1269\ : std_logic;
+SIGNAL \inst|knightlight~1270\ : std_logic;
+SIGNAL \inst|knightlight~1271\ : std_logic;
+SIGNAL \inst|knightlight~1272\ : std_logic;
+SIGNAL \inst|knightlight~1273\ : std_logic;
+SIGNAL \inst|knightlight~1274\ : std_logic;
+SIGNAL \inst|knightlight~1277\ : std_logic;
+SIGNAL \inst|knightlight~1275\ : std_logic;
+SIGNAL \inst|knightlight~1276\ : std_logic;
+SIGNAL \inst|ledstate_next~431\ : std_logic;
+SIGNAL \inst|ledstate_next~432\ : std_logic;
+SIGNAL \inst|ledstate_next~433\ : std_logic;
+SIGNAL \inst|ledstate_next~436\ : std_logic;
+SIGNAL \inst|ledstate\ : std_logic;
+SIGNAL \inst|knightlight~1267\ : std_logic;
+SIGNAL \inst|knightlight~1268\ : std_logic;
+SIGNAL \inst|knightlight~1265\ : std_logic;
+SIGNAL \inst|knightlight~1266\ : std_logic;
+SIGNAL \inst|knightlight~1264\ : std_logic;
+SIGNAL \inst|knightlight\ : std_logic_vector(7 DOWNTO 0);
+SIGNAL \inst|counter\ : std_logic_vector(6 DOWNTO 0);
+SIGNAL \inst|ALT_INV_knightlight\ : std_logic_vector(7 DOWNTO 0);
+SIGNAL \ALT_INV_RESET~combout\ : std_logic;
+
+BEGIN
+
+LEDS <= ww_LEDS;
+ww_CLK <= CLK;
+ww_RESET <= RESET;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+
+\inst1|altpll_component|pll_INCLK_bus\ <= (gnd & \CLK~combout\);
+
+\inst1|altpll_component|_clk0\ <= \inst1|altpll_component|pll_CLK_bus\(0);
+\inst1|altpll_component|pll~CLK1\ <= \inst1|altpll_component|pll_CLK_bus\(1);
+\inst1|altpll_component|pll~CLK2\ <= \inst1|altpll_component|pll_CLK_bus\(2);
+
+\inst1|altpll_component|_clk0~clkctrl_I_INCLK_bus\ <= (gnd & gnd & gnd & \inst1|altpll_component|_clk0\);
+\inst|ALT_INV_knightlight\(7) <= NOT \inst|knightlight\(7);
+\inst|ALT_INV_knightlight\(6) <= NOT \inst|knightlight\(6);
+\inst|ALT_INV_knightlight\(5) <= NOT \inst|knightlight\(5);
+\inst|ALT_INV_knightlight\(4) <= NOT \inst|knightlight\(4);
+\inst|ALT_INV_knightlight\(3) <= NOT \inst|knightlight\(3);
+\inst|ALT_INV_knightlight\(2) <= NOT \inst|knightlight\(2);
+\inst|ALT_INV_knightlight\(1) <= NOT \inst|knightlight\(1);
+\inst|ALT_INV_knightlight\(0) <= NOT \inst|knightlight\(0);
+\ALT_INV_RESET~combout\ <= NOT \RESET~combout\;
+
+\inst|counter[3]~I\ : cycloneii_lcell_ff
+PORT MAP (
+ clk => \inst1|altpll_component|_clk0~clkctrl\,
+ datain => \inst|Mod0|auto_generated|divider|divider|StageOut[59]~638\,
+ sclr => \ALT_INV_RESET~combout\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \inst|counter\(3));
+
+\inst|counter[6]~I\ : cycloneii_lcell_ff
+PORT MAP (
+ clk => \inst1|altpll_component|_clk0~clkctrl\,
+ datain => \inst|Mod0|auto_generated|divider|divider|StageOut[62]~641\,
+ sclr => \ALT_INV_RESET~combout\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \inst|counter\(6));
+
+\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~20_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~20\ = \inst|Add0~104\ & (GND # !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~19\) # !\inst|Add0~104\ &
+-- (\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~19\ $ GND)
+-- \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~21\ = CARRY(\inst|Add0~104\ # !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~19\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0011110011001111",
+ sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+ datab => \inst|Add0~104\,
+ datad => VCC,
+ cin => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~19\,
+ combout => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~20\,
+ cout => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~21\);
+
+\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~22_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~22\ = \inst|Add0~106\ & !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~21\ # !\inst|Add0~106\ & (\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~21\ #
+-- GND)
+-- \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~23\ = CARRY(!\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~21\ # !\inst|Add0~106\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0101101001011111",
+ sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+ dataa => \inst|Add0~106\,
+ datad => VCC,
+ cin => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~21\,
+ combout => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~22\,
+ cout => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~23\);
+
+\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[6]~24_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[6]~24\ = \inst|Add0~108\ & (\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~23\ $ GND) # !\inst|Add0~108\ &
+-- !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~23\ & VCC
+-- \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[6]~25\ = CARRY(\inst|Add0~108\ & !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~23\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1100001100001100",
+ sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+ datab => \inst|Add0~108\,
+ datad => VCC,
+ cin => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~23\,
+ combout => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[6]~24\,
+ cout => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[6]~25\);
+
+\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~22_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~22\ = \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~21\ & (\inst|Mod0|auto_generated|divider|divider|StageOut[50]~21\ #
+-- \inst|Mod0|auto_generated|divider|divider|StageOut[50]~29\) # !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~21\ & !\inst|Mod0|auto_generated|divider|divider|StageOut[50]~21\ &
+-- !\inst|Mod0|auto_generated|divider|divider|StageOut[50]~29\
+-- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~23\ = CARRY(!\inst|Mod0|auto_generated|divider|divider|StageOut[50]~21\ & !\inst|Mod0|auto_generated|divider|divider|StageOut[50]~29\ &
+-- !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~21\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1110000100000001",
+ sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+ dataa => \inst|Mod0|auto_generated|divider|divider|StageOut[50]~21\,
+ datab => \inst|Mod0|auto_generated|divider|divider|StageOut[50]~29\,
+ datad => VCC,
+ cin => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~21\,
+ combout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~22\,
+ cout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~23\);
+
+\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[6]~28_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[6]~28\ = \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~27\ & (\inst|Mod0|auto_generated|divider|divider|StageOut[53]~26\ #
+-- \inst|Mod0|auto_generated|divider|divider|StageOut[53]~18\) # !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~27\ & ((\inst|Mod0|auto_generated|divider|divider|StageOut[53]~26\ #
+-- \inst|Mod0|auto_generated|divider|divider|StageOut[53]~18\))
+-- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[6]~29\ = CARRY(!\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~27\ & (\inst|Mod0|auto_generated|divider|divider|StageOut[53]~26\ #
+-- \inst|Mod0|auto_generated|divider|divider|StageOut[53]~18\))
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1110000100001110",
+ sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+ dataa => \inst|Mod0|auto_generated|divider|divider|StageOut[53]~26\,
+ datab => \inst|Mod0|auto_generated|divider|divider|StageOut[53]~18\,
+ datad => VCC,
+ cin => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~27\,
+ combout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[6]~28\,
+ cout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[6]~29\);
+
+\inst|Mod0|auto_generated|divider|divider|StageOut[54]~25_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Mod0|auto_generated|divider|divider|StageOut[54]~25\ = !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\ & \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[6]~24\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0000111100000000",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ datac => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
+ datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[6]~24\,
+ combout => \inst|Mod0|auto_generated|divider|divider|StageOut[54]~25\);
+
+\inst|Mod0|auto_generated|divider|divider|StageOut[53]~26_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Mod0|auto_generated|divider|divider|StageOut[53]~26\ = \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~22\ & !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0000000010101010",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ dataa => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~22\,
+ datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
+ combout => \inst|Mod0|auto_generated|divider|divider|StageOut[53]~26\);
+
+\inst|Mod0|auto_generated|divider|divider|StageOut[52]~27_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Mod0|auto_generated|divider|divider|StageOut[52]~27\ = \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~20\ & !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0000000011110000",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ datac => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~20\,
+ datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
+ combout => \inst|Mod0|auto_generated|divider|divider|StageOut[52]~27\);
+
+\inst|Mod0|auto_generated|divider|divider|StageOut[50]~21_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Mod0|auto_generated|divider|divider|StageOut[50]~21\ = \inst|Add0~100\ & \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1111000000000000",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ datac => \inst|Add0~100\,
+ datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
+ combout => \inst|Mod0|auto_generated|divider|divider|StageOut[50]~21\);
+
+\inst|Mod0|auto_generated|divider|divider|StageOut[49]~22_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Mod0|auto_generated|divider|divider|StageOut[49]~22\ = \inst|Add0~98\ & \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1100110000000000",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ datab => \inst|Add0~98\,
+ datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
+ combout => \inst|Mod0|auto_generated|divider|divider|StageOut[49]~22\);
+
+\inst|Mod0|auto_generated|divider|divider|StageOut[59]~638_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Mod0|auto_generated|divider|divider|StageOut[59]~638\ = \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ & (\inst|Mod0|auto_generated|divider|divider|StageOut[50]~29\ # \inst|Mod0|auto_generated|divider|divider|StageOut[50]~21\)
+-- # !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ & (\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~22\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1110111011110000",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ dataa => \inst|Mod0|auto_generated|divider|divider|StageOut[50]~29\,
+ datab => \inst|Mod0|auto_generated|divider|divider|StageOut[50]~21\,
+ datac => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~22\,
+ datad => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\,
+ combout => \inst|Mod0|auto_generated|divider|divider|StageOut[59]~638\);
+
+\inst|Mod0|auto_generated|divider|divider|StageOut[62]~641_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Mod0|auto_generated|divider|divider|StageOut[62]~641\ = \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ & (\inst|Mod0|auto_generated|divider|divider|StageOut[53]~26\ # \inst|Mod0|auto_generated|divider|divider|StageOut[53]~18\)
+-- # !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ & (\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[6]~28\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1111101011001100",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ dataa => \inst|Mod0|auto_generated|divider|divider|StageOut[53]~26\,
+ datab => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[6]~28\,
+ datac => \inst|Mod0|auto_generated|divider|divider|StageOut[53]~18\,
+ datad => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\,
+ combout => \inst|Mod0|auto_generated|divider|divider|StageOut[62]~641\);
+
+\inst|ledstate_next~434_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|ledstate_next~434\ = \inst|knightlight\(3) $ \inst|Equal1~59\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0000111111110000",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ datac => \inst|knightlight\(3),
+ datad => \inst|Equal1~59\,
+ combout => \inst|ledstate_next~434\);
+
+\inst|ledstate_next~435_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|ledstate_next~435\ = \inst|knightlight\(4) & (\inst|ledstate\ # \inst|ledstate_next~434\) # !\inst|knightlight\(4) & (\inst|ledstate_next~434\ & \inst|ledstate\ # !\inst|ledstate_next~434\ & (\inst|knightlight\(7)))
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1110101111101000",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ dataa => \inst|ledstate\,
+ datab => \inst|knightlight\(4),
+ datac => \inst|ledstate_next~434\,
+ datad => \inst|knightlight\(7),
+ combout => \inst|ledstate_next~435\);
+
+\CLK~I\ : cycloneii_io
+-- pragma translate_off
+GENERIC MAP (
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "input",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => GND,
+ padio => ww_CLK,
+ combout => \CLK~combout\);
+
+\inst1|altpll_component|pll\ : cycloneii_pll
+-- pragma translate_off
+GENERIC MAP (
+ bandwidth => 0,
+ bandwidth_type => "auto",
+ c0_high => 4,
+ c0_initial => 1,
+ c0_low => 4,
+ c0_mode => "even",
+ c0_ph => 0,
+ c1_mode => "bypass",
+ c1_ph => 0,
+ c2_mode => "bypass",
+ c2_ph => 0,
+ charge_pump_current => 80,
+ clk0_counter => "c0",
+ clk0_divide_by => 1,
+ clk0_duty_cycle => 50,
+ clk0_multiply_by => 4,
+ clk0_phase_shift => "0",
+ clk1_duty_cycle => 50,
+ clk1_phase_shift => "0",
+ clk2_duty_cycle => 50,
+ clk2_phase_shift => "0",
+ compensate_clock => "clk0",
+ gate_lock_counter => 0,
+ gate_lock_signal => "no",
+ inclk0_input_frequency => 40000,
+ inclk1_input_frequency => 40000,
+ invalid_lock_multiplier => 5,
+ loop_filter_c => 3,
+ loop_filter_r => " 2.500000",
+ m => 32,
+ m_initial => 1,
+ m_ph => 0,
+ n => 1,
+ operation_mode => "normal",
+ pfd_max => 100000,
+ pfd_min => 2484,
+ pll_compensation_delay => 5370,
+ self_reset_on_gated_loss_lock => "off",
+ simulation_type => "timing",
+ valid_lock_multiplier => 1,
+ vco_center => 1333,
+ vco_max => 2000,
+ vco_min => 1000)
+-- pragma translate_on
+PORT MAP (
+ inclk => \inst1|altpll_component|pll_INCLK_bus\,
+ clk => \inst1|altpll_component|pll_CLK_bus\);
+
+\inst1|altpll_component|_clk0~clkctrl_I\ : cycloneii_clkctrl
+-- pragma translate_off
+GENERIC MAP (
+ clock_type => "global clock",
+ ena_register_mode => "falling edge")
+-- pragma translate_on
+PORT MAP (
+ inclk => \inst1|altpll_component|_clk0~clkctrl_I_INCLK_bus\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ outclk => \inst1|altpll_component|_clk0~clkctrl\);
+
+\inst|Add0~100_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Add0~100\ = \inst|counter\(3) & (\inst|Add0~99\ $ GND) # !\inst|counter\(3) & !\inst|Add0~99\ & VCC
+-- \inst|Add0~101\ = CARRY(\inst|counter\(3) & !\inst|Add0~99\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1010010100001010",
+ sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+ dataa => \inst|counter\(3),
+ datad => VCC,
+ cin => \inst|Add0~99\,
+ combout => \inst|Add0~100\,
+ cout => \inst|Add0~101\);
+
+\inst|Add0~102_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Add0~102\ = \inst|counter\(4) & !\inst|Add0~101\ # !\inst|counter\(4) & (\inst|Add0~101\ # GND)
+-- \inst|Add0~103\ = CARRY(!\inst|Add0~101\ # !\inst|counter\(4))
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0011110000111111",
+ sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+ datab => \inst|counter\(4),
+ datad => VCC,
+ cin => \inst|Add0~101\,
+ combout => \inst|Add0~102\,
+ cout => \inst|Add0~103\);
+
+\inst|Add0~104_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Add0~104\ = \inst|counter\(5) & (\inst|Add0~103\ $ GND) # !\inst|counter\(5) & !\inst|Add0~103\ & VCC
+-- \inst|Add0~105\ = CARRY(\inst|counter\(5) & !\inst|Add0~103\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1010010100001010",
+ sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+ dataa => \inst|counter\(5),
+ datad => VCC,
+ cin => \inst|Add0~103\,
+ combout => \inst|Add0~104\,
+ cout => \inst|Add0~105\);
+
+\inst|Add0~106_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Add0~106\ = \inst|counter\(6) & !\inst|Add0~105\ # !\inst|counter\(6) & (\inst|Add0~105\ # GND)
+-- \inst|Add0~107\ = CARRY(!\inst|Add0~105\ # !\inst|counter\(6))
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0101101001011111",
+ sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+ dataa => \inst|counter\(6),
+ datad => VCC,
+ cin => \inst|Add0~105\,
+ combout => \inst|Add0~106\,
+ cout => \inst|Add0~107\);
+
+\inst|Add0~108_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Add0~108\ = !\inst|Add0~107\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0000111100001111",
+ sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+ cin => \inst|Add0~107\,
+ combout => \inst|Add0~108\);
+
+\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~18_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~18\ = \inst|Add0~102\ & \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~17\ & VCC # !\inst|Add0~102\ &
+-- !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~17\
+-- \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~19\ = CARRY(!\inst|Add0~102\ & !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~17\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1010010100000101",
+ sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+ dataa => \inst|Add0~102\,
+ datad => VCC,
+ cin => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~17\,
+ combout => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~18\,
+ cout => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~19\);
+
+\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\ = !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[6]~25\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0000111100001111",
+ sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+ cin => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[6]~25\,
+ combout => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\);
+
+\inst|Mod0|auto_generated|divider|divider|StageOut[48]~31_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Mod0|auto_generated|divider|divider|StageOut[48]~31\ = \inst|Add0~96\ & !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0000000010101010",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ dataa => \inst|Add0~96\,
+ datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
+ combout => \inst|Mod0|auto_generated|divider|divider|StageOut[48]~31\);
+
+\inst|Mod0|auto_generated|divider|divider|StageOut[48]~23_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Mod0|auto_generated|divider|divider|StageOut[48]~23\ = \inst|Add0~96\ & \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1010101000000000",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ dataa => \inst|Add0~96\,
+ datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
+ combout => \inst|Mod0|auto_generated|divider|divider|StageOut[48]~23\);
+
+\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[1]~18_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[1]~18\ = \inst|Mod0|auto_generated|divider|divider|StageOut[48]~31\ # \inst|Mod0|auto_generated|divider|divider|StageOut[48]~23\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1111111111110000",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ datac => \inst|Mod0|auto_generated|divider|divider|StageOut[48]~31\,
+ datad => \inst|Mod0|auto_generated|divider|divider|StageOut[48]~23\,
+ combout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[1]~18\);
+
+\inst|Add0~96_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Add0~96\ = \inst|counter\(0) & (\inst|counter\(1) $ VCC) # !\inst|counter\(0) & \inst|counter\(1) & VCC
+-- \inst|Add0~97\ = CARRY(\inst|counter\(0) & \inst|counter\(1))
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0110011010001000",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ dataa => \inst|counter\(0),
+ datab => \inst|counter\(1),
+ datad => VCC,
+ combout => \inst|Add0~96\,
+ cout => \inst|Add0~97\);
+
+\inst|Mod0|auto_generated|divider|divider|StageOut[54]~17_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Mod0|auto_generated|divider|divider|StageOut[54]~17\ = \inst|Add0~108\ & \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1100110000000000",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ datab => \inst|Add0~108\,
+ datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
+ combout => \inst|Mod0|auto_generated|divider|divider|StageOut[54]~17\);
+
+\inst|Mod0|auto_generated|divider|divider|StageOut[53]~18_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Mod0|auto_generated|divider|divider|StageOut[53]~18\ = \inst|Add0~106\ & \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1100110000000000",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ datab => \inst|Add0~106\,
+ datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
+ combout => \inst|Mod0|auto_generated|divider|divider|StageOut[53]~18\);
+
+\inst|Mod0|auto_generated|divider|divider|StageOut[52]~19_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Mod0|auto_generated|divider|divider|StageOut[52]~19\ = \inst|Add0~104\ & \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1100110000000000",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ datab => \inst|Add0~104\,
+ datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
+ combout => \inst|Mod0|auto_generated|divider|divider|StageOut[52]~19\);
+
+\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~16_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~16\ = \inst|Add0~100\ $ VCC
+-- \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~17\ = CARRY(\inst|Add0~100\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0011001111001100",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ datab => \inst|Add0~100\,
+ datad => VCC,
+ combout => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~16\,
+ cout => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~17\);
+
+\inst|Mod0|auto_generated|divider|divider|StageOut[50]~29_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Mod0|auto_generated|divider|divider|StageOut[50]~29\ = \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~16\ & !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0000000011110000",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ datac => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~16\,
+ datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
+ combout => \inst|Mod0|auto_generated|divider|divider|StageOut[50]~29\);
+
+\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~20_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~20\ = (\inst|Mod0|auto_generated|divider|divider|StageOut[49]~22\ # \inst|Mod0|auto_generated|divider|divider|StageOut[49]~30\)
+-- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~21\ = CARRY(\inst|Mod0|auto_generated|divider|divider|StageOut[49]~22\ # \inst|Mod0|auto_generated|divider|divider|StageOut[49]~30\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0001000111101110",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ dataa => \inst|Mod0|auto_generated|divider|divider|StageOut[49]~22\,
+ datab => \inst|Mod0|auto_generated|divider|divider|StageOut[49]~30\,
+ datad => VCC,
+ combout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~20\,
+ cout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~21\);
+
+\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~24_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~24\ = \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~23\ & ((\inst|Mod0|auto_generated|divider|divider|StageOut[51]~20\ #
+-- \inst|Mod0|auto_generated|divider|divider|StageOut[51]~28\)) # !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~23\ & (\inst|Mod0|auto_generated|divider|divider|StageOut[51]~20\ #
+-- \inst|Mod0|auto_generated|divider|divider|StageOut[51]~28\ # GND)
+-- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~25\ = CARRY(\inst|Mod0|auto_generated|divider|divider|StageOut[51]~20\ # \inst|Mod0|auto_generated|divider|divider|StageOut[51]~28\ #
+-- !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~23\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0001111011101111",
+ sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+ dataa => \inst|Mod0|auto_generated|divider|divider|StageOut[51]~20\,
+ datab => \inst|Mod0|auto_generated|divider|divider|StageOut[51]~28\,
+ datad => VCC,
+ cin => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~23\,
+ combout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~24\,
+ cout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~25\);
+
+\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~26_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~26\ = \inst|Mod0|auto_generated|divider|divider|StageOut[52]~27\ & (!\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~25\) #
+-- !\inst|Mod0|auto_generated|divider|divider|StageOut[52]~27\ & (\inst|Mod0|auto_generated|divider|divider|StageOut[52]~19\ & !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~25\ #
+-- !\inst|Mod0|auto_generated|divider|divider|StageOut[52]~19\ & (\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~25\ # GND))
+-- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~27\ = CARRY(!\inst|Mod0|auto_generated|divider|divider|StageOut[52]~27\ & !\inst|Mod0|auto_generated|divider|divider|StageOut[52]~19\ #
+-- !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~25\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0001111000011111",
+ sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+ dataa => \inst|Mod0|auto_generated|divider|divider|StageOut[52]~27\,
+ datab => \inst|Mod0|auto_generated|divider|divider|StageOut[52]~19\,
+ datad => VCC,
+ cin => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~25\,
+ combout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~26\,
+ cout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~27\);
+
+\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[7]~31_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[7]~31\ = CARRY(!\inst|Mod0|auto_generated|divider|divider|StageOut[54]~25\ & !\inst|Mod0|auto_generated|divider|divider|StageOut[54]~17\ &
+-- !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[6]~29\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0000000000000001",
+ sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+ dataa => \inst|Mod0|auto_generated|divider|divider|StageOut[54]~25\,
+ datab => \inst|Mod0|auto_generated|divider|divider|StageOut[54]~17\,
+ datad => VCC,
+ cin => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[6]~29\,
+ cout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[7]~31\);
+
+\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ = \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[7]~31\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1111000011110000",
+ sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+ cin => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[7]~31\,
+ combout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\);
+
+\inst|Mod0|auto_generated|divider|divider|StageOut[57]~636_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Mod0|auto_generated|divider|divider|StageOut[57]~636\ = \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ & (\inst|Add0~96\) # !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ &
+-- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[1]~18\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1111000011001100",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ datab => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[1]~18\,
+ datac => \inst|Add0~96\,
+ datad => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\,
+ combout => \inst|Mod0|auto_generated|divider|divider|StageOut[57]~636\);
+
+\RESET~I\ : cycloneii_io
+-- pragma translate_off
+GENERIC MAP (
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "input",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => GND,
+ padio => ww_RESET,
+ combout => \RESET~combout\);
+
+\inst|counter[1]~I\ : cycloneii_lcell_ff
+PORT MAP (
+ clk => \inst1|altpll_component|_clk0~clkctrl\,
+ datain => \inst|Mod0|auto_generated|divider|divider|StageOut[57]~636\,
+ sclr => \ALT_INV_RESET~combout\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \inst|counter\(1));
+
+\inst|Add0~98_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Add0~98\ = \inst|counter\(2) & !\inst|Add0~97\ # !\inst|counter\(2) & (\inst|Add0~97\ # GND)
+-- \inst|Add0~99\ = CARRY(!\inst|Add0~97\ # !\inst|counter\(2))
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0011110000111111",
+ sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+ datab => \inst|counter\(2),
+ datad => VCC,
+ cin => \inst|Add0~97\,
+ combout => \inst|Add0~98\,
+ cout => \inst|Add0~99\);
+
+\inst|Mod0|auto_generated|divider|divider|StageOut[49]~30_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Mod0|auto_generated|divider|divider|StageOut[49]~30\ = \inst|Add0~98\ & !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0000000011001100",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ datab => \inst|Add0~98\,
+ datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
+ combout => \inst|Mod0|auto_generated|divider|divider|StageOut[49]~30\);
+
+\inst|Mod0|auto_generated|divider|divider|StageOut[58]~639_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Mod0|auto_generated|divider|divider|StageOut[58]~639\ = \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ & \inst|Add0~98\ # !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ &
+-- (\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~20\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1010101011110000",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ dataa => \inst|Add0~98\,
+ datac => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~20\,
+ datad => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\,
+ combout => \inst|Mod0|auto_generated|divider|divider|StageOut[58]~639\);
+
+\inst|counter[2]~I\ : cycloneii_lcell_ff
+PORT MAP (
+ clk => \inst1|altpll_component|_clk0~clkctrl\,
+ datain => \inst|Mod0|auto_generated|divider|divider|StageOut[58]~639\,
+ sclr => \ALT_INV_RESET~combout\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \inst|counter\(2));
+
+\inst|Mod0|auto_generated|divider|divider|StageOut[51]~28_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Mod0|auto_generated|divider|divider|StageOut[51]~28\ = \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~18\ & !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0000000011110000",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ datac => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~18\,
+ datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
+ combout => \inst|Mod0|auto_generated|divider|divider|StageOut[51]~28\);
+
+\inst|Mod0|auto_generated|divider|divider|StageOut[51]~20_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Mod0|auto_generated|divider|divider|StageOut[51]~20\ = \inst|Add0~102\ & \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1111000000000000",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ datac => \inst|Add0~102\,
+ datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
+ combout => \inst|Mod0|auto_generated|divider|divider|StageOut[51]~20\);
+
+\inst|Mod0|auto_generated|divider|divider|StageOut[60]~642_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Mod0|auto_generated|divider|divider|StageOut[60]~642\ = \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ & (\inst|Mod0|auto_generated|divider|divider|StageOut[51]~28\ # \inst|Mod0|auto_generated|divider|divider|StageOut[51]~20\)
+-- # !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ & (\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~24\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1111101011001100",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ dataa => \inst|Mod0|auto_generated|divider|divider|StageOut[51]~28\,
+ datab => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~24\,
+ datac => \inst|Mod0|auto_generated|divider|divider|StageOut[51]~20\,
+ datad => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\,
+ combout => \inst|Mod0|auto_generated|divider|divider|StageOut[60]~642\);
+
+\inst|counter[4]~I\ : cycloneii_lcell_ff
+PORT MAP (
+ clk => \inst1|altpll_component|_clk0~clkctrl\,
+ datain => \inst|Mod0|auto_generated|divider|divider|StageOut[60]~642\,
+ sclr => \ALT_INV_RESET~combout\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \inst|counter\(4));
+
+\inst|Mod0|auto_generated|divider|divider|StageOut[61]~640_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Mod0|auto_generated|divider|divider|StageOut[61]~640\ = \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ & (\inst|Mod0|auto_generated|divider|divider|StageOut[52]~27\ # \inst|Mod0|auto_generated|divider|divider|StageOut[52]~19\)
+-- # !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ & (\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~26\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1110111011110000",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ dataa => \inst|Mod0|auto_generated|divider|divider|StageOut[52]~27\,
+ datab => \inst|Mod0|auto_generated|divider|divider|StageOut[52]~19\,
+ datac => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~26\,
+ datad => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\,
+ combout => \inst|Mod0|auto_generated|divider|divider|StageOut[61]~640\);
+
+\inst|counter[5]~I\ : cycloneii_lcell_ff
+PORT MAP (
+ clk => \inst1|altpll_component|_clk0~clkctrl\,
+ datain => \inst|Mod0|auto_generated|divider|divider|StageOut[61]~640\,
+ sclr => \ALT_INV_RESET~combout\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \inst|counter\(5));
+
+\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[0]~34_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[0]~34\ = !\inst|counter\(0)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0000000011111111",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ datad => \inst|counter\(0),
+ combout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[0]~34\);
+
+\inst|Mod0|auto_generated|divider|divider|StageOut[56]~637_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Mod0|auto_generated|divider|divider|StageOut[56]~637\ = \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ & (!\inst|counter\(0)) # !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ &
+-- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[0]~34\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0000111111001100",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ datab => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[0]~34\,
+ datac => \inst|counter\(0),
+ datad => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\,
+ combout => \inst|Mod0|auto_generated|divider|divider|StageOut[56]~637\);
+
+\inst|counter[0]~I\ : cycloneii_lcell_ff
+PORT MAP (
+ clk => \inst1|altpll_component|_clk0~clkctrl\,
+ datain => \inst|Mod0|auto_generated|divider|divider|StageOut[56]~637\,
+ sclr => \ALT_INV_RESET~combout\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \inst|counter\(0));
+
+\inst|Equal1~58_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Equal1~58\ = !\inst|counter\(3) & \inst|counter\(0) & \inst|counter\(1) & !\inst|counter\(2)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0000000001000000",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ dataa => \inst|counter\(3),
+ datab => \inst|counter\(0),
+ datac => \inst|counter\(1),
+ datad => \inst|counter\(2),
+ combout => \inst|Equal1~58\);
+
+\inst|Equal1~59_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|Equal1~59\ = \inst|counter\(6) & !\inst|counter\(4) & \inst|counter\(5) & \inst|Equal1~58\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0010000000000000",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ dataa => \inst|counter\(6),
+ datab => \inst|counter\(4),
+ datac => \inst|counter\(5),
+ datad => \inst|Equal1~58\,
+ combout => \inst|Equal1~59\);
+
+\inst|knightlight~1269_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|knightlight~1269\ = \inst|ledstate\ & (\inst|knightlight\(5)) # !\inst|ledstate\ & \inst|knightlight\(3)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1111101001010000",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ dataa => \inst|ledstate\,
+ datac => \inst|knightlight\(3),
+ datad => \inst|knightlight\(5),
+ combout => \inst|knightlight~1269\);
+
+\inst|knightlight~1270_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|knightlight~1270\ = \inst|Equal1~59\ & \inst|knightlight~1269\ # !\inst|Equal1~59\ & (\inst|knightlight\(4))
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1100110011110000",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ datab => \inst|knightlight~1269\,
+ datac => \inst|knightlight\(4),
+ datad => \inst|Equal1~59\,
+ combout => \inst|knightlight~1270\);
+
+\inst|knightlight[4]~I\ : cycloneii_lcell_ff
+PORT MAP (
+ clk => \inst1|altpll_component|_clk0~clkctrl\,
+ datain => \inst|knightlight~1270\,
+ sclr => \ALT_INV_RESET~combout\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \inst|knightlight\(4));
+
+\inst|knightlight~1271_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|knightlight~1271\ = \inst|ledstate\ & (\inst|knightlight\(4)) # !\inst|ledstate\ & \inst|knightlight\(2)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1111110000001100",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ datab => \inst|knightlight\(2),
+ datac => \inst|ledstate\,
+ datad => \inst|knightlight\(4),
+ combout => \inst|knightlight~1271\);
+
+\inst|knightlight~1272_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|knightlight~1272\ = \inst|Equal1~59\ & (\inst|knightlight~1271\) # !\inst|Equal1~59\ & \inst|knightlight\(3)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1111110000110000",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ datab => \inst|Equal1~59\,
+ datac => \inst|knightlight\(3),
+ datad => \inst|knightlight~1271\,
+ combout => \inst|knightlight~1272\);
+
+\inst|knightlight[3]~I\ : cycloneii_lcell_ff
+PORT MAP (
+ clk => \inst1|altpll_component|_clk0~clkctrl\,
+ datain => \inst|knightlight~1272\,
+ sclr => \ALT_INV_RESET~combout\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \inst|knightlight\(3));
+
+\inst|knightlight~1273_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|knightlight~1273\ = \inst|ledstate\ & (\inst|knightlight\(3)) # !\inst|ledstate\ & \inst|knightlight\(1)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1100101011001010",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ dataa => \inst|knightlight\(1),
+ datab => \inst|knightlight\(3),
+ datac => \inst|ledstate\,
+ combout => \inst|knightlight~1273\);
+
+\inst|knightlight~1274_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|knightlight~1274\ = \inst|Equal1~59\ & (\inst|knightlight~1273\) # !\inst|Equal1~59\ & \inst|knightlight\(2)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1111101001010000",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ dataa => \inst|Equal1~59\,
+ datac => \inst|knightlight\(2),
+ datad => \inst|knightlight~1273\,
+ combout => \inst|knightlight~1274\);
+
+\inst|knightlight[2]~I\ : cycloneii_lcell_ff
+PORT MAP (
+ clk => \inst1|altpll_component|_clk0~clkctrl\,
+ datain => \inst|knightlight~1274\,
+ sdata => VCC,
+ sload => \ALT_INV_RESET~combout\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \inst|knightlight\(2));
+
+\inst|knightlight~1277_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|knightlight~1277\ = \inst|Equal1~59\ & \inst|ledstate\ & (\inst|knightlight\(1)) # !\inst|Equal1~59\ & (\inst|knightlight\(0))
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1101100001010000",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ dataa => \inst|Equal1~59\,
+ datab => \inst|ledstate\,
+ datac => \inst|knightlight\(0),
+ datad => \inst|knightlight\(1),
+ combout => \inst|knightlight~1277\);
+
+\inst|knightlight[0]~I\ : cycloneii_lcell_ff
+PORT MAP (
+ clk => \inst1|altpll_component|_clk0~clkctrl\,
+ datain => \inst|knightlight~1277\,
+ sdata => VCC,
+ sload => \ALT_INV_RESET~combout\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \inst|knightlight\(0));
+
+\inst|knightlight~1275_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|knightlight~1275\ = \inst|ledstate\ & \inst|knightlight\(2) # !\inst|ledstate\ & (\inst|knightlight\(0))
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1100111111000000",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ datab => \inst|knightlight\(2),
+ datac => \inst|ledstate\,
+ datad => \inst|knightlight\(0),
+ combout => \inst|knightlight~1275\);
+
+\inst|knightlight~1276_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|knightlight~1276\ = \inst|Equal1~59\ & (\inst|knightlight~1275\) # !\inst|Equal1~59\ & \inst|knightlight\(1)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1111101001010000",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ dataa => \inst|Equal1~59\,
+ datac => \inst|knightlight\(1),
+ datad => \inst|knightlight~1275\,
+ combout => \inst|knightlight~1276\);
+
+\inst|knightlight[1]~I\ : cycloneii_lcell_ff
+PORT MAP (
+ clk => \inst1|altpll_component|_clk0~clkctrl\,
+ datain => \inst|knightlight~1276\,
+ sdata => VCC,
+ sload => \ALT_INV_RESET~combout\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \inst|knightlight\(1));
+
+\inst|ledstate_next~431_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|ledstate_next~431\ = \inst|knightlight\(2) & (\inst|knightlight\(6) # \inst|knightlight\(5)) # !\inst|knightlight\(2) & \inst|knightlight\(6) & \inst|knightlight\(5)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1111110011000000",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ datab => \inst|knightlight\(2),
+ datac => \inst|knightlight\(6),
+ datad => \inst|knightlight\(5),
+ combout => \inst|ledstate_next~431\);
+
+\inst|ledstate_next~432_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|ledstate_next~432\ = \inst|ledstate\ & \inst|knightlight\(2) & \inst|knightlight\(1) & !\inst|ledstate_next~431\ # !\inst|ledstate\ & !\inst|knightlight\(2) & !\inst|knightlight\(1) & \inst|ledstate_next~431\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0000000110000000",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ dataa => \inst|ledstate\,
+ datab => \inst|knightlight\(2),
+ datac => \inst|knightlight\(1),
+ datad => \inst|ledstate_next~431\,
+ combout => \inst|ledstate_next~432\);
+
+\inst|ledstate_next~433_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|ledstate_next~433\ = \inst|knightlight\(0) # \inst|knightlight\(3)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1111111111001100",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ datab => \inst|knightlight\(0),
+ datad => \inst|knightlight\(3),
+ combout => \inst|ledstate_next~433\);
+
+\inst|ledstate_next~436_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|ledstate_next~436\ = \inst|ledstate_next~435\ & (\inst|ledstate\ # \inst|ledstate_next~432\ & !\inst|ledstate_next~433\) # !\inst|ledstate_next~435\ & \inst|ledstate\ & (!\inst|ledstate_next~433\ # !\inst|ledstate_next~432\)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1011000011111000",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ dataa => \inst|ledstate_next~435\,
+ datab => \inst|ledstate_next~432\,
+ datac => \inst|ledstate\,
+ datad => \inst|ledstate_next~433\,
+ combout => \inst|ledstate_next~436\);
+
+\inst|ledstate~I\ : cycloneii_lcell_ff
+PORT MAP (
+ clk => \inst1|altpll_component|_clk0~clkctrl\,
+ datain => \inst|ledstate_next~436\,
+ sclr => \ALT_INV_RESET~combout\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \inst|ledstate\);
+
+\inst|knightlight~1267_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|knightlight~1267\ = \inst|ledstate\ & \inst|knightlight\(6) # !\inst|ledstate\ & (\inst|knightlight\(4))
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1100111111000000",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ datab => \inst|knightlight\(6),
+ datac => \inst|ledstate\,
+ datad => \inst|knightlight\(4),
+ combout => \inst|knightlight~1267\);
+
+\inst|knightlight~1268_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|knightlight~1268\ = \inst|Equal1~59\ & (\inst|knightlight~1267\) # !\inst|Equal1~59\ & \inst|knightlight\(5)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1111110000110000",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ datab => \inst|Equal1~59\,
+ datac => \inst|knightlight\(5),
+ datad => \inst|knightlight~1267\,
+ combout => \inst|knightlight~1268\);
+
+\inst|knightlight[5]~I\ : cycloneii_lcell_ff
+PORT MAP (
+ clk => \inst1|altpll_component|_clk0~clkctrl\,
+ datain => \inst|knightlight~1268\,
+ sclr => \ALT_INV_RESET~combout\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \inst|knightlight\(5));
+
+\inst|knightlight~1265_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|knightlight~1265\ = \inst|ledstate\ & (\inst|knightlight\(7)) # !\inst|ledstate\ & \inst|knightlight\(5)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1111110000001100",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ datab => \inst|knightlight\(5),
+ datac => \inst|ledstate\,
+ datad => \inst|knightlight\(7),
+ combout => \inst|knightlight~1265\);
+
+\inst|knightlight~1266_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|knightlight~1266\ = \inst|Equal1~59\ & (\inst|knightlight~1265\) # !\inst|Equal1~59\ & \inst|knightlight\(6)
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1111110000110000",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ datab => \inst|Equal1~59\,
+ datac => \inst|knightlight\(6),
+ datad => \inst|knightlight~1265\,
+ combout => \inst|knightlight~1266\);
+
+\inst|knightlight[6]~I\ : cycloneii_lcell_ff
+PORT MAP (
+ clk => \inst1|altpll_component|_clk0~clkctrl\,
+ datain => \inst|knightlight~1266\,
+ sclr => \ALT_INV_RESET~combout\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \inst|knightlight\(6));
+
+\inst|knightlight~1264_I\ : cycloneii_lcell_comb
+-- Equation(s):
+-- \inst|knightlight~1264\ = \inst|Equal1~59\ & !\inst|ledstate\ & \inst|knightlight\(6) # !\inst|Equal1~59\ & (\inst|knightlight\(7))
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "0100010011110000",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ dataa => \inst|ledstate\,
+ datab => \inst|knightlight\(6),
+ datac => \inst|knightlight\(7),
+ datad => \inst|Equal1~59\,
+ combout => \inst|knightlight~1264\);
+
+\inst|knightlight[7]~I\ : cycloneii_lcell_ff
+PORT MAP (
+ clk => \inst1|altpll_component|_clk0~clkctrl\,
+ datain => \inst|knightlight~1264\,
+ sclr => \ALT_INV_RESET~combout\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ regout => \inst|knightlight\(7));
+
+\LEDS[7]~I\ : cycloneii_io
+-- pragma translate_off
+GENERIC MAP (
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \inst|ALT_INV_knightlight\(7),
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_LEDS(7));
+
+\LEDS[6]~I\ : cycloneii_io
+-- pragma translate_off
+GENERIC MAP (
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \inst|ALT_INV_knightlight\(6),
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_LEDS(6));
+
+\LEDS[5]~I\ : cycloneii_io
+-- pragma translate_off
+GENERIC MAP (
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \inst|ALT_INV_knightlight\(5),
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_LEDS(5));
+
+\LEDS[4]~I\ : cycloneii_io
+-- pragma translate_off
+GENERIC MAP (
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \inst|ALT_INV_knightlight\(4),
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_LEDS(4));
+
+\LEDS[3]~I\ : cycloneii_io
+-- pragma translate_off
+GENERIC MAP (
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \inst|ALT_INV_knightlight\(3),
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_LEDS(3));
+
+\LEDS[2]~I\ : cycloneii_io
+-- pragma translate_off
+GENERIC MAP (
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \inst|ALT_INV_knightlight\(2),
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_LEDS(2));
+
+\LEDS[1]~I\ : cycloneii_io
+-- pragma translate_off
+GENERIC MAP (
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \inst|ALT_INV_knightlight\(1),
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_LEDS(1));
+
+\LEDS[0]~I\ : cycloneii_io
+-- pragma translate_off
+GENERIC MAP (
+ input_async_reset => "none",
+ input_power_up => "low",
+ input_register_mode => "none",
+ input_sync_reset => "none",
+ oe_async_reset => "none",
+ oe_power_up => "low",
+ oe_register_mode => "none",
+ oe_sync_reset => "none",
+ operation_mode => "output",
+ output_async_reset => "none",
+ output_power_up => "low",
+ output_register_mode => "none",
+ output_sync_reset => "none")
+-- pragma translate_on
+PORT MAP (
+ datain => \inst|ALT_INV_knightlight\(0),
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ devoe => ww_devoe,
+ oe => VCC,
+ padio => ww_LEDS(0));
+END structure;
+
+
--- /dev/null
+vendor_name = ModelSim
+source_file = 1, /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo_pkg.vhd
+source_file = 1, /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd
+source_file = 1, /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/pll.vhd
+source_file = 1, /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo_top.bdf
+source_file = 1, /opt/quartus/libraries/megafunctions/altpll.tdf
+source_file = 1, /opt/quartus/libraries/megafunctions/aglobal70.inc
+source_file = 1, /opt/quartus/libraries/megafunctions/stratix_pll.inc
+source_file = 1, /opt/quartus/libraries/megafunctions/stratixii_pll.inc
+source_file = 1, /opt/quartus/libraries/megafunctions/cycloneii_pll.inc
+source_file = 1, /opt/quartus/libraries/megafunctions/cbx.lst
+source_file = 1, /opt/quartus/libraries/megafunctions/lpm_divide.tdf
+source_file = 1, /opt/quartus/libraries/megafunctions/abs_divider.inc
+source_file = 1, /opt/quartus/libraries/megafunctions/sign_div_unsign.inc
+source_file = 1, /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/lpm_divide_85m.tdf
+source_file = 1, /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/sign_div_unsign_fkh.tdf
+source_file = 1, /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf
+source_file = 1, /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/add_sub_lkc.tdf
+source_file = 1, /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/add_sub_mkc.tdf
+design_name = demo_top
+instance = comp, \inst|counter[3]~I\, inst|counter[3], demo_top, 1
+instance = comp, \inst|counter[6]~I\, inst|counter[6], demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~20_I\, inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~20, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~22_I\, inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~22, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[6]~24_I\, inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[6]~24, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~22_I\, inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~22, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[6]~28_I\, inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[6]~28, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[54]~25_I\, inst|Mod0|auto_generated|divider|divider|StageOut[54]~25, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[53]~26_I\, inst|Mod0|auto_generated|divider|divider|StageOut[53]~26, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[52]~27_I\, inst|Mod0|auto_generated|divider|divider|StageOut[52]~27, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[50]~21_I\, inst|Mod0|auto_generated|divider|divider|StageOut[50]~21, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[49]~22_I\, inst|Mod0|auto_generated|divider|divider|StageOut[49]~22, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[59]~638_I\, inst|Mod0|auto_generated|divider|divider|StageOut[59]~638, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[62]~641_I\, inst|Mod0|auto_generated|divider|divider|StageOut[62]~641, demo_top, 1
+instance = comp, \inst|ledstate_next~434_I\, inst|ledstate_next~434, demo_top, 1
+instance = comp, \inst|ledstate_next~435_I\, inst|ledstate_next~435, demo_top, 1
+instance = comp, \CLK~I\, CLK, demo_top, 1
+instance = comp, \inst1|altpll_component|pll\, inst1|altpll_component|pll, demo_top, 1
+instance = comp, \inst1|altpll_component|_clk0~clkctrl_I\, inst1|altpll_component|_clk0~clkctrl, demo_top, 1
+instance = comp, \inst|Add0~100_I\, inst|Add0~100, demo_top, 1
+instance = comp, \inst|Add0~102_I\, inst|Add0~102, demo_top, 1
+instance = comp, \inst|Add0~104_I\, inst|Add0~104, demo_top, 1
+instance = comp, \inst|Add0~106_I\, inst|Add0~106, demo_top, 1
+instance = comp, \inst|Add0~108_I\, inst|Add0~108, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~18_I\, inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~18, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26_I\, inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[48]~31_I\, inst|Mod0|auto_generated|divider|divider|StageOut[48]~31, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[48]~23_I\, inst|Mod0|auto_generated|divider|divider|StageOut[48]~23, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[1]~18_I\, inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[1]~18, demo_top, 1
+instance = comp, \inst|Add0~96_I\, inst|Add0~96, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[54]~17_I\, inst|Mod0|auto_generated|divider|divider|StageOut[54]~17, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[53]~18_I\, inst|Mod0|auto_generated|divider|divider|StageOut[53]~18, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[52]~19_I\, inst|Mod0|auto_generated|divider|divider|StageOut[52]~19, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~16_I\, inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~16, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[50]~29_I\, inst|Mod0|auto_generated|divider|divider|StageOut[50]~29, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~20_I\, inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~20, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~24_I\, inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~24, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~26_I\, inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~26, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[7]~31_I\, inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[7]~31, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32_I\, inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[57]~636_I\, inst|Mod0|auto_generated|divider|divider|StageOut[57]~636, demo_top, 1
+instance = comp, \RESET~I\, RESET, demo_top, 1
+instance = comp, \inst|counter[1]~I\, inst|counter[1], demo_top, 1
+instance = comp, \inst|Add0~98_I\, inst|Add0~98, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[49]~30_I\, inst|Mod0|auto_generated|divider|divider|StageOut[49]~30, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[58]~639_I\, inst|Mod0|auto_generated|divider|divider|StageOut[58]~639, demo_top, 1
+instance = comp, \inst|counter[2]~I\, inst|counter[2], demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[51]~28_I\, inst|Mod0|auto_generated|divider|divider|StageOut[51]~28, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[51]~20_I\, inst|Mod0|auto_generated|divider|divider|StageOut[51]~20, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[60]~642_I\, inst|Mod0|auto_generated|divider|divider|StageOut[60]~642, demo_top, 1
+instance = comp, \inst|counter[4]~I\, inst|counter[4], demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[61]~640_I\, inst|Mod0|auto_generated|divider|divider|StageOut[61]~640, demo_top, 1
+instance = comp, \inst|counter[5]~I\, inst|counter[5], demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[0]~34_I\, inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[0]~34, demo_top, 1
+instance = comp, \inst|Mod0|auto_generated|divider|divider|StageOut[56]~637_I\, inst|Mod0|auto_generated|divider|divider|StageOut[56]~637, demo_top, 1
+instance = comp, \inst|counter[0]~I\, inst|counter[0], demo_top, 1
+instance = comp, \inst|Equal1~58_I\, inst|Equal1~58, demo_top, 1
+instance = comp, \inst|Equal1~59_I\, inst|Equal1~59, demo_top, 1
+instance = comp, \inst|knightlight~1269_I\, inst|knightlight~1269, demo_top, 1
+instance = comp, \inst|knightlight~1270_I\, inst|knightlight~1270, demo_top, 1
+instance = comp, \inst|knightlight[4]~I\, inst|knightlight[4], demo_top, 1
+instance = comp, \inst|knightlight~1271_I\, inst|knightlight~1271, demo_top, 1
+instance = comp, \inst|knightlight~1272_I\, inst|knightlight~1272, demo_top, 1
+instance = comp, \inst|knightlight[3]~I\, inst|knightlight[3], demo_top, 1
+instance = comp, \inst|knightlight~1273_I\, inst|knightlight~1273, demo_top, 1
+instance = comp, \inst|knightlight~1274_I\, inst|knightlight~1274, demo_top, 1
+instance = comp, \inst|knightlight[2]~I\, inst|knightlight[2], demo_top, 1
+instance = comp, \inst|knightlight~1277_I\, inst|knightlight~1277, demo_top, 1
+instance = comp, \inst|knightlight[0]~I\, inst|knightlight[0], demo_top, 1
+instance = comp, \inst|knightlight~1275_I\, inst|knightlight~1275, demo_top, 1
+instance = comp, \inst|knightlight~1276_I\, inst|knightlight~1276, demo_top, 1
+instance = comp, \inst|knightlight[1]~I\, inst|knightlight[1], demo_top, 1
+instance = comp, \inst|ledstate_next~431_I\, inst|ledstate_next~431, demo_top, 1
+instance = comp, \inst|ledstate_next~432_I\, inst|ledstate_next~432, demo_top, 1
+instance = comp, \inst|ledstate_next~433_I\, inst|ledstate_next~433, demo_top, 1
+instance = comp, \inst|ledstate_next~436_I\, inst|ledstate_next~436, demo_top, 1
+instance = comp, \inst|ledstate~I\, inst|ledstate, demo_top, 1
+instance = comp, \inst|knightlight~1267_I\, inst|knightlight~1267, demo_top, 1
+instance = comp, \inst|knightlight~1268_I\, inst|knightlight~1268, demo_top, 1
+instance = comp, \inst|knightlight[5]~I\, inst|knightlight[5], demo_top, 1
+instance = comp, \inst|knightlight~1265_I\, inst|knightlight~1265, demo_top, 1
+instance = comp, \inst|knightlight~1266_I\, inst|knightlight~1266, demo_top, 1
+instance = comp, \inst|knightlight[6]~I\, inst|knightlight[6], demo_top, 1
+instance = comp, \inst|knightlight~1264_I\, inst|knightlight~1264, demo_top, 1
+instance = comp, \inst|knightlight[7]~I\, inst|knightlight[7], demo_top, 1
+instance = comp, \LEDS[7]~I\, LEDS[7], demo_top, 1
+instance = comp, \LEDS[6]~I\, LEDS[6], demo_top, 1
+instance = comp, \LEDS[5]~I\, LEDS[5], demo_top, 1
+instance = comp, \LEDS[4]~I\, LEDS[4], demo_top, 1
+instance = comp, \LEDS[3]~I\, LEDS[3], demo_top, 1
+instance = comp, \LEDS[2]~I\, LEDS[2], demo_top, 1
+instance = comp, \LEDS[1]~I\, LEDS[1], demo_top, 1
+instance = comp, \LEDS[0]~I\, LEDS[0], demo_top, 1
--- /dev/null
+// Copyright (C) 1991-2007 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions
+// and other software and tools, and its AMPP partner logic
+// functions, and any output files from any of the foregoing
+// (including device programming or simulation files), and any
+// associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License
+// Subscription Agreement, Altera MegaCore Function License
+// Agreement, or other applicable license agreement, including,
+// without limitation, that your use is for the sole purpose of
+// programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details.
+
+
+//
+// Device: Altera EP2C35F484C6 Package FBGA484
+//
+
+//
+// This SDF file should be used for ModelSim (VHDL) only
+//
+
+(DELAYFILE
+ (SDFVERSION "2.1")
+ (DESIGN "demo_top")
+ (DATE "03/30/2009 19:53:36")
+ (VENDOR "Altera")
+ (PROGRAM "Quartus II")
+ (VERSION "Version 7.0 Build 33 02/05/2007 SJ Full Version")
+ (DIVIDER .)
+ (TIMESCALE 1 ps)
+
+ (CELL
+ (CELLTYPE "cycloneii_lcell_ff")
+ (INSTANCE \\inst\|counter\[3\]\~I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT clk (1557:1557:1557) (1559:1559:1559))
+ (PORT datain (84:84:84) (84:84:84))
+ (PORT sclr (6919:6919:6919) (7003:7003:7003))
+ (IOPATH (posedge clk) regout (250:250:250) (250:250:250))
+ )
+ )
+ (TIMINGCHECK
+ (HOLD datain (posedge clk) (266:266:266))
+ (HOLD sclr (posedge clk) (266:266:266))
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_ff")
+ (INSTANCE \\inst\|counter\[6\]\~I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT clk (1557:1557:1557) (1559:1559:1559))
+ (PORT datain (84:84:84) (84:84:84))
+ (PORT sclr (6919:6919:6919) (7003:7003:7003))
+ (IOPATH (posedge clk) regout (250:250:250) (250:250:250))
+ )
+ )
+ (TIMINGCHECK
+ (HOLD datain (posedge clk) (266:266:266))
+ (HOLD sclr (posedge clk) (266:266:266))
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Mod0\|auto_generated\|divider\|divider\|add_sub_6_result_int\[4\]\~20_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (258:258:258) (226:226:226))
+ (IOPATH datab combout (420:420:420) (420:420:420))
+ (IOPATH datab cout (393:393:393) (393:393:393))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ (IOPATH cin combout (410:410:410) (410:410:410))
+ (IOPATH cin cout (71:71:71) (71:71:71))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Mod0\|auto_generated\|divider\|divider\|add_sub_6_result_int\[5\]\~22_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (276:276:276) (238:238:238))
+ (IOPATH dataa combout (438:438:438) (438:438:438))
+ (IOPATH dataa cout (414:414:414) (414:414:414))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ (IOPATH cin combout (410:410:410) (410:410:410))
+ (IOPATH cin cout (71:71:71) (71:71:71))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Mod0\|auto_generated\|divider\|divider\|add_sub_6_result_int\[6\]\~24_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (257:257:257) (224:224:224))
+ (IOPATH datab combout (420:420:420) (420:420:420))
+ (IOPATH datab cout (393:393:393) (393:393:393))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ (IOPATH cin combout (410:410:410) (410:410:410))
+ (IOPATH cin cout (71:71:71) (71:71:71))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Mod0\|auto_generated\|divider\|divider\|add_sub_7_result_int\[3\]\~22_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (272:272:272) (232:232:232))
+ (PORT datab (266:266:266) (236:236:236))
+ (IOPATH dataa combout (413:413:413) (413:413:413))
+ (IOPATH dataa cout (414:414:414) (414:414:414))
+ (IOPATH datab combout (393:393:393) (393:393:393))
+ (IOPATH datab cout (393:393:393) (393:393:393))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ (IOPATH cin combout (410:410:410) (410:410:410))
+ (IOPATH cin cout (71:71:71) (71:71:71))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Mod0\|auto_generated\|divider\|divider\|add_sub_7_result_int\[6\]\~28_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (685:685:685) (583:583:583))
+ (PORT datab (442:442:442) (377:377:377))
+ (IOPATH dataa combout (438:438:438) (438:438:438))
+ (IOPATH dataa cout (414:414:414) (414:414:414))
+ (IOPATH datab combout (420:420:420) (420:420:420))
+ (IOPATH datab cout (393:393:393) (393:393:393))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ (IOPATH cin combout (410:410:410) (410:410:410))
+ (IOPATH cin cout (71:71:71) (71:71:71))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Mod0\|auto_generated\|divider\|divider\|StageOut\[54\]\~25_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (680:680:680) (629:629:629))
+ (PORT datad (432:432:432) (371:371:371))
+ (IOPATH datac combout (275:275:275) (275:275:275))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Mod0\|auto_generated\|divider\|divider\|StageOut\[53\]\~26_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (451:451:451) (378:378:378))
+ (PORT datad (524:524:524) (474:474:474))
+ (IOPATH dataa combout (438:438:438) (438:438:438))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Mod0\|auto_generated\|divider\|divider\|StageOut\[52\]\~27_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (430:430:430) (363:363:363))
+ (PORT datad (519:519:519) (470:470:470))
+ (IOPATH datac combout (275:275:275) (275:275:275))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Mod0\|auto_generated\|divider\|divider\|StageOut\[50\]\~21_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (663:663:663) (569:569:569))
+ (PORT datad (705:705:705) (625:625:625))
+ (IOPATH datac combout (271:271:271) (271:271:271))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Mod0\|auto_generated\|divider\|divider\|StageOut\[49\]\~22_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (670:670:670) (576:576:576))
+ (PORT datad (705:705:705) (626:626:626))
+ (IOPATH datab combout (393:393:393) (393:393:393))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Mod0\|auto_generated\|divider\|divider\|StageOut\[59\]\~638_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (471:471:471) (404:404:404))
+ (PORT datab (446:446:446) (384:384:384))
+ (PORT datac (253:253:253) (219:219:219))
+ (PORT datad (271:271:271) (244:244:244))
+ (IOPATH dataa combout (438:438:438) (438:438:438))
+ (IOPATH datab combout (419:419:419) (419:419:419))
+ (IOPATH datac combout (275:275:275) (275:275:275))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Mod0\|auto_generated\|divider\|divider\|StageOut\[62\]\~641_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (689:689:689) (587:587:587))
+ (PORT datab (255:255:255) (224:224:224))
+ (PORT datac (441:441:441) (374:374:374))
+ (PORT datad (274:274:274) (247:247:247))
+ (IOPATH dataa combout (437:437:437) (437:437:437))
+ (IOPATH datab combout (420:420:420) (420:420:420))
+ (IOPATH datac combout (271:271:271) (271:271:271))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|ledstate_next\~434_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (355:355:355) (329:329:329))
+ (PORT datad (1719:1719:1719) (1734:1734:1734))
+ (IOPATH datac combout (275:275:275) (275:275:275))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|ledstate_next\~435_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (386:386:386) (355:355:355))
+ (PORT datab (342:342:342) (313:313:313))
+ (PORT datac (287:287:287) (263:263:263))
+ (PORT datad (485:485:485) (474:474:474))
+ (IOPATH dataa combout (438:438:438) (438:438:438))
+ (IOPATH datab combout (420:420:420) (420:420:420))
+ (IOPATH datac combout (275:275:275) (275:275:275))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_asynch_io")
+ (INSTANCE \\CLK\~I\\.asynch_inst)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH padio combout (979:979:979) (979:979:979))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_pll")
+ (INSTANCE \\inst1\|altpll_component\|pll\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT inclk[0] (2013:2013:2013) (2005:2005:2005))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_clkctrl")
+ (INSTANCE \\inst1\|altpll_component\|_clk0\~clkctrl_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT inclk[0] (1091:1091:1091) (1087:1087:1087))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_ena_reg")
+ (INSTANCE \\inst1\|altpll_component\|_clk0\~clkctrl_I\\.extena0_reg)
+ (DELAY
+ (ABSOLUTE
+ (PORT d (254:254:254) (254:254:254))
+ (PORT clk (0:0:0) (0:0:0))
+ (IOPATH (posedge clk) q (218:218:218) (218:218:218))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP d (posedge clk) (50:50:50))
+ (HOLD d (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Add0\~100_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (741:741:741) (648:648:648))
+ (IOPATH dataa combout (438:438:438) (438:438:438))
+ (IOPATH dataa cout (414:414:414) (414:414:414))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ (IOPATH cin combout (410:410:410) (410:410:410))
+ (IOPATH cin cout (71:71:71) (71:71:71))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Add0\~102_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (713:713:713) (622:622:622))
+ (IOPATH datab combout (420:420:420) (420:420:420))
+ (IOPATH datab cout (393:393:393) (393:393:393))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ (IOPATH cin combout (410:410:410) (410:410:410))
+ (IOPATH cin cout (71:71:71) (71:71:71))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Add0\~104_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (735:735:735) (638:638:638))
+ (IOPATH dataa combout (438:438:438) (438:438:438))
+ (IOPATH dataa cout (414:414:414) (414:414:414))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ (IOPATH cin combout (410:410:410) (410:410:410))
+ (IOPATH cin cout (71:71:71) (71:71:71))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Add0\~106_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (736:736:736) (633:633:633))
+ (IOPATH dataa combout (438:438:438) (438:438:438))
+ (IOPATH dataa cout (414:414:414) (414:414:414))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ (IOPATH cin combout (410:410:410) (410:410:410))
+ (IOPATH cin cout (71:71:71) (71:71:71))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Add0\~108_I\\)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH cin combout (410:410:410) (410:410:410))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Mod0\|auto_generated\|divider\|divider\|add_sub_6_result_int\[3\]\~18_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (277:277:277) (240:240:240))
+ (IOPATH dataa combout (413:413:413) (413:413:413))
+ (IOPATH dataa cout (414:414:414) (414:414:414))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ (IOPATH cin combout (410:410:410) (410:410:410))
+ (IOPATH cin cout (71:71:71) (71:71:71))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Mod0\|auto_generated\|divider\|divider\|add_sub_6_result_int\[7\]\~26_I\\)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH cin combout (410:410:410) (410:410:410))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Mod0\|auto_generated\|divider\|divider\|StageOut\[48\]\~31_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (466:466:466) (440:440:440))
+ (PORT datad (522:522:522) (473:473:473))
+ (IOPATH dataa combout (438:438:438) (438:438:438))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Mod0\|auto_generated\|divider\|divider\|StageOut\[48\]\~23_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (464:464:464) (439:439:439))
+ (PORT datad (521:521:521) (474:474:474))
+ (IOPATH dataa combout (413:413:413) (413:413:413))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Mod0\|auto_generated\|divider\|divider\|add_sub_7_result_int\[1\]\~18_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (247:247:247) (210:210:210))
+ (PORT datad (239:239:239) (206:206:206))
+ (IOPATH datac combout (242:242:242) (242:242:242))
+ (IOPATH datad combout (149:149:149) (149:149:149))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Add0\~96_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (505:505:505) (433:433:433))
+ (PORT datab (323:323:323) (292:292:292))
+ (IOPATH dataa combout (437:437:437) (437:437:437))
+ (IOPATH dataa cout (504:504:504) (504:504:504))
+ (IOPATH datab combout (420:420:420) (420:420:420))
+ (IOPATH datab cout (485:485:485) (485:485:485))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Mod0\|auto_generated\|divider\|divider\|StageOut\[54\]\~17_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (441:441:441) (376:376:376))
+ (PORT datad (522:522:522) (475:475:475))
+ (IOPATH datab combout (393:393:393) (393:393:393))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Mod0\|auto_generated\|divider\|divider\|StageOut\[53\]\~18_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (443:443:443) (379:379:379))
+ (PORT datad (515:515:515) (469:469:469))
+ (IOPATH datab combout (393:393:393) (393:393:393))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Mod0\|auto_generated\|divider\|divider\|StageOut\[52\]\~19_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (434:434:434) (367:367:367))
+ (PORT datad (523:523:523) (473:473:473))
+ (IOPATH datab combout (393:393:393) (393:393:393))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Mod0\|auto_generated\|divider\|divider\|add_sub_6_result_int\[2\]\~16_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (259:259:259) (228:228:228))
+ (IOPATH datab combout (420:420:420) (420:420:420))
+ (IOPATH datab cout (393:393:393) (393:393:393))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Mod0\|auto_generated\|divider\|divider\|StageOut\[50\]\~29_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (667:667:667) (572:572:572))
+ (PORT datad (705:705:705) (626:626:626))
+ (IOPATH datac combout (275:275:275) (275:275:275))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Mod0\|auto_generated\|divider\|divider\|add_sub_7_result_int\[2\]\~20_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (263:263:263) (223:223:223))
+ (PORT datab (244:244:244) (211:211:211))
+ (IOPATH dataa combout (438:438:438) (438:438:438))
+ (IOPATH dataa cout (504:504:504) (504:504:504))
+ (IOPATH datab combout (420:420:420) (420:420:420))
+ (IOPATH datab cout (485:485:485) (485:485:485))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Mod0\|auto_generated\|divider\|divider\|add_sub_7_result_int\[4\]\~24_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (451:451:451) (377:377:377))
+ (PORT datab (263:263:263) (232:232:232))
+ (IOPATH dataa combout (438:438:438) (438:438:438))
+ (IOPATH dataa cout (414:414:414) (414:414:414))
+ (IOPATH datab combout (420:420:420) (420:420:420))
+ (IOPATH datab cout (393:393:393) (393:393:393))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ (IOPATH cin combout (410:410:410) (410:410:410))
+ (IOPATH cin cout (71:71:71) (71:71:71))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Mod0\|auto_generated\|divider\|divider\|add_sub_7_result_int\[5\]\~26_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (410:410:410) (376:376:376))
+ (PORT datab (441:441:441) (378:378:378))
+ (IOPATH dataa combout (438:438:438) (438:438:438))
+ (IOPATH dataa cout (414:414:414) (414:414:414))
+ (IOPATH datab combout (420:420:420) (420:420:420))
+ (IOPATH datab cout (393:393:393) (393:393:393))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ (IOPATH cin combout (410:410:410) (410:410:410))
+ (IOPATH cin cout (71:71:71) (71:71:71))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Mod0\|auto_generated\|divider\|divider\|add_sub_7_result_int\[7\]\~31_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (429:429:429) (399:399:399))
+ (PORT datab (427:427:427) (361:361:361))
+ (IOPATH dataa cout (414:414:414) (414:414:414))
+ (IOPATH datab cout (393:393:393) (393:393:393))
+ (IOPATH cin cout (71:71:71) (71:71:71))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Mod0\|auto_generated\|divider\|divider\|add_sub_7_result_int\[8\]\~32_I\\)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH cin combout (410:410:410) (410:410:410))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Mod0\|auto_generated\|divider\|divider\|StageOut\[57\]\~636_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (431:431:431) (369:369:369))
+ (PORT datac (255:255:255) (219:219:219))
+ (PORT datad (682:682:682) (595:595:595))
+ (IOPATH datab combout (420:420:420) (420:420:420))
+ (IOPATH datac combout (271:271:271) (271:271:271))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_asynch_io")
+ (INSTANCE \\RESET\~I\\.asynch_inst)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH padio combout (850:850:850) (850:850:850))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_ff")
+ (INSTANCE \\inst\|counter\[1\]\~I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT clk (1555:1555:1555) (1559:1559:1559))
+ (PORT datain (84:84:84) (84:84:84))
+ (PORT sclr (6914:6914:6914) (7001:7001:7001))
+ (IOPATH (posedge clk) regout (250:250:250) (250:250:250))
+ )
+ )
+ (TIMINGCHECK
+ (HOLD datain (posedge clk) (266:266:266))
+ (HOLD sclr (posedge clk) (266:266:266))
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Add0\~98_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (316:316:316) (283:283:283))
+ (IOPATH datab combout (420:420:420) (420:420:420))
+ (IOPATH datab cout (393:393:393) (393:393:393))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ (IOPATH cin combout (410:410:410) (410:410:410))
+ (IOPATH cin cout (71:71:71) (71:71:71))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Mod0\|auto_generated\|divider\|divider\|StageOut\[49\]\~30_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (670:670:670) (576:576:576))
+ (PORT datad (706:706:706) (625:625:625))
+ (IOPATH datab combout (420:420:420) (420:420:420))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Mod0\|auto_generated\|divider\|divider\|StageOut\[58\]\~639_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (276:276:276) (238:238:238))
+ (PORT datac (703:703:703) (658:658:658))
+ (PORT datad (680:680:680) (592:592:592))
+ (IOPATH dataa combout (438:438:438) (438:438:438))
+ (IOPATH datac combout (275:275:275) (275:275:275))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_ff")
+ (INSTANCE \\inst\|counter\[2\]\~I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT clk (1555:1555:1555) (1559:1559:1559))
+ (PORT datain (84:84:84) (84:84:84))
+ (PORT sclr (6914:6914:6914) (7001:7001:7001))
+ (IOPATH (posedge clk) regout (250:250:250) (250:250:250))
+ )
+ )
+ (TIMINGCHECK
+ (HOLD datain (posedge clk) (266:266:266))
+ (HOLD sclr (posedge clk) (266:266:266))
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Mod0\|auto_generated\|divider\|divider\|StageOut\[51\]\~28_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (661:661:661) (567:567:567))
+ (PORT datad (706:706:706) (625:625:625))
+ (IOPATH datac combout (275:275:275) (275:275:275))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Mod0\|auto_generated\|divider\|divider\|StageOut\[51\]\~20_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (442:442:442) (375:375:375))
+ (PORT datad (515:515:515) (470:470:470))
+ (IOPATH datac combout (271:271:271) (271:271:271))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Mod0\|auto_generated\|divider\|divider\|StageOut\[60\]\~642_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (469:469:469) (404:404:404))
+ (PORT datab (256:256:256) (226:226:226))
+ (PORT datac (908:908:908) (799:799:799))
+ (PORT datad (274:274:274) (247:247:247))
+ (IOPATH dataa combout (437:437:437) (437:437:437))
+ (IOPATH datab combout (420:420:420) (420:420:420))
+ (IOPATH datac combout (271:271:271) (271:271:271))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_ff")
+ (INSTANCE \\inst\|counter\[4\]\~I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT clk (1557:1557:1557) (1559:1559:1559))
+ (PORT datain (84:84:84) (84:84:84))
+ (PORT sclr (6919:6919:6919) (7003:7003:7003))
+ (IOPATH (posedge clk) regout (250:250:250) (250:250:250))
+ )
+ )
+ (TIMINGCHECK
+ (HOLD datain (posedge clk) (266:266:266))
+ (HOLD sclr (posedge clk) (266:266:266))
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Mod0\|auto_generated\|divider\|divider\|StageOut\[61\]\~640_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (463:463:463) (399:399:399))
+ (PORT datab (444:444:444) (381:381:381))
+ (PORT datac (253:253:253) (219:219:219))
+ (PORT datad (273:273:273) (246:246:246))
+ (IOPATH dataa combout (438:438:438) (438:438:438))
+ (IOPATH datab combout (419:419:419) (419:419:419))
+ (IOPATH datac combout (275:275:275) (275:275:275))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_ff")
+ (INSTANCE \\inst\|counter\[5\]\~I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT clk (1557:1557:1557) (1559:1559:1559))
+ (PORT datain (84:84:84) (84:84:84))
+ (PORT sclr (6919:6919:6919) (7003:7003:7003))
+ (IOPATH (posedge clk) regout (250:250:250) (250:250:250))
+ )
+ )
+ (TIMINGCHECK
+ (HOLD datain (posedge clk) (266:266:266))
+ (HOLD sclr (posedge clk) (266:266:266))
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Mod0\|auto_generated\|divider\|divider\|add_sub_7_result_int\[0\]\~34_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT datad (507:507:507) (450:450:450))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Mod0\|auto_generated\|divider\|divider\|StageOut\[56\]\~637_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (427:427:427) (362:362:362))
+ (PORT datad (679:679:679) (592:592:592))
+ (IOPATH datab combout (420:420:420) (420:420:420))
+ (IOPATH datac combout (323:323:323) (323:323:323))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_ff")
+ (INSTANCE \\inst\|counter\[0\]\~I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT clk (1555:1555:1555) (1559:1559:1559))
+ (PORT datain (84:84:84) (84:84:84))
+ (PORT sclr (6914:6914:6914) (7001:7001:7001))
+ (IOPATH (posedge clk) regout (250:250:250) (250:250:250))
+ )
+ )
+ (TIMINGCHECK
+ (HOLD datain (posedge clk) (266:266:266))
+ (HOLD sclr (posedge clk) (266:266:266))
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Equal1\~58_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (748:748:748) (656:656:656))
+ (PORT datab (513:513:513) (455:455:455))
+ (PORT datac (493:493:493) (428:428:428))
+ (PORT datad (471:471:471) (450:450:450))
+ (IOPATH dataa combout (398:398:398) (398:398:398))
+ (IOPATH datab combout (415:415:415) (415:415:415))
+ (IOPATH datac combout (275:275:275) (275:275:275))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|Equal1\~59_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1013:1013:1013) (942:942:942))
+ (PORT datab (1390:1390:1390) (1216:1216:1216))
+ (PORT datac (735:735:735) (647:647:647))
+ (PORT datad (246:246:246) (217:217:217))
+ (IOPATH dataa combout (413:413:413) (413:413:413))
+ (IOPATH datab combout (371:371:371) (371:371:371))
+ (IOPATH datac combout (275:275:275) (275:275:275))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|knightlight\~1269_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (386:386:386) (355:355:355))
+ (PORT datac (364:364:364) (338:338:338))
+ (PORT datad (337:337:337) (311:311:311))
+ (IOPATH dataa combout (413:413:413) (413:413:413))
+ (IOPATH datac combout (271:271:271) (271:271:271))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|knightlight\~1270_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (257:257:257) (227:227:227))
+ (PORT datad (1718:1718:1718) (1734:1734:1734))
+ (IOPATH datab combout (419:419:419) (419:419:419))
+ (IOPATH datac combout (323:323:323) (323:323:323))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_ff")
+ (INSTANCE \\inst\|knightlight\[4\]\~I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT clk (1507:1507:1507) (1511:1511:1511))
+ (PORT datain (84:84:84) (84:84:84))
+ (PORT sclr (7184:7184:7184) (7134:7134:7134))
+ (IOPATH (posedge clk) regout (250:250:250) (250:250:250))
+ )
+ )
+ (TIMINGCHECK
+ (HOLD datain (posedge clk) (266:266:266))
+ (HOLD sclr (posedge clk) (266:266:266))
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|knightlight\~1271_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (2137:2137:2137) (2036:2036:2036))
+ (PORT datac (367:367:367) (341:341:341))
+ (PORT datad (335:335:335) (308:308:308))
+ (IOPATH datab combout (420:420:420) (420:420:420))
+ (IOPATH datac combout (271:271:271) (271:271:271))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|knightlight\~1272_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (1720:1720:1720) (1737:1737:1737))
+ (PORT datad (263:263:263) (235:235:235))
+ (IOPATH datab combout (393:393:393) (393:393:393))
+ (IOPATH datac combout (323:323:323) (323:323:323))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_ff")
+ (INSTANCE \\inst\|knightlight\[3\]\~I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT clk (1507:1507:1507) (1511:1511:1511))
+ (PORT datain (84:84:84) (84:84:84))
+ (PORT sclr (7184:7184:7184) (7134:7134:7134))
+ (IOPATH (posedge clk) regout (250:250:250) (250:250:250))
+ )
+ )
+ (TIMINGCHECK
+ (HOLD datain (posedge clk) (266:266:266))
+ (HOLD sclr (posedge clk) (266:266:266))
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|knightlight\~1273_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (338:338:338) (302:302:302))
+ (PORT datab (2407:2407:2407) (2342:2342:2342))
+ (PORT datac (2220:2220:2220) (2030:2030:2030))
+ (IOPATH dataa combout (438:438:438) (438:438:438))
+ (IOPATH datab combout (420:420:420) (420:420:420))
+ (IOPATH datac combout (275:275:275) (275:275:275))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|knightlight\~1274_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (287:287:287) (251:251:251))
+ (PORT datad (240:240:240) (210:210:210))
+ (IOPATH dataa combout (413:413:413) (413:413:413))
+ (IOPATH datac combout (323:323:323) (323:323:323))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_ff")
+ (INSTANCE \\inst\|knightlight\[2\]\~I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT clk (1554:1554:1554) (1557:1557:1557))
+ (PORT datain (84:84:84) (84:84:84))
+ (PORT sload (7065:7065:7065) (7149:7149:7149))
+ (IOPATH (posedge clk) regout (250:250:250) (250:250:250))
+ )
+ )
+ (TIMINGCHECK
+ (HOLD datain (posedge clk) (266:266:266))
+ (HOLD sload (posedge clk) (266:266:266))
+ (HOLD sdata (posedge clk) (266:266:266))
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|knightlight\~1277_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (283:283:283) (247:247:247))
+ (PORT datab (2206:2206:2206) (2010:2010:2010))
+ (PORT datad (514:514:514) (461:461:461))
+ (IOPATH dataa combout (410:410:410) (410:410:410))
+ (IOPATH datab combout (415:415:415) (415:415:415))
+ (IOPATH datac combout (323:323:323) (323:323:323))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_ff")
+ (INSTANCE \\inst\|knightlight\[0\]\~I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT clk (1554:1554:1554) (1557:1557:1557))
+ (PORT datain (84:84:84) (84:84:84))
+ (PORT sload (7065:7065:7065) (7149:7149:7149))
+ (IOPATH (posedge clk) regout (250:250:250) (250:250:250))
+ )
+ )
+ (TIMINGCHECK
+ (HOLD datain (posedge clk) (266:266:266))
+ (HOLD sload (posedge clk) (266:266:266))
+ (HOLD sdata (posedge clk) (266:266:266))
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|knightlight\~1275_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (310:310:310) (278:278:278))
+ (PORT datac (2223:2223:2223) (2032:2032:2032))
+ (PORT datad (319:319:319) (291:291:291))
+ (IOPATH datab combout (419:419:419) (419:419:419))
+ (IOPATH datac combout (275:275:275) (275:275:275))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|knightlight\~1276_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (284:284:284) (247:247:247))
+ (PORT datad (251:251:251) (221:221:221))
+ (IOPATH dataa combout (413:413:413) (413:413:413))
+ (IOPATH datac combout (323:323:323) (323:323:323))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_ff")
+ (INSTANCE \\inst\|knightlight\[1\]\~I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT clk (1554:1554:1554) (1557:1557:1557))
+ (PORT datain (84:84:84) (84:84:84))
+ (PORT sload (7065:7065:7065) (7149:7149:7149))
+ (IOPATH (posedge clk) regout (250:250:250) (250:250:250))
+ )
+ )
+ (TIMINGCHECK
+ (HOLD datain (posedge clk) (266:266:266))
+ (HOLD sload (posedge clk) (266:266:266))
+ (HOLD sdata (posedge clk) (266:266:266))
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|ledstate_next\~431_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (2138:2138:2138) (2036:2036:2036))
+ (PORT datac (335:335:335) (303:303:303))
+ (PORT datad (334:334:334) (308:308:308))
+ (IOPATH datab combout (419:419:419) (419:419:419))
+ (IOPATH datac combout (271:271:271) (271:271:271))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|ledstate_next\~432_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (376:376:376) (347:347:347))
+ (PORT datab (2137:2137:2137) (2036:2036:2036))
+ (PORT datac (1997:1997:1997) (1837:1837:1837))
+ (PORT datad (243:243:243) (213:213:213))
+ (IOPATH dataa combout (437:437:437) (437:437:437))
+ (IOPATH datab combout (419:419:419) (419:419:419))
+ (IOPATH datac combout (275:275:275) (275:275:275))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|ledstate_next\~433_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (321:321:321) (290:290:290))
+ (PORT datad (2402:2402:2402) (2339:2339:2339))
+ (IOPATH datab combout (420:420:420) (420:420:420))
+ (IOPATH datad combout (149:149:149) (149:149:149))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|ledstate_next\~436_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (269:269:269) (230:230:230))
+ (PORT datab (247:247:247) (214:214:214))
+ (PORT datad (1903:1903:1903) (1731:1731:1731))
+ (IOPATH dataa combout (438:438:438) (438:438:438))
+ (IOPATH datab combout (420:420:420) (420:420:420))
+ (IOPATH datac combout (323:323:323) (323:323:323))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_ff")
+ (INSTANCE \\inst\|ledstate\~I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT clk (1507:1507:1507) (1511:1511:1511))
+ (PORT datain (84:84:84) (84:84:84))
+ (PORT sclr (7184:7184:7184) (7134:7134:7134))
+ (IOPATH (posedge clk) regout (250:250:250) (250:250:250))
+ )
+ )
+ (TIMINGCHECK
+ (HOLD datain (posedge clk) (266:266:266))
+ (HOLD sclr (posedge clk) (266:266:266))
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|knightlight\~1267_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (329:329:329) (299:299:299))
+ (PORT datac (375:375:375) (347:347:347))
+ (PORT datad (336:336:336) (310:310:310))
+ (IOPATH datab combout (419:419:419) (419:419:419))
+ (IOPATH datac combout (275:275:275) (275:275:275))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|knightlight\~1268_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (1719:1719:1719) (1736:1736:1736))
+ (PORT datad (248:248:248) (219:219:219))
+ (IOPATH datab combout (393:393:393) (393:393:393))
+ (IOPATH datac combout (323:323:323) (323:323:323))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_ff")
+ (INSTANCE \\inst\|knightlight\[5\]\~I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT clk (1507:1507:1507) (1511:1511:1511))
+ (PORT datain (84:84:84) (84:84:84))
+ (PORT sclr (7184:7184:7184) (7134:7134:7134))
+ (IOPATH (posedge clk) regout (250:250:250) (250:250:250))
+ )
+ )
+ (TIMINGCHECK
+ (HOLD datain (posedge clk) (266:266:266))
+ (HOLD sclr (posedge clk) (266:266:266))
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|knightlight\~1265_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (341:341:341) (313:313:313))
+ (PORT datac (373:373:373) (346:346:346))
+ (PORT datad (485:485:485) (473:473:473))
+ (IOPATH datab combout (420:420:420) (420:420:420))
+ (IOPATH datac combout (271:271:271) (271:271:271))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|knightlight\~1266_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (1722:1722:1722) (1739:1739:1739))
+ (PORT datad (247:247:247) (217:217:217))
+ (IOPATH datab combout (393:393:393) (393:393:393))
+ (IOPATH datac combout (323:323:323) (323:323:323))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_ff")
+ (INSTANCE \\inst\|knightlight\[6\]\~I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT clk (1507:1507:1507) (1511:1511:1511))
+ (PORT datain (84:84:84) (84:84:84))
+ (PORT sclr (7184:7184:7184) (7134:7134:7134))
+ (IOPATH (posedge clk) regout (250:250:250) (250:250:250))
+ )
+ )
+ (TIMINGCHECK
+ (HOLD datain (posedge clk) (266:266:266))
+ (HOLD sclr (posedge clk) (266:266:266))
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_comb")
+ (INSTANCE \\inst\|knightlight\~1264_I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (386:386:386) (354:354:354))
+ (PORT datab (330:330:330) (301:301:301))
+ (PORT datad (1719:1719:1719) (1735:1735:1735))
+ (IOPATH dataa combout (438:438:438) (438:438:438))
+ (IOPATH datab combout (419:419:419) (419:419:419))
+ (IOPATH datac combout (323:323:323) (323:323:323))
+ (IOPATH datad combout (150:150:150) (150:150:150))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_lcell_ff")
+ (INSTANCE \\inst\|knightlight\[7\]\~I\\)
+ (DELAY
+ (ABSOLUTE
+ (PORT clk (1507:1507:1507) (1511:1511:1511))
+ (PORT datain (84:84:84) (84:84:84))
+ (PORT sclr (7184:7184:7184) (7134:7134:7134))
+ (IOPATH (posedge clk) regout (250:250:250) (250:250:250))
+ )
+ )
+ (TIMINGCHECK
+ (HOLD datain (posedge clk) (266:266:266))
+ (HOLD sclr (posedge clk) (266:266:266))
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_asynch_io")
+ (INSTANCE \\LEDS\[7\]\~I\\.asynch_inst)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (4263:4263:4263) (4176:4176:4176))
+ (IOPATH datain padio (2632:2632:2632) (2632:2632:2632))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_asynch_io")
+ (INSTANCE \\LEDS\[6\]\~I\\.asynch_inst)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3010:3010:3010) (2978:2978:2978))
+ (IOPATH datain padio (2642:2642:2642) (2642:2642:2642))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_asynch_io")
+ (INSTANCE \\LEDS\[5\]\~I\\.asynch_inst)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3047:3047:3047) (3072:3072:3072))
+ (IOPATH datain padio (2632:2632:2632) (2632:2632:2632))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_asynch_io")
+ (INSTANCE \\LEDS\[4\]\~I\\.asynch_inst)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (4383:4383:4383) (4424:4424:4424))
+ (IOPATH datain padio (2642:2642:2642) (2642:2642:2642))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_asynch_io")
+ (INSTANCE \\LEDS\[3\]\~I\\.asynch_inst)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3538:3538:3538) (3534:3534:3534))
+ (IOPATH datain padio (2642:2642:2642) (2642:2642:2642))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_asynch_io")
+ (INSTANCE \\LEDS\[2\]\~I\\.asynch_inst)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (6134:6134:6134) (6236:6236:6236))
+ (IOPATH datain padio (2632:2632:2632) (2632:2632:2632))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_asynch_io")
+ (INSTANCE \\LEDS\[1\]\~I\\.asynch_inst)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (5949:5949:5949) (6019:6019:6019))
+ (IOPATH datain padio (2632:2632:2632) (2632:2632:2632))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "cycloneii_asynch_io")
+ (INSTANCE \\LEDS\[0\]\~I\\.asynch_inst)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (6268:6268:6268) (6365:6365:6365))
+ (IOPATH datain padio (2622:2622:2622) (2622:2622:2622))
+ )
+ )
+ )
+)
--- /dev/null
+configuration conf of demo_tb is
+ for behav
+ for uut : demo_top
+ use entity work.demo(behav);
+ end for;
+ end for;
+end conf;
\ No newline at end of file
--- /dev/null
+configuration conf of demo_tb is
+ for behav
+ for uut : demo_top
+ use entity work.demo_top(structure);
+ end for;
+ end for;
+end conf;
\ No newline at end of file
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use work.demo_pkg.all;
+
+entity demo_tb is
+
+end demo_tb;
+
+architecture behav of demo_tb is
+
+ component demo_top is
+
+ port (
+ clk : in std_logic;
+ reset : in std_logic;
+ leds : out std_logic_vector(7 downto 0));
+
+ end component demo_top;
+
+
+ signal clk : std_logic;
+ signal reset : std_logic;
+ signal leds : std_logic_vector(7 downto 0);
+
+ constant QUARTZ_PERIOD : time := 40 ns;
+
+begin -- behav
+
+ uut: demo_top
+ port map (
+ clk => clk,
+ reset => reset,
+ leds => leds);
+
+ process
+ begin -- process
+ clk <= '0';
+ wait for QUARTZ_PERIOD / 2;
+ clk <= '1';
+ wait for QUARTZ_PERIOD / 2;
+ end process;
+
+ process
+ begin -- process
+ reset <= RESETVALUE;
+ wait for 10 * QUARTZ_PERIOD;
+ reset <= not RESETVALUE;
+
+ wait; -- infinite wait
+
+ -- wait for 50 us;
+ -- assert false report "Simulation done" severity failure;
+ end process;
+
+end behav;
+
--- /dev/null
+if {[file exists behav_work]} {
+ vdel -all -lib behav_work
+}
+
+# create work library directory
+vlib behav_work
+
+# map directory to library name "work"
+vmap work behav_work
+
+#compile vhdl files
+vcom -work work ../../src/demo_pkg.vhd
+vcom -work work -cover bs ../../src/demo.vhd
+
+# compile testbench
+vcom -work work demo_tb.vhd
+
+# compile configuration file
+vcom -work work config_behav.vhd
+
+# start simulation
+vsim -coverage work.conf
+
+view -undock wave
+
+# add signals to waveform
+# add all testbench signals
+add wave *
+
+# add internal signals of unit under test
+add wave -divider DEMO
+add wave uut/counter
+add wave uut/ledstate
+
+# auto-run simulation
+run 50 us
+wave zoomfull
--- /dev/null
+# compile technology libraries
+# if you're using Quartus Web Edition combined with ModelSim-Altera you have
+# to omit this step. ModelSim-Altera uses its own precompiled Altera technology
+# libraries.
+
+set SIM_LIBRARY_PATH /opt/altera8.1/quartus/eda/sim_lib
+
+if {[file exists cyclonelib]} {
+ vdel -all -lib cyclonelib
+}
+
+vlib cyclonelib
+vmap cycloneii cyclonelib
+
+vcom -work cycloneii $SIM_LIBRARY_PATH/cycloneii_atoms.vhd
+vcom -work cycloneii $SIM_LIBRARY_PATH/cycloneii_components.vhd
+
+# end compile technology libraries
+
+
+# create work library directory
+vlib post_work
+
+# map directory to library name "work"
+vmap work post_work
+
+# compile gate-level netlist
+set NETLIST_PATH ../../quartus/simulation/modelsim
+
+vcom -work work "$NETLIST_PATH/demo.vho"
+
+# compile testbench
+vcom -work work {../../src/demo_pkg.vhd}
+vcom -work work demo_tb.vhd
+
+# compile configuration file
+vcom -work work config_post.vhd
+
+# start simulation
+vsim -t 1ps +transport_int_delays +transport_path_delays -sdftyp /uut=$NETLIST_PATH/demo_vhd.sdo -L cycloneii -L work work.conf
+
+view -undock wave
+
+# add signals to waveform
+# add all testbench signals
+add wave *
+
+# auto-run simulation
+run 50 us
+wave zoomfull
+
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.demo_pkg.all;
+
+entity demo is
+
+ port (
+ clk : in std_logic;
+ reset : in std_logic;
+ leds : out std_logic_vector(7 downto 0));
+
+end demo;
+
+
+architecture behav of demo is
+
+ function GetShiftDelay return time is
+ begin
+ if SIMULATION then
+ return 1 us;
+ else
+ return 100 ms;
+ end if;
+ end;
+
+ signal knightlight, knightlight_next : std_logic_vector (7 downto 0);
+
+ type LEDSTATE_T is (LEFT_S, RIGHT_S);
+ signal ledstate, ledstate_next : LEDSTATE_T;
+
+ subtype counter_t is integer range 0 to (GetShiftDelay / PERIOD);
+ signal counter : counter_t;
+
+ signal syncreset : std_logic;
+
+begin -- behav
+
+ process(clk)
+ begin
+ if rising_edge(clk) then
+ syncreset <= reset;
+ end if;
+ end process;
+
+
+ sync: process(clk, reset)
+ begin
+ if rising_edge(clk) then
+ if syncreset = RESETVALUE then
+ knightlight <= (others => LED_OFF);
+ knightlight(2 downto 0) <= (others => LED_ON);
+ ledstate <= LEFT_S;
+ else
+ knightlight <= knightlight_next;
+ ledstate <= ledstate_next;
+ end if;
+ end if;
+ end process;
+
+ next_state_logic: process(ledstate, knightlight, counter)
+ variable knightlight_tmp : bit_vector (7 downto 0);
+ begin -- process
+ -- default assignments
+ ledstate_next <= ledstate;
+ knightlight_tmp := TO_BITVECTOR(knightlight);
+
+ case ledstate is
+ when LEFT_S =>
+ if counter = counter_t'high - 1 then
+ knightlight_tmp := knightlight_tmp sll 1;
+ end if;
+ if knightlight_tmp = "11100000" then
+ ledstate_next <= RIGHT_S;
+ end if;
+ when RIGHT_S =>
+ if counter = counter_t'high - 1 then
+ knightlight_tmp := knightlight_tmp srl 1;
+ end if;
+ if knightlight_tmp = "00000111" then
+ ledstate_next <= LEFT_S;
+ end if;
+ when others => null;
+ end case;
+
+ knightlight_next <= TO_STDLOGICVECTOR(knightlight_tmp);
+ end process;
+
+ counterProcess: process(clk, reset)
+ begin -- process
+ if rising_edge(clk) then
+ if syncreset = RESETVALUE then
+ counter <= 0;
+ elsif counter < counter_t'high then
+ counter <= counter + 1;
+ else
+ counter <= 0;
+ end if;
+ end if;
+ end process;
+
+ leds <= not knightlight;
+
+end behav;
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+
+package demo_pkg is
+
+ constant SIMULATION : boolean := FALSE;
+
+ constant PERIOD : time := 10 ns;
+ constant RESETVALUE : std_logic := '0';
+ constant LED_ON : std_logic := '1';
+ constant LED_OFF : std_logic := '0';
+
+end demo_pkg;
--- /dev/null
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+*/
+//#pragma file_not_in_maxplusii_format
+(header "graphic" (version "1.3"))
+(pin
+ (input)
+ (rect 416 296 584 312)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "RESET" (rect 5 0 40 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+ (annotation_block (location)(rect 368 312 416 328))
+)
+(pin
+ (input)
+ (rect 136 56 304 72)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "CLK" (rect 5 0 26 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+ (annotation_block (location)(rect 168 176 216 192))
+)
+(pin
+ (output)
+ (rect 896 144 1072 160)
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+ (text "LEDS[7..0]" (rect 90 0 144 12)(font "Arial" ))
+ (pt 0 8)
+ (drawing
+ (line (pt 0 8)(pt 52 8)(line_width 1))
+ (line (pt 52 4)(pt 78 4)(line_width 1))
+ (line (pt 52 12)(pt 78 12)(line_width 1))
+ (line (pt 52 12)(pt 52 4)(line_width 1))
+ (line (pt 78 4)(pt 82 8)(line_width 1))
+ (line (pt 82 8)(pt 78 12)(line_width 1))
+ (line (pt 78 12)(pt 82 8)(line_width 1))
+ )
+ (annotation_block (location)(rect 1072 160 1128 272))
+)
+(symbol
+ (rect 696 120 856 216)
+ (text "demo" (rect 5 0 32 12)(font "Arial" ))
+ (text "inst" (rect 8 80 25 92)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "clk" (rect 0 0 14 12)(font "Arial" ))
+ (text "clk" (rect 21 27 35 39)(font "Arial" ))
+ (line (pt 0 32)(pt 16 32)(line_width 1))
+ )
+ (port
+ (pt 0 48)
+ (input)
+ (text "reset" (rect 0 0 24 12)(font "Arial" ))
+ (text "reset" (rect 21 43 45 55)(font "Arial" ))
+ (line (pt 0 48)(pt 16 48)(line_width 1))
+ )
+ (port
+ (pt 160 32)
+ (output)
+ (text "leds[7..0]" (rect 0 0 46 12)(font "Arial" ))
+ (text "leds[7..0]" (rect 69 27 115 39)(font "Arial" ))
+ (line (pt 160 32)(pt 144 32)(line_width 3))
+ )
+ (drawing
+ (rectangle (rect 16 16 144 80)(line_width 1))
+ )
+)
+(symbol
+ (rect 352 56 592 216)
+ (text "pll" (rect 114 0 129 16)(font "Arial" (font_size 10)))
+ (text "inst1" (rect 8 144 31 156)(font "Arial" ))
+ (port
+ (pt 0 64)
+ (input)
+ (text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+ (text "inclk0" (rect 4 51 35 65)(font "Arial" (font_size 8)))
+ (line (pt 0 64)(pt 40 64)(line_width 1))
+ )
+ (port
+ (pt 240 64)
+ (output)
+ (text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+ (text "c0" (rect 225 51 239 65)(font "Arial" (font_size 8)))
+ (line (pt 240 64)(pt 208 64)(line_width 1))
+ )
+ (drawing
+ (text "Cyclone II" (rect 183 145 234 157)(font "Arial" ))
+ (text "inclk0 frequency: 25.000 MHz" (rect 50 59 197 71)(font "Arial" ))
+ (text "Operation Mode: Normal" (rect 50 73 169 85)(font "Arial" ))
+ (text "Clk " (rect 51 96 71 108)(font "Arial" ))
+ (text "Ratio" (rect 73 96 98 108)(font "Arial" ))
+ (text "Ph (dg)" (rect 100 96 135 108)(font "Arial" ))
+ (text "DC (%)" (rect 135 96 171 108)(font "Arial" ))
+ (text "c0" (rect 54 111 65 123)(font "Arial" ))
+ (text "4/1" (rect 78 111 93 123)(font "Arial" ))
+ (text "0.00" (rect 106 111 127 123)(font "Arial" ))
+ (text "50.00" (rect 139 111 166 123)(font "Arial" ))
+ (line (pt 0 0)(pt 241 0)(line_width 1))
+ (line (pt 241 0)(pt 241 161)(line_width 1))
+ (line (pt 0 161)(pt 241 161)(line_width 1))
+ (line (pt 0 0)(pt 0 161)(line_width 1))
+ (line (pt 48 94)(pt 168 94)(line_width 1))
+ (line (pt 48 108)(pt 168 108)(line_width 1))
+ (line (pt 48 123)(pt 168 123)(line_width 1))
+ (line (pt 48 94)(pt 48 123)(line_width 1))
+ (line (pt 70 94)(pt 70 123)(line_width 3))
+ (line (pt 97 94)(pt 97 123)(line_width 3))
+ (line (pt 132 94)(pt 132 123)(line_width 3))
+ (line (pt 167 94)(pt 167 123)(line_width 1))
+ (line (pt 40 48)(pt 208 48)(line_width 1))
+ (line (pt 208 48)(pt 208 144)(line_width 1))
+ (line (pt 40 144)(pt 208 144)(line_width 1))
+ (line (pt 40 48)(pt 40 144)(line_width 1))
+ )
+)
+(connector
+ (pt 304 64)
+ (pt 312 64)
+)
+(connector
+ (pt 312 64)
+ (pt 312 120)
+)
+(connector
+ (pt 312 120)
+ (pt 352 120)
+)
+(connector
+ (pt 592 120)
+ (pt 640 120)
+)
+(connector
+ (pt 640 120)
+ (pt 640 152)
+)
+(connector
+ (pt 640 152)
+ (pt 696 152)
+)
+(connector
+ (pt 856 152)
+ (pt 896 152)
+ (bus)
+)
+(connector
+ (pt 632 168)
+ (pt 696 168)
+)
+(connector
+ (pt 632 304)
+ (pt 584 304)
+)
+(connector
+ (pt 632 168)
+ (pt 632 304)
+)
--- /dev/null
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+ (rect 0 0 240 160)
+ (text "pll" (rect 114 0 129 16)(font "Arial" (font_size 10)))
+ (text "inst" (rect 8 144 25 156)(font "Arial" ))
+ (port
+ (pt 0 64)
+ (input)
+ (text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+ (text "inclk0" (rect 4 51 31 64)(font "Arial" (font_size 8)))
+ (line (pt 0 64)(pt 40 64)(line_width 1))
+ )
+ (port
+ (pt 240 64)
+ (output)
+ (text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+ (text "c0" (rect 225 51 236 64)(font "Arial" (font_size 8)))
+ (line (pt 240 64)(pt 208 64)(line_width 1))
+ )
+ (drawing
+ (text "Cyclone II" (rect 183 145 227 157)(font "Arial" ))
+ (text "inclk0 frequency: 25.000 MHz" (rect 50 59 175 71)(font "Arial" ))
+ (text "Operation Mode: Normal" (rect 50 73 151 85)(font "Arial" ))
+ (text "Clk " (rect 51 96 68 108)(font "Arial" ))
+ (text "Ratio" (rect 73 96 95 108)(font "Arial" ))
+ (text "Ph (dg)" (rect 100 96 130 108)(font "Arial" ))
+ (text "DC (%)" (rect 135 96 166 108)(font "Arial" ))
+ (text "c0" (rect 54 111 64 123)(font "Arial" ))
+ (text "4/1" (rect 78 111 91 123)(font "Arial" ))
+ (text "0.00" (rect 106 111 124 123)(font "Arial" ))
+ (text "50.00" (rect 139 111 162 123)(font "Arial" ))
+ (line (pt 0 0)(pt 241 0)(line_width 1))
+ (line (pt 241 0)(pt 241 161)(line_width 1))
+ (line (pt 0 161)(pt 241 161)(line_width 1))
+ (line (pt 0 0)(pt 0 161)(line_width 1))
+ (line (pt 48 94)(pt 168 94)(line_width 1))
+ (line (pt 48 108)(pt 168 108)(line_width 1))
+ (line (pt 48 123)(pt 168 123)(line_width 1))
+ (line (pt 48 94)(pt 48 123)(line_width 1))
+ (line (pt 70 94)(pt 70 123)(line_width 3))
+ (line (pt 97 94)(pt 97 123)(line_width 3))
+ (line (pt 132 94)(pt 132 123)(line_width 3))
+ (line (pt 167 94)(pt 167 123)(line_width 1))
+ (line (pt 40 48)(pt 208 48)(line_width 1))
+ (line (pt 208 48)(pt 208 144)(line_width 1))
+ (line (pt 40 144)(pt 208 144)(line_width 1))
+ (line (pt 40 48)(pt 40 144)(line_width 1))
+ )
+)
--- /dev/null
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions
+--and other software and tools, and its AMPP partner logic
+--functions, and any output files from any of the foregoing
+--(including device programming or simulation files), and any
+--associated documentation or information are expressly subject
+--to the terms and conditions of the Altera Program License
+--Subscription Agreement, Altera MegaCore Function License
+--Agreement, or other applicable license agreement, including,
+--without limitation, that your use is for the sole purpose of
+--programming logic devices manufactured by Altera and sold by
+--Altera or its authorized distributors. Please refer to the
+--applicable agreement for further details.
+
+
+component pll
+ PORT
+ (
+ inclk0 : IN STD_LOGIC := '0';
+ c0 : OUT STD_LOGIC
+ );
+end component;
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone II" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock" />
+<pin name="c0" direction="output" scope="external" source="clock" />
+
+</global>
+</pinplan>
--- /dev/null
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
--- /dev/null
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll
+
+-- ============================================================
+-- File Name: pll.vhd
+-- Megafunction Name(s):
+-- altpll
+--
+-- Simulation Library Files(s):
+-- altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Full Version
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions
+--and other software and tools, and its AMPP partner logic
+--functions, and any output files from any of the foregoing
+--(including device programming or simulation files), and any
+--associated documentation or information are expressly subject
+--to the terms and conditions of the Altera Program License
+--Subscription Agreement, Altera MegaCore Function License
+--Agreement, or other applicable license agreement, including,
+--without limitation, that your use is for the sole purpose of
+--programming logic devices manufactured by Altera and sold by
+--Altera or its authorized distributors. Please refer to the
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll IS
+ PORT
+ (
+ inclk0 : IN STD_LOGIC := '0';
+ c0 : OUT STD_LOGIC
+ );
+END pll;
+
+
+ARCHITECTURE SYN OF pll IS
+
+ SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
+ SIGNAL sub_wire1 : STD_LOGIC ;
+ SIGNAL sub_wire2 : STD_LOGIC ;
+ SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0);
+ SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0);
+ SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+ COMPONENT altpll
+ GENERIC (
+ clk0_divide_by : NATURAL;
+ clk0_duty_cycle : NATURAL;
+ clk0_multiply_by : NATURAL;
+ clk0_phase_shift : STRING;
+ compensate_clock : STRING;
+ inclk0_input_frequency : NATURAL;
+ intended_device_family : STRING;
+ lpm_hint : STRING;
+ lpm_type : STRING;
+ operation_mode : STRING;
+ port_activeclock : STRING;
+ port_areset : STRING;
+ port_clkbad0 : STRING;
+ port_clkbad1 : STRING;
+ port_clkloss : STRING;
+ port_clkswitch : STRING;
+ port_configupdate : STRING;
+ port_fbin : STRING;
+ port_inclk0 : STRING;
+ port_inclk1 : STRING;
+ port_locked : STRING;
+ port_pfdena : STRING;
+ port_phasecounterselect : STRING;
+ port_phasedone : STRING;
+ port_phasestep : STRING;
+ port_phaseupdown : STRING;
+ port_pllena : STRING;
+ port_scanaclr : STRING;
+ port_scanclk : STRING;
+ port_scanclkena : STRING;
+ port_scandata : STRING;
+ port_scandataout : STRING;
+ port_scandone : STRING;
+ port_scanread : STRING;
+ port_scanwrite : STRING;
+ port_clk0 : STRING;
+ port_clk1 : STRING;
+ port_clk2 : STRING;
+ port_clk3 : STRING;
+ port_clk4 : STRING;
+ port_clk5 : STRING;
+ port_clkena0 : STRING;
+ port_clkena1 : STRING;
+ port_clkena2 : STRING;
+ port_clkena3 : STRING;
+ port_clkena4 : STRING;
+ port_clkena5 : STRING;
+ port_extclk0 : STRING;
+ port_extclk1 : STRING;
+ port_extclk2 : STRING;
+ port_extclk3 : STRING
+ );
+ PORT (
+ inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+ clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
+ );
+ END COMPONENT;
+
+BEGIN
+ sub_wire4_bv(0 DOWNTO 0) <= "0";
+ sub_wire4 <= To_stdlogicvector(sub_wire4_bv);
+ sub_wire1 <= sub_wire0(0);
+ c0 <= sub_wire1;
+ sub_wire2 <= inclk0;
+ sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2;
+
+ altpll_component : altpll
+ GENERIC MAP (
+ clk0_divide_by => 1,
+ clk0_duty_cycle => 50,
+ clk0_multiply_by => 4,
+ clk0_phase_shift => "0",
+ compensate_clock => "CLK0",
+ inclk0_input_frequency => 40000,
+ intended_device_family => "Cyclone II",
+ lpm_hint => "CBX_MODULE_PREFIX=pll",
+ lpm_type => "altpll",
+ operation_mode => "NORMAL",
+ port_activeclock => "PORT_UNUSED",
+ port_areset => "PORT_UNUSED",
+ port_clkbad0 => "PORT_UNUSED",
+ port_clkbad1 => "PORT_UNUSED",
+ port_clkloss => "PORT_UNUSED",
+ port_clkswitch => "PORT_UNUSED",
+ port_configupdate => "PORT_UNUSED",
+ port_fbin => "PORT_UNUSED",
+ port_inclk0 => "PORT_USED",
+ port_inclk1 => "PORT_UNUSED",
+ port_locked => "PORT_UNUSED",
+ port_pfdena => "PORT_UNUSED",
+ port_phasecounterselect => "PORT_UNUSED",
+ port_phasedone => "PORT_UNUSED",
+ port_phasestep => "PORT_UNUSED",
+ port_phaseupdown => "PORT_UNUSED",
+ port_pllena => "PORT_UNUSED",
+ port_scanaclr => "PORT_UNUSED",
+ port_scanclk => "PORT_UNUSED",
+ port_scanclkena => "PORT_UNUSED",
+ port_scandata => "PORT_UNUSED",
+ port_scandataout => "PORT_UNUSED",
+ port_scandone => "PORT_UNUSED",
+ port_scanread => "PORT_UNUSED",
+ port_scanwrite => "PORT_UNUSED",
+ port_clk0 => "PORT_USED",
+ port_clk1 => "PORT_UNUSED",
+ port_clk2 => "PORT_UNUSED",
+ port_clk3 => "PORT_UNUSED",
+ port_clk4 => "PORT_UNUSED",
+ port_clk5 => "PORT_UNUSED",
+ port_clkena0 => "PORT_UNUSED",
+ port_clkena1 => "PORT_UNUSED",
+ port_clkena2 => "PORT_UNUSED",
+ port_clkena3 => "PORT_UNUSED",
+ port_clkena4 => "PORT_UNUSED",
+ port_clkena5 => "PORT_UNUSED",
+ port_extclk0 => "PORT_UNUSED",
+ port_extclk1 => "PORT_UNUSED",
+ port_extclk2 => "PORT_UNUSED",
+ port_extclk3 => "PORT_UNUSED"
+ )
+ PORT MAP (
+ inclk => sub_wire3,
+ clk => sub_wire0
+ );
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "25.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "300.000"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "40000"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
+-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_waveforms.html TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_wave*.jpg FALSE FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
projects / hwmod.git / commitdiff