demo/quartus/demo.eda.rpt

   1 EDA Netlist Writer report for demo
   2 Mon Mar 30 19:53:36 2009
   3 Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version
   4
   5
   6 ---------------------
   7 ; Table of Contents ;
   8 ---------------------
   9   1. Legal Notice
  10   2. EDA Netlist Writer Summary
  11   3. Simulation Settings
  12   4. Simulation Generated Files
  13   5. EDA Netlist Writer Messages
  14
  15
  16
  17 ----------------
  18 ; Legal Notice ;
  19 ----------------
  20 Copyright (C) 1991-2007 Altera Corporation
  21 Your use of Altera Corporation's design tools, logic functions
  22 and other software and tools, and its AMPP partner logic
  23 functions, and any output files from any of the foregoing
  24 (including device programming or simulation files), and any
  25 associated documentation or information are expressly subject
  26 to the terms and conditions of the Altera Program License
  27 Subscription Agreement, Altera MegaCore Function License
  28 Agreement, or other applicable license agreement, including,
  29 without limitation, that your use is for the sole purpose of
  30 programming logic devices manufactured by Altera and sold by
  31 Altera or its authorized distributors.  Please refer to the
  32 applicable agreement for further details.
  33
  34
  35
  36 +-------------------------------------------------------------------+
  37 ; EDA Netlist Writer Summary                                        ;
  38 +---------------------------+---------------------------------------+
  39 ; EDA Netlist Writer Status ; Successful - Mon Mar 30 19:53:36 2009 ;
  40 ; Revision Name             ; demo                                  ;
  41 ; Top-level Entity Name     ; demo_top                              ;
  42 ; Family                    ; Cyclone II                            ;
  43 ; Simulation Files Creation ; Successful                            ;
  44 +---------------------------+---------------------------------------+
  45
  46
  47 +--------------------------------------------------------------------------------------------------------------+
  48 ; Simulation Settings                                                                                          ;
  49 +--------------------------------------------------------------------------------------------+-----------------+
  50 ; Option                                                                                     ; Setting         ;
  51 +--------------------------------------------------------------------------------------------+-----------------+
  52 ; Tool Name                                                                                  ; ModelSim (VHDL) ;
  53 ; Generate netlist for functional simulation only                                            ; Off             ;
  54 ; Time scale                                                                                 ; 1 ps            ;
  55 ; Truncate long hierarchy paths                                                              ; Off             ;
  56 ; Map illegal HDL characters                                                                 ; Off             ;
  57 ; Flatten buses into individual nodes                                                        ; Off             ;
  58 ; Maintain hierarchy                                                                         ; Off             ;
  59 ; Bring out device-wide set/reset signals as ports                                           ; Off             ;
  60 ; Enable glitch filtering                                                                    ; Off             ;
  61 ; Do not write top level VHDL entity                                                         ; Off             ;
  62 ; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off             ;
  63 ; Architecture name in VHDL output netlist                                                   ; structure       ;
  64 +--------------------------------------------------------------------------------------------+-----------------+
  65
  66
  67 +-----------------------------------------------------------------------------------------------------------------+
  68 ; Simulation Generated Files                                                                                      ;
  69 +-----------------------------------------------------------------------------------------------------------------+
  70 ; Generated Files                                                                                                 ;
  71 +-----------------------------------------------------------------------------------------------------------------+
  72 ; /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/simulation/modelsim/demo.vho     ;
  73 ; /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/simulation/modelsim/demo_vhd.sdo ;
  74 +-----------------------------------------------------------------------------------------------------------------+
  75
  76
  77 +-----------------------------+
  78 ; EDA Netlist Writer Messages ;
  79 +-----------------------------+
  80 Info: *******************************************************************
  81 Info: Running Quartus II EDA Netlist Writer
  82     Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
  83     Info: Processing started: Mon Mar 30 19:53:35 2009
  84 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off demo -c demo
  85 Info: Generated files "demo.vho" and "demo_vhd.sdo" in directory "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/simulation/modelsim/" for EDA simulation tool
  86 Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings
  87     Info: Processing ended: Mon Mar 30 19:53:36 2009
  88     Info: Elapsed time: 00:00:01
  89
  90