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[hwmod.git] / demo / quartus / db / demo.fit.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 30 19:52:45 2009 " "Info: Processing started: Mon Mar 30 19:52:45 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off demo -c demo " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off demo -c demo" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "demo EP2C35F484C6 " "Info: Selected device EP2C35F484C6 for design \"demo\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "pll:inst1\|altpll:altpll_component\|pll Cyclone II " "Info: Implemented PLL \"pll:inst1\|altpll:altpll_component\|pll\" as Cyclone II PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "pll:inst1\|altpll:altpll_component\|_clk0 4 1 0 0 " "Info: Implementing clock multiplication of 4, clock division of 1, and phase shift of 0 degrees (0 ps) for pll:inst1\|altpll:altpll_component\|_clk0 port" {  } { { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0}  } { { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "Implemented PLL \"%1!s!\" as %2!s! PLL type" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 0 "Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" 0 0}
{ "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_TOP" "1 0 " "Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use" { { "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_NONE_OVERRIDE" "92 Top " "Info: Previous placement does not exist for 92 of 92 atoms in partition Top" {  } {  } 0 0 "Previous placement does not exist for %1!d! of %1!d! atoms in partition %2!s!" 0 0}  } {  } 0 0 "The Fitter has identified %1!d! logical partitions of which %2!d! have a previous placement to use" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C15AF484C6 " "Info: Device EP2C15AF484C6 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C20F484C6 " "Info: Device EP2C20F484C6 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F484C6 " "Info: Device EP2C50F484C6 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ C4 " "Info: Pin ~ASDO~ is reserved at location C4" {  } {  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ C3 " "Info: Pin ~nCSO~ is reserved at location C3" {  } {  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS150p/nCEO~ W20 " "Info: Pin ~LVDS150p/nCEO~ is reserved at location W20" {  } {  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "pll:inst1\|altpll:altpll_component\|_clk0 (placed in counter C0 of PLL_1) " "Info: Automatically promoted node pll:inst1\|altpll:altpll_component\|_clk0 (placed in counter C0 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0}  } { { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 495 3 0 } } { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "" { pll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "" { pll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:01 " "Info: Finished register packing: elapsed time is 00:00:01" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0}  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "6.881 ns register register " "Info: Estimated most critical path is register to register delay of 6.881 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns demo:inst\|counter\[3\] 1 REG LAB_X57_Y31 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X57_Y31; Fanout = 3; REG Node = 'demo:inst\|counter\[3\]'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "" { demo:inst|counter[3] } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.914 ns) + CELL(0.414 ns) 1.328 ns demo:inst\|Add0~101 2 COMB LAB_X55_Y31 2 " "Info: 2: + IC(0.914 ns) + CELL(0.414 ns) = 1.328 ns; Loc. = LAB_X55_Y31; Fanout = 2; COMB Node = 'demo:inst\|Add0~101'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "1.328 ns" { demo:inst|counter[3] demo:inst|Add0~101 } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 86 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 1.738 ns demo:inst\|Add0~102 3 COMB LAB_X55_Y31 3 " "Info: 3: + IC(0.000 ns) + CELL(0.410 ns) = 1.738 ns; Loc. = LAB_X55_Y31; Fanout = 3; COMB Node = 'demo:inst\|Add0~102'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.410 ns" { demo:inst|Add0~101 demo:inst|Add0~102 } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 86 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.397 ns) + CELL(0.414 ns) 2.549 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[3\]~19 4 COMB LAB_X55_Y31 2 " "Info: 4: + IC(0.397 ns) + CELL(0.414 ns) = 2.549 ns; Loc. = LAB_X55_Y31; Fanout = 2; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[3\]~19'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.811 ns" { demo:inst|Add0~102 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[3]~19 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 57 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.620 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[4\]~21 5 COMB LAB_X55_Y31 2 " "Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 2.620 ns; Loc. = LAB_X55_Y31; Fanout = 2; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[4\]~21'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.071 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[3]~19 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[4]~21 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 57 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.691 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[5\]~23 6 COMB LAB_X55_Y31 2 " "Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 2.691 ns; Loc. = LAB_X55_Y31; Fanout = 2; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[5\]~23'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.071 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[4]~21 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[5]~23 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 57 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.762 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[6\]~25 7 COMB LAB_X55_Y31 1 " "Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 2.762 ns; Loc. = LAB_X55_Y31; Fanout = 1; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[6\]~25'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.071 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[5]~23 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[6]~25 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 57 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 3.172 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[7\]~26 8 COMB LAB_X55_Y31 14 " "Info: 8: + IC(0.000 ns) + CELL(0.410 ns) = 3.172 ns; Loc. = LAB_X55_Y31; Fanout = 14; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[7\]~26'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.410 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[6]~25 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[7]~26 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 57 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.587 ns) + CELL(0.437 ns) 4.196 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|StageOut\[49\]~22 9 COMB LAB_X57_Y31 2 " "Info: 9: + IC(0.587 ns) + CELL(0.437 ns) = 4.196 ns; Loc. = LAB_X57_Y31; Fanout = 2; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|StageOut\[49\]~22'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "1.024 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[7]~26 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[49]~22 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 79 10 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.397 ns) + CELL(0.414 ns) 5.007 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[2\]~21 10 COMB LAB_X57_Y31 2 " "Info: 10: + IC(0.397 ns) + CELL(0.414 ns) = 5.007 ns; Loc. = LAB_X57_Y31; Fanout = 2; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[2\]~21'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.811 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[49]~22 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[2]~21 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 62 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 5.078 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[3\]~23 11 COMB LAB_X57_Y31 2 " "Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 5.078 ns; Loc. = LAB_X57_Y31; Fanout = 2; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[3\]~23'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.071 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[2]~21 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[3]~23 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 62 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 5.149 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[4\]~25 12 COMB LAB_X57_Y31 2 " "Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 5.149 ns; Loc. = LAB_X57_Y31; Fanout = 2; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[4\]~25'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.071 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[3]~23 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[4]~25 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 62 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 5.220 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[5\]~27 13 COMB LAB_X57_Y31 2 " "Info: 13: + IC(0.000 ns) + CELL(0.071 ns) = 5.220 ns; Loc. = LAB_X57_Y31; Fanout = 2; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[5\]~27'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.071 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[4]~25 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[5]~27 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 62 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 5.291 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[6\]~29 14 COMB LAB_X57_Y31 1 " "Info: 14: + IC(0.000 ns) + CELL(0.071 ns) = 5.291 ns; Loc. = LAB_X57_Y31; Fanout = 1; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[6\]~29'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.071 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[5]~27 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[6]~29 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 62 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 5.362 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[7\]~31 15 COMB LAB_X57_Y31 1 " "Info: 15: + IC(0.000 ns) + CELL(0.071 ns) = 5.362 ns; Loc. = LAB_X57_Y31; Fanout = 1; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[7\]~31'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.071 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[6]~29 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[7]~31 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 62 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 5.772 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[8\]~32 16 COMB LAB_X57_Y31 7 " "Info: 16: + IC(0.000 ns) + CELL(0.410 ns) = 5.772 ns; Loc. = LAB_X57_Y31; Fanout = 7; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[8\]~32'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.410 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[7]~31 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[8]~32 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 62 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.875 ns) + CELL(0.150 ns) 6.797 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|StageOut\[57\]~636 17 COMB LAB_X55_Y31 1 " "Info: 17: + IC(0.875 ns) + CELL(0.150 ns) = 6.797 ns; Loc. = LAB_X55_Y31; Fanout = 1; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|StageOut\[57\]~636'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "1.025 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[8]~32 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[57]~636 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 79 10 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 6.881 ns demo:inst\|counter\[1\] 18 REG LAB_X55_Y31 3 " "Info: 18: + IC(0.000 ns) + CELL(0.084 ns) = 6.881 ns; Loc. = LAB_X55_Y31; Fanout = 3; REG Node = 'demo:inst\|counter\[1\]'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.084 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[57]~636 demo:inst|counter[1] } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.711 ns ( 53.93 % ) " "Info: Total cell delay = 3.711 ns ( 53.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.170 ns ( 46.07 % ) " "Info: Total interconnect delay = 3.170 ns ( 46.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "6.881 ns" { demo:inst|counter[3] demo:inst|Add0~101 demo:inst|Add0~102 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[3]~19 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[4]~21 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[5]~23 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[6]~25 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[7]~26 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[49]~22 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[2]~21 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[3]~23 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[4]~25 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[5]~27 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[6]~29 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[7]~31 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[8]~32 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[57]~636 demo:inst|counter[1] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X22_Y12 X32_Y23 " "Info: The peak interconnect region extends from location X22_Y12 to location X32_Y23" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "8 " "Warning: Found 8 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDS\[7\] 0 " "Info: Pin \"LEDS\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDS\[6\] 0 " "Info: Pin \"LEDS\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDS\[5\] 0 " "Info: Pin \"LEDS\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDS\[4\] 0 " "Info: Pin \"LEDS\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDS\[3\] 0 " "Info: Pin \"LEDS\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDS\[2\] 0 " "Info: Pin \"LEDS\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDS\[1\] 0 " "Info: Pin \"LEDS\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDS\[0\] 0 " "Info: Pin \"LEDS\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 30 19:52:59 2009 " "Info: Processing ended: Mon Mar 30 19:52:59 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Info: Elapsed time: 00:00:14" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/demo.fit.smsg " "Info: Generated suppressed messages file /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/demo.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}