1 Analysis & Synthesis report for demo
2 Mon Mar 30 19:52:38 2009
3 Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version
10 2. Analysis & Synthesis Summary
11 3. Analysis & Synthesis Settings
12 4. Analysis & Synthesis Source Files Read
13 5. Analysis & Synthesis Resource Usage Summary
14 6. Analysis & Synthesis Resource Utilization by Entity
15 7. General Register Statistics
16 8. Multiplexer Restructuring Statistics (Restructuring Performed)
17 9. Parameter Settings for User Entity Instance: pll:inst1|altpll:altpll_component
18 10. Parameter Settings for Inferred Entity Instance: demo:inst|lpm_divide:Mod0
19 11. Analysis & Synthesis Messages
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28 and other software and tools, and its AMPP partner logic
29 functions, and any output files from any of the foregoing
30 (including device programming or simulation files), and any
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35 without limitation, that your use is for the sole purpose of
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42 +------------------------------------------------------------------------------+
43 ; Analysis & Synthesis Summary ;
44 +------------------------------------+-----------------------------------------+
45 ; Analysis & Synthesis Status ; Successful - Mon Mar 30 19:52:38 2009 ;
46 ; Quartus II Version ; 7.0 Build 33 02/05/2007 SJ Full Version ;
47 ; Revision Name ; demo ;
48 ; Top-level Entity Name ; demo_top ;
49 ; Family ; Cyclone II ;
50 ; Total logic elements ; 73 ;
51 ; Total combinational functions ; 73 ;
52 ; Dedicated logic registers ; 16 ;
53 ; Total registers ; N/A until Partition Merge ;
54 ; Total pins ; N/A until Partition Merge ;
55 ; Total virtual pins ; N/A until Partition Merge ;
56 ; Total memory bits ; N/A until Partition Merge ;
57 ; Embedded Multiplier 9-bit elements ; N/A until Partition Merge ;
58 ; Total PLLs ; N/A until Partition Merge ;
59 +------------------------------------+-----------------------------------------+
62 +--------------------------------------------------------------------------------------------------------------+
63 ; Analysis & Synthesis Settings ;
64 +--------------------------------------------------------------------+--------------------+--------------------+
65 ; Option ; Setting ; Default Value ;
66 +--------------------------------------------------------------------+--------------------+--------------------+
67 ; Device ; EP2C35F484C6 ; ;
68 ; Top-level entity name ; demo_top ; demo ;
69 ; Family name ; Cyclone II ; Stratix ;
70 ; Type of Retiming Performed During Resynthesis ; Full ; ;
71 ; Resynthesis Optimization Effort ; Normal ; ;
72 ; Physical Synthesis Level for Resynthesis ; Normal ; ;
73 ; Use Generated Physical Constraints File ; On ; ;
74 ; Restructure Multiplexers ; Auto ; Auto ;
75 ; Create Debugging Nodes for IP Cores ; Off ; Off ;
76 ; Preserve fewer node names ; On ; On ;
77 ; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
78 ; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
79 ; VHDL Version ; VHDL93 ; VHDL93 ;
80 ; State Machine Processing ; Auto ; Auto ;
81 ; Safe State Machine ; Off ; Off ;
82 ; Extract Verilog State Machines ; On ; On ;
83 ; Extract VHDL State Machines ; On ; On ;
84 ; Ignore Verilog initial constructs ; Off ; Off ;
85 ; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
86 ; DSP Block Balancing ; Auto ; Auto ;
87 ; NOT Gate Push-Back ; On ; On ;
88 ; Power-Up Don't Care ; On ; On ;
89 ; Remove Redundant Logic Cells ; Off ; Off ;
90 ; Remove Duplicate Registers ; On ; On ;
91 ; Ignore CARRY Buffers ; Off ; Off ;
92 ; Ignore CASCADE Buffers ; Off ; Off ;
93 ; Ignore GLOBAL Buffers ; Off ; Off ;
94 ; Ignore ROW GLOBAL Buffers ; Off ; Off ;
95 ; Ignore LCELL Buffers ; Off ; Off ;
96 ; Ignore SOFT Buffers ; On ; On ;
97 ; Limit AHDL Integers to 32 Bits ; Off ; Off ;
98 ; Optimization Technique -- Cyclone II ; Balanced ; Balanced ;
99 ; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70 ; 70 ;
100 ; Auto Carry Chains ; On ; On ;
101 ; Auto Open-Drain Pins ; On ; On ;
102 ; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
103 ; Perform gate-level register retiming ; Off ; Off ;
104 ; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
105 ; Auto ROM Replacement ; On ; On ;
106 ; Auto RAM Replacement ; On ; On ;
107 ; Auto Shift Register Replacement ; On ; On ;
108 ; Auto Clock Enable Replacement ; On ; On ;
109 ; Allow Synchronous Control Signals ; On ; On ;
110 ; Force Use of Synchronous Clear Signals ; Off ; Off ;
111 ; Auto RAM to Logic Cell Conversion ; Off ; Off ;
112 ; Auto Resource Sharing ; Off ; Off ;
113 ; Allow Any RAM Size For Recognition ; Off ; Off ;
114 ; Allow Any ROM Size For Recognition ; Off ; Off ;
115 ; Allow Any Shift Register Size For Recognition ; Off ; Off ;
116 ; Ignore translate_off and synthesis_off directives ; Off ; Off ;
117 ; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
118 ; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
119 ; Retiming Meta-Stability Register Sequence Length ; 2 ; 2 ;
120 ; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
121 ; HDL message level ; Level2 ; Level2 ;
122 ; Suppress Register Optimization Related Messages ; Off ; Off ;
123 ; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
124 ; Use smart compilation ; Off ; Off ;
125 +--------------------------------------------------------------------+--------------------+--------------------+
128 +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
129 ; Analysis & Synthesis Source Files Read ;
130 +----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------------------------------+
131 ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
132 +----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------------------------------+
133 ; ../src/demo_pkg.vhd ; yes ; User VHDL File ; /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo_pkg.vhd ;
134 ; ../src/demo.vhd ; yes ; User VHDL File ; /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd ;
135 ; ../src/pll.vhd ; yes ; User VHDL File ; /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/pll.vhd ;
136 ; ../src/demo_top.bdf ; yes ; User Block Diagram/Schematic File ; /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo_top.bdf ;
137 ; altpll.tdf ; yes ; Megafunction ; /opt/quartus/libraries/megafunctions/altpll.tdf ;
138 ; aglobal70.inc ; yes ; Megafunction ; /opt/quartus/libraries/megafunctions/aglobal70.inc ;
139 ; stratix_pll.inc ; yes ; Megafunction ; /opt/quartus/libraries/megafunctions/stratix_pll.inc ;
140 ; stratixii_pll.inc ; yes ; Megafunction ; /opt/quartus/libraries/megafunctions/stratixii_pll.inc ;
141 ; cycloneii_pll.inc ; yes ; Megafunction ; /opt/quartus/libraries/megafunctions/cycloneii_pll.inc ;
142 ; lpm_divide.tdf ; yes ; Megafunction ; /opt/quartus/libraries/megafunctions/lpm_divide.tdf ;
143 ; abs_divider.inc ; yes ; Megafunction ; /opt/quartus/libraries/megafunctions/abs_divider.inc ;
144 ; sign_div_unsign.inc ; yes ; Megafunction ; /opt/quartus/libraries/megafunctions/sign_div_unsign.inc ;
145 ; db/lpm_divide_85m.tdf ; yes ; Auto-Generated Megafunction ; /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/lpm_divide_85m.tdf ;
146 ; db/sign_div_unsign_fkh.tdf ; yes ; Auto-Generated Megafunction ; /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/sign_div_unsign_fkh.tdf ;
147 ; db/alt_u_div_00f.tdf ; yes ; Auto-Generated Megafunction ; /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf ;
148 ; db/add_sub_lkc.tdf ; yes ; Auto-Generated Megafunction ; /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/add_sub_lkc.tdf ;
149 ; db/add_sub_mkc.tdf ; yes ; Auto-Generated Megafunction ; /homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/add_sub_mkc.tdf ;
150 +----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------------------------------+
153 +---------------------------------------------------------------------------------------+
154 ; Analysis & Synthesis Resource Usage Summary ;
155 +---------------------------------------------+-----------------------------------------+
157 +---------------------------------------------+-----------------------------------------+
158 ; Estimated Total logic elements ; 73 ;
160 ; Total combinational functions ; 73 ;
161 ; Logic element usage by number of LUT inputs ; ;
162 ; -- 4 input functions ; 11 ;
163 ; -- 3 input functions ; 23 ;
164 ; -- <=2 input functions ; 39 ;
166 ; Logic elements by mode ; ;
167 ; -- normal mode ; 56 ;
168 ; -- arithmetic mode ; 17 ;
170 ; Total registers ; 16 ;
171 ; -- Dedicated logic registers ; 16 ;
172 ; -- I/O registers ; 0 ;
176 ; Maximum fan-out node ; pll:inst1|altpll:altpll_component|_clk0 ;
177 ; Maximum fan-out ; 16 ;
178 ; Total fan-out ; 233 ;
179 ; Average fan-out ; 2.33 ;
180 +---------------------------------------------+-----------------------------------------+
183 +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
184 ; Analysis & Synthesis Resource Utilization by Entity ;
185 +-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------------------------------------------+
186 ; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
187 +-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------------------------------------------+
188 ; |demo_top ; 73 (0) ; 16 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |demo_top ;
189 ; |demo:inst| ; 73 (37) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |demo_top|demo:inst ;
190 ; |lpm_divide:Mod0| ; 36 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |demo_top|demo:inst|lpm_divide:Mod0 ;
191 ; |lpm_divide_85m:auto_generated| ; 36 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |demo_top|demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated ;
192 ; |sign_div_unsign_fkh:divider| ; 36 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |demo_top|demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider ;
193 ; |alt_u_div_00f:divider| ; 36 (36) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |demo_top|demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider ;
194 ; |pll:inst1| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |demo_top|pll:inst1 ;
195 ; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |demo_top|pll:inst1|altpll:altpll_component ;
196 +-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------------------------------------------+
197 Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
200 +------------------------------------------------------+
201 ; General Register Statistics ;
202 +----------------------------------------------+-------+
203 ; Statistic ; Value ;
204 +----------------------------------------------+-------+
205 ; Total registers ; 16 ;
206 ; Number of registers using Synchronous Clear ; 13 ;
207 ; Number of registers using Synchronous Load ; 3 ;
208 ; Number of registers using Asynchronous Clear ; 0 ;
209 ; Number of registers using Asynchronous Load ; 0 ;
210 ; Number of registers using Clock Enable ; 0 ;
211 ; Number of registers using Preset ; 0 ;
212 +----------------------------------------------+-------+
215 +--------------------------------------------------------------------------------------------------------------------------------------------------+
216 ; Multiplexer Restructuring Statistics (Restructuring Performed) ;
217 +--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------+
218 ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
219 +--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------+
220 ; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; Yes ; |demo_top|demo:inst|knightlight[7] ;
221 ; 3:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |demo_top|demo:inst|knightlight[2] ;
222 +--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------+
225 +--------------------------------------------------------------------------------+
226 ; Parameter Settings for User Entity Instance: pll:inst1|altpll:altpll_component ;
227 +-------------------------------+-------------------+----------------------------+
228 ; Parameter Name ; Value ; Type ;
229 +-------------------------------+-------------------+----------------------------+
230 ; OPERATION_MODE ; NORMAL ; Untyped ;
231 ; PLL_TYPE ; AUTO ; Untyped ;
232 ; QUALIFY_CONF_DONE ; OFF ; Untyped ;
233 ; COMPENSATE_CLOCK ; CLK0 ; Untyped ;
234 ; SCAN_CHAIN ; LONG ; Untyped ;
235 ; PRIMARY_CLOCK ; INCLK0 ; Untyped ;
236 ; INCLK0_INPUT_FREQUENCY ; 40000 ; Signed Integer ;
237 ; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ;
238 ; GATE_LOCK_SIGNAL ; NO ; Untyped ;
239 ; GATE_LOCK_COUNTER ; 0 ; Untyped ;
240 ; LOCK_HIGH ; 1 ; Untyped ;
241 ; LOCK_LOW ; 1 ; Untyped ;
242 ; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ;
243 ; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ;
244 ; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ;
245 ; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ;
246 ; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ;
247 ; SKIP_VCO ; OFF ; Untyped ;
248 ; SWITCH_OVER_COUNTER ; 0 ; Untyped ;
249 ; SWITCH_OVER_TYPE ; AUTO ; Untyped ;
250 ; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ;
251 ; BANDWIDTH ; 0 ; Untyped ;
252 ; BANDWIDTH_TYPE ; AUTO ; Untyped ;
253 ; SPREAD_FREQUENCY ; 0 ; Untyped ;
254 ; DOWN_SPREAD ; 0 ; Untyped ;
255 ; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ;
256 ; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ;
257 ; CLK9_MULTIPLY_BY ; 0 ; Untyped ;
258 ; CLK8_MULTIPLY_BY ; 0 ; Untyped ;
259 ; CLK7_MULTIPLY_BY ; 0 ; Untyped ;
260 ; CLK6_MULTIPLY_BY ; 0 ; Untyped ;
261 ; CLK5_MULTIPLY_BY ; 1 ; Untyped ;
262 ; CLK4_MULTIPLY_BY ; 1 ; Untyped ;
263 ; CLK3_MULTIPLY_BY ; 1 ; Untyped ;
264 ; CLK2_MULTIPLY_BY ; 1 ; Untyped ;
265 ; CLK1_MULTIPLY_BY ; 1 ; Untyped ;
266 ; CLK0_MULTIPLY_BY ; 4 ; Signed Integer ;
267 ; CLK9_DIVIDE_BY ; 0 ; Untyped ;
268 ; CLK8_DIVIDE_BY ; 0 ; Untyped ;
269 ; CLK7_DIVIDE_BY ; 0 ; Untyped ;
270 ; CLK6_DIVIDE_BY ; 0 ; Untyped ;
271 ; CLK5_DIVIDE_BY ; 1 ; Untyped ;
272 ; CLK4_DIVIDE_BY ; 1 ; Untyped ;
273 ; CLK3_DIVIDE_BY ; 1 ; Untyped ;
274 ; CLK2_DIVIDE_BY ; 1 ; Untyped ;
275 ; CLK1_DIVIDE_BY ; 1 ; Untyped ;
276 ; CLK0_DIVIDE_BY ; 1 ; Signed Integer ;
277 ; CLK9_PHASE_SHIFT ; 0 ; Untyped ;
278 ; CLK8_PHASE_SHIFT ; 0 ; Untyped ;
279 ; CLK7_PHASE_SHIFT ; 0 ; Untyped ;
280 ; CLK6_PHASE_SHIFT ; 0 ; Untyped ;
281 ; CLK5_PHASE_SHIFT ; 0 ; Untyped ;
282 ; CLK4_PHASE_SHIFT ; 0 ; Untyped ;
283 ; CLK3_PHASE_SHIFT ; 0 ; Untyped ;
284 ; CLK2_PHASE_SHIFT ; 0 ; Untyped ;
285 ; CLK1_PHASE_SHIFT ; 0 ; Untyped ;
286 ; CLK0_PHASE_SHIFT ; 0 ; Untyped ;
287 ; CLK5_TIME_DELAY ; 0 ; Untyped ;
288 ; CLK4_TIME_DELAY ; 0 ; Untyped ;
289 ; CLK3_TIME_DELAY ; 0 ; Untyped ;
290 ; CLK2_TIME_DELAY ; 0 ; Untyped ;
291 ; CLK1_TIME_DELAY ; 0 ; Untyped ;
292 ; CLK0_TIME_DELAY ; 0 ; Untyped ;
293 ; CLK9_DUTY_CYCLE ; 50 ; Untyped ;
294 ; CLK8_DUTY_CYCLE ; 50 ; Untyped ;
295 ; CLK7_DUTY_CYCLE ; 50 ; Untyped ;
296 ; CLK6_DUTY_CYCLE ; 50 ; Untyped ;
297 ; CLK5_DUTY_CYCLE ; 50 ; Untyped ;
298 ; CLK4_DUTY_CYCLE ; 50 ; Untyped ;
299 ; CLK3_DUTY_CYCLE ; 50 ; Untyped ;
300 ; CLK2_DUTY_CYCLE ; 50 ; Untyped ;
301 ; CLK1_DUTY_CYCLE ; 50 ; Untyped ;
302 ; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ;
303 ; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
304 ; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
305 ; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
306 ; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
307 ; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
308 ; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
309 ; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
310 ; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
311 ; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
312 ; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
313 ; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
314 ; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
315 ; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
316 ; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
317 ; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
318 ; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
319 ; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
320 ; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
321 ; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
322 ; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
323 ; LOCK_WINDOW_UI ; 0.05 ; Untyped ;
324 ; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ;
325 ; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ;
326 ; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ;
327 ; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ;
328 ; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ;
329 ; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ;
330 ; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ;
331 ; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ;
332 ; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ;
333 ; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ;
334 ; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ;
335 ; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ;
336 ; EXTCLK3_TIME_DELAY ; 0 ; Untyped ;
337 ; EXTCLK2_TIME_DELAY ; 0 ; Untyped ;
338 ; EXTCLK1_TIME_DELAY ; 0 ; Untyped ;
339 ; EXTCLK0_TIME_DELAY ; 0 ; Untyped ;
340 ; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ;
341 ; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ;
342 ; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ;
343 ; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ;
344 ; VCO_MULTIPLY_BY ; 0 ; Untyped ;
345 ; VCO_DIVIDE_BY ; 0 ; Untyped ;
346 ; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ;
347 ; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ;
348 ; VCO_MIN ; 0 ; Untyped ;
349 ; VCO_MAX ; 0 ; Untyped ;
350 ; VCO_CENTER ; 0 ; Untyped ;
351 ; PFD_MIN ; 0 ; Untyped ;
352 ; PFD_MAX ; 0 ; Untyped ;
353 ; M_INITIAL ; 0 ; Untyped ;
359 ; C0_HIGH ; 0 ; Untyped ;
360 ; C1_HIGH ; 0 ; Untyped ;
361 ; C2_HIGH ; 0 ; Untyped ;
362 ; C3_HIGH ; 0 ; Untyped ;
363 ; C4_HIGH ; 0 ; Untyped ;
364 ; C5_HIGH ; 0 ; Untyped ;
365 ; C6_HIGH ; 0 ; Untyped ;
366 ; C7_HIGH ; 0 ; Untyped ;
367 ; C8_HIGH ; 0 ; Untyped ;
368 ; C9_HIGH ; 0 ; Untyped ;
369 ; C0_LOW ; 0 ; Untyped ;
370 ; C1_LOW ; 0 ; Untyped ;
371 ; C2_LOW ; 0 ; Untyped ;
372 ; C3_LOW ; 0 ; Untyped ;
373 ; C4_LOW ; 0 ; Untyped ;
374 ; C5_LOW ; 0 ; Untyped ;
375 ; C6_LOW ; 0 ; Untyped ;
376 ; C7_LOW ; 0 ; Untyped ;
377 ; C8_LOW ; 0 ; Untyped ;
378 ; C9_LOW ; 0 ; Untyped ;
379 ; C0_INITIAL ; 0 ; Untyped ;
380 ; C1_INITIAL ; 0 ; Untyped ;
381 ; C2_INITIAL ; 0 ; Untyped ;
382 ; C3_INITIAL ; 0 ; Untyped ;
383 ; C4_INITIAL ; 0 ; Untyped ;
384 ; C5_INITIAL ; 0 ; Untyped ;
385 ; C6_INITIAL ; 0 ; Untyped ;
386 ; C7_INITIAL ; 0 ; Untyped ;
387 ; C8_INITIAL ; 0 ; Untyped ;
388 ; C9_INITIAL ; 0 ; Untyped ;
389 ; C0_MODE ; BYPASS ; Untyped ;
390 ; C1_MODE ; BYPASS ; Untyped ;
391 ; C2_MODE ; BYPASS ; Untyped ;
392 ; C3_MODE ; BYPASS ; Untyped ;
393 ; C4_MODE ; BYPASS ; Untyped ;
394 ; C5_MODE ; BYPASS ; Untyped ;
395 ; C6_MODE ; BYPASS ; Untyped ;
396 ; C7_MODE ; BYPASS ; Untyped ;
397 ; C8_MODE ; BYPASS ; Untyped ;
398 ; C9_MODE ; BYPASS ; Untyped ;
399 ; C0_PH ; 0 ; Untyped ;
400 ; C1_PH ; 0 ; Untyped ;
401 ; C2_PH ; 0 ; Untyped ;
402 ; C3_PH ; 0 ; Untyped ;
403 ; C4_PH ; 0 ; Untyped ;
404 ; C5_PH ; 0 ; Untyped ;
405 ; C6_PH ; 0 ; Untyped ;
406 ; C7_PH ; 0 ; Untyped ;
407 ; C8_PH ; 0 ; Untyped ;
408 ; C9_PH ; 0 ; Untyped ;
409 ; L0_HIGH ; 1 ; Untyped ;
410 ; L1_HIGH ; 1 ; Untyped ;
411 ; G0_HIGH ; 1 ; Untyped ;
412 ; G1_HIGH ; 1 ; Untyped ;
413 ; G2_HIGH ; 1 ; Untyped ;
414 ; G3_HIGH ; 1 ; Untyped ;
415 ; E0_HIGH ; 1 ; Untyped ;
416 ; E1_HIGH ; 1 ; Untyped ;
417 ; E2_HIGH ; 1 ; Untyped ;
418 ; E3_HIGH ; 1 ; Untyped ;
419 ; L0_LOW ; 1 ; Untyped ;
420 ; L1_LOW ; 1 ; Untyped ;
421 ; G0_LOW ; 1 ; Untyped ;
422 ; G1_LOW ; 1 ; Untyped ;
423 ; G2_LOW ; 1 ; Untyped ;
424 ; G3_LOW ; 1 ; Untyped ;
425 ; E0_LOW ; 1 ; Untyped ;
426 ; E1_LOW ; 1 ; Untyped ;
427 ; E2_LOW ; 1 ; Untyped ;
428 ; E3_LOW ; 1 ; Untyped ;
429 ; L0_INITIAL ; 1 ; Untyped ;
430 ; L1_INITIAL ; 1 ; Untyped ;
431 ; G0_INITIAL ; 1 ; Untyped ;
432 ; G1_INITIAL ; 1 ; Untyped ;
433 ; G2_INITIAL ; 1 ; Untyped ;
434 ; G3_INITIAL ; 1 ; Untyped ;
435 ; E0_INITIAL ; 1 ; Untyped ;
436 ; E1_INITIAL ; 1 ; Untyped ;
437 ; E2_INITIAL ; 1 ; Untyped ;
438 ; E3_INITIAL ; 1 ; Untyped ;
439 ; L0_MODE ; BYPASS ; Untyped ;
440 ; L1_MODE ; BYPASS ; Untyped ;
441 ; G0_MODE ; BYPASS ; Untyped ;
442 ; G1_MODE ; BYPASS ; Untyped ;
443 ; G2_MODE ; BYPASS ; Untyped ;
444 ; G3_MODE ; BYPASS ; Untyped ;
445 ; E0_MODE ; BYPASS ; Untyped ;
446 ; E1_MODE ; BYPASS ; Untyped ;
447 ; E2_MODE ; BYPASS ; Untyped ;
448 ; E3_MODE ; BYPASS ; Untyped ;
449 ; L0_PH ; 0 ; Untyped ;
450 ; L1_PH ; 0 ; Untyped ;
451 ; G0_PH ; 0 ; Untyped ;
452 ; G1_PH ; 0 ; Untyped ;
453 ; G2_PH ; 0 ; Untyped ;
454 ; G3_PH ; 0 ; Untyped ;
455 ; E0_PH ; 0 ; Untyped ;
456 ; E1_PH ; 0 ; Untyped ;
457 ; E2_PH ; 0 ; Untyped ;
458 ; E3_PH ; 0 ; Untyped ;
459 ; M_PH ; 0 ; Untyped ;
460 ; C1_USE_CASC_IN ; OFF ; Untyped ;
461 ; C2_USE_CASC_IN ; OFF ; Untyped ;
462 ; C3_USE_CASC_IN ; OFF ; Untyped ;
463 ; C4_USE_CASC_IN ; OFF ; Untyped ;
464 ; C5_USE_CASC_IN ; OFF ; Untyped ;
465 ; C6_USE_CASC_IN ; OFF ; Untyped ;
466 ; C7_USE_CASC_IN ; OFF ; Untyped ;
467 ; C8_USE_CASC_IN ; OFF ; Untyped ;
468 ; C9_USE_CASC_IN ; OFF ; Untyped ;
469 ; CLK0_COUNTER ; G0 ; Untyped ;
470 ; CLK1_COUNTER ; G0 ; Untyped ;
471 ; CLK2_COUNTER ; G0 ; Untyped ;
472 ; CLK3_COUNTER ; G0 ; Untyped ;
473 ; CLK4_COUNTER ; G0 ; Untyped ;
474 ; CLK5_COUNTER ; G0 ; Untyped ;
475 ; L0_TIME_DELAY ; 0 ; Untyped ;
476 ; L1_TIME_DELAY ; 0 ; Untyped ;
477 ; G0_TIME_DELAY ; 0 ; Untyped ;
478 ; G1_TIME_DELAY ; 0 ; Untyped ;
479 ; G2_TIME_DELAY ; 0 ; Untyped ;
480 ; G3_TIME_DELAY ; 0 ; Untyped ;
481 ; E0_TIME_DELAY ; 0 ; Untyped ;
482 ; E1_TIME_DELAY ; 0 ; Untyped ;
483 ; E2_TIME_DELAY ; 0 ; Untyped ;
484 ; E3_TIME_DELAY ; 0 ; Untyped ;
485 ; M_TIME_DELAY ; 0 ; Untyped ;
486 ; N_TIME_DELAY ; 0 ; Untyped ;
487 ; EXTCLK3_COUNTER ; E3 ; Untyped ;
488 ; EXTCLK2_COUNTER ; E2 ; Untyped ;
489 ; EXTCLK1_COUNTER ; E1 ; Untyped ;
490 ; EXTCLK0_COUNTER ; E0 ; Untyped ;
491 ; ENABLE0_COUNTER ; L0 ; Untyped ;
492 ; ENABLE1_COUNTER ; L0 ; Untyped ;
493 ; CHARGE_PUMP_CURRENT ; 2 ; Untyped ;
494 ; LOOP_FILTER_R ; 1.000000 ; Untyped ;
495 ; LOOP_FILTER_C ; 5 ; Untyped ;
496 ; VCO_POST_SCALE ; 0 ; Untyped ;
497 ; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ;
498 ; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ;
499 ; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ;
500 ; INTENDED_DEVICE_FAMILY ; Cyclone II ; Untyped ;
501 ; PORT_CLKENA0 ; PORT_UNUSED ; Untyped ;
502 ; PORT_CLKENA1 ; PORT_UNUSED ; Untyped ;
503 ; PORT_CLKENA2 ; PORT_UNUSED ; Untyped ;
504 ; PORT_CLKENA3 ; PORT_UNUSED ; Untyped ;
505 ; PORT_CLKENA4 ; PORT_UNUSED ; Untyped ;
506 ; PORT_CLKENA5 ; PORT_UNUSED ; Untyped ;
507 ; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ;
508 ; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ;
509 ; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ;
510 ; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ;
511 ; PORT_EXTCLK0 ; PORT_UNUSED ; Untyped ;
512 ; PORT_EXTCLK1 ; PORT_UNUSED ; Untyped ;
513 ; PORT_EXTCLK2 ; PORT_UNUSED ; Untyped ;
514 ; PORT_EXTCLK3 ; PORT_UNUSED ; Untyped ;
515 ; PORT_CLKBAD0 ; PORT_UNUSED ; Untyped ;
516 ; PORT_CLKBAD1 ; PORT_UNUSED ; Untyped ;
517 ; PORT_CLK0 ; PORT_USED ; Untyped ;
518 ; PORT_CLK1 ; PORT_UNUSED ; Untyped ;
519 ; PORT_CLK2 ; PORT_UNUSED ; Untyped ;
520 ; PORT_CLK3 ; PORT_UNUSED ; Untyped ;
521 ; PORT_CLK4 ; PORT_UNUSED ; Untyped ;
522 ; PORT_CLK5 ; PORT_UNUSED ; Untyped ;
523 ; PORT_CLK6 ; PORT_CONNECTIVITY ; Untyped ;
524 ; PORT_CLK7 ; PORT_CONNECTIVITY ; Untyped ;
525 ; PORT_CLK8 ; PORT_CONNECTIVITY ; Untyped ;
526 ; PORT_CLK9 ; PORT_CONNECTIVITY ; Untyped ;
527 ; PORT_SCANDATA ; PORT_UNUSED ; Untyped ;
528 ; PORT_SCANDATAOUT ; PORT_UNUSED ; Untyped ;
529 ; PORT_SCANDONE ; PORT_UNUSED ; Untyped ;
530 ; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ;
531 ; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ;
532 ; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ;
533 ; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ;
534 ; PORT_INCLK1 ; PORT_UNUSED ; Untyped ;
535 ; PORT_INCLK0 ; PORT_USED ; Untyped ;
536 ; PORT_FBIN ; PORT_UNUSED ; Untyped ;
537 ; PORT_PLLENA ; PORT_UNUSED ; Untyped ;
538 ; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ;
539 ; PORT_ARESET ; PORT_UNUSED ; Untyped ;
540 ; PORT_PFDENA ; PORT_UNUSED ; Untyped ;
541 ; PORT_SCANCLK ; PORT_UNUSED ; Untyped ;
542 ; PORT_SCANACLR ; PORT_UNUSED ; Untyped ;
543 ; PORT_SCANREAD ; PORT_UNUSED ; Untyped ;
544 ; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ;
545 ; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ;
546 ; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ;
547 ; PORT_LOCKED ; PORT_UNUSED ; Untyped ;
548 ; PORT_CONFIGUPDATE ; PORT_UNUSED ; Untyped ;
549 ; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ;
550 ; PORT_PHASEDONE ; PORT_UNUSED ; Untyped ;
551 ; PORT_PHASESTEP ; PORT_UNUSED ; Untyped ;
552 ; PORT_PHASEUPDOWN ; PORT_UNUSED ; Untyped ;
553 ; PORT_SCANCLKENA ; PORT_UNUSED ; Untyped ;
554 ; PORT_PHASECOUNTERSELECT ; PORT_UNUSED ; Untyped ;
555 ; M_TEST_SOURCE ; 5 ; Untyped ;
556 ; C0_TEST_SOURCE ; 5 ; Untyped ;
557 ; C1_TEST_SOURCE ; 5 ; Untyped ;
558 ; C2_TEST_SOURCE ; 5 ; Untyped ;
559 ; C3_TEST_SOURCE ; 5 ; Untyped ;
560 ; C4_TEST_SOURCE ; 5 ; Untyped ;
561 ; C5_TEST_SOURCE ; 5 ; Untyped ;
562 ; C6_TEST_SOURCE ; 0 ; Untyped ;
563 ; C7_TEST_SOURCE ; 0 ; Untyped ;
564 ; C8_TEST_SOURCE ; 0 ; Untyped ;
565 ; C9_TEST_SOURCE ; 0 ; Untyped ;
566 ; CBXI_PARAMETER ; NOTHING ; Untyped ;
567 ; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ;
568 ; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ;
569 ; WIDTH_CLOCK ; 6 ; Untyped ;
570 ; DEVICE_FAMILY ; Cyclone II ; Untyped ;
571 ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
572 ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
573 ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
574 ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
575 +-------------------------------+-------------------+----------------------------+
576 Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
579 +----------------------------------------------------------------------------+
580 ; Parameter Settings for Inferred Entity Instance: demo:inst|lpm_divide:Mod0 ;
581 +------------------------+----------------+----------------------------------+
582 ; Parameter Name ; Value ; Type ;
583 +------------------------+----------------+----------------------------------+
584 ; LPM_WIDTHN ; 8 ; Untyped ;
585 ; LPM_WIDTHD ; 8 ; Untyped ;
586 ; LPM_NREPRESENTATION ; UNSIGNED ; Untyped ;
587 ; LPM_DREPRESENTATION ; UNSIGNED ; Untyped ;
588 ; LPM_PIPELINE ; 0 ; Untyped ;
589 ; LPM_REMAINDERPOSITIVE ; TRUE ; Untyped ;
590 ; MAXIMIZE_SPEED ; 5 ; Untyped ;
591 ; CBXI_PARAMETER ; lpm_divide_85m ; Untyped ;
592 ; CARRY_CHAIN ; MANUAL ; Untyped ;
593 ; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
594 ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
595 ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
596 ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
597 ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
598 +------------------------+----------------+----------------------------------+
599 Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
602 +-------------------------------+
603 ; Analysis & Synthesis Messages ;
604 +-------------------------------+
605 Info: *******************************************************************
606 Info: Running Quartus II Analysis & Synthesis
607 Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
608 Info: Processing started: Mon Mar 30 19:52:35 2009
609 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off demo -c demo
610 Info: Found 1 design units, including 0 entities, in source file ../src/demo_pkg.vhd
611 Info: Found design unit 1: demo_pkg
612 Info: Found 2 design units, including 1 entities, in source file ../src/demo.vhd
613 Info: Found design unit 1: demo-behav
614 Info: Found entity 1: demo
615 Info: Found 2 design units, including 1 entities, in source file ../src/pll.vhd
616 Info: Found design unit 1: pll-SYN
617 Info: Found entity 1: pll
618 Info: Found 1 design units, including 1 entities, in source file ../src/demo_top.bdf
619 Info: Found entity 1: demo_top
620 Info: Elaborating entity "demo_top" for the top level hierarchy
621 Info: Elaborating entity "demo" for hierarchy "demo:inst"
622 Info: Elaborating entity "pll" for hierarchy "pll:inst1"
623 Info: Found 1 design units, including 1 entities, in source file /opt/quartus/libraries/megafunctions/altpll.tdf
624 Info: Found entity 1: altpll
625 Info: Elaborating entity "altpll" for hierarchy "pll:inst1|altpll:altpll_component"
626 Info: Elaborated megafunction instantiation "pll:inst1|altpll:altpll_component"
627 Info: Found 1 design units, including 1 entities, in source file /opt/quartus/libraries/megafunctions/lpm_divide.tdf
628 Info: Found entity 1: lpm_divide
629 Info: Elaborated megafunction instantiation "demo:inst|lpm_divide:Mod0"
630 Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_85m.tdf
631 Info: Found entity 1: lpm_divide_85m
632 Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_fkh.tdf
633 Info: Found entity 1: sign_div_unsign_fkh
634 Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_00f.tdf
635 Info: Found entity 1: alt_u_div_00f
636 Info: Found 1 design units, including 1 entities, in source file db/add_sub_lkc.tdf
637 Info: Found entity 1: add_sub_lkc
638 Info: Found 1 design units, including 1 entities, in source file db/add_sub_mkc.tdf
639 Info: Found entity 1: add_sub_mkc
640 Info: Found the following redundant logic cells in design
641 Info: Logic cell "demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[0]~34"
642 Info: Implemented 84 device resources after synthesis - the final resource count might be different
643 Info: Implemented 2 input pins
644 Info: Implemented 8 output pins
645 Info: Implemented 73 logic cells
646 Info: Implemented 1 ClockLock PLLs
647 Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
648 Info: Processing ended: Mon Mar 30 19:52:38 2009
649 Info: Elapsed time: 00:00:03
projects / hwmod.git / blob