demo/quartus/simulation/modelsim/demo.vho

   1 -- Copyright (C) 1991-2007 Altera Corporation
   2 -- Your use of Altera Corporation's design tools, logic functions
   3 -- and other software and tools, and its AMPP partner logic
   4 -- functions, and any output files from any of the foregoing
   5 -- (including device programming or simulation files), and any
   6 -- associated documentation or information are expressly subject
   7 -- to the terms and conditions of the Altera Program License
   8 -- Subscription Agreement, Altera MegaCore Function License
   9 -- Agreement, or other applicable license agreement, including,
  10 -- without limitation, that your use is for the sole purpose of
  11 -- programming logic devices manufactured by Altera and sold by
  12 -- Altera or its authorized distributors.  Please refer to the
  13 -- applicable agreement for further details.
  14
  15 -- VENDOR "Altera"
  16 -- PROGRAM "Quartus II"
  17 -- VERSION "Version 7.0 Build 33 02/05/2007 SJ Full Version"
  18
  19 -- DATE "03/30/2009 19:53:36"
  20
  21 --
  22 -- Device: Altera EP2C35F484C6 Package FBGA484
  23 --
  24
  25 --
  26 -- This VHDL file should be used for ModelSim (VHDL) only
  27 --
  28
  29 LIBRARY IEEE, cycloneii;
  30 USE IEEE.std_logic_1164.all;
  31 USE cycloneii.cycloneii_components.all;
  32
  33 ENTITY  demo_top IS
  34     PORT (
  35         LEDS : OUT std_logic_vector(7 DOWNTO 0);
  36         CLK : IN std_logic;
  37         RESET : IN std_logic
  38         );
  39 END demo_top;
  40
  41 ARCHITECTURE structure OF demo_top IS
  42 SIGNAL gnd : std_logic := '0';
  43 SIGNAL vcc : std_logic := '1';
  44 SIGNAL devoe : std_logic := '1';
  45 SIGNAL devclrn : std_logic := '1';
  46 SIGNAL devpor : std_logic := '1';
  47 SIGNAL ww_devoe : std_logic;
  48 SIGNAL ww_devclrn : std_logic;
  49 SIGNAL ww_devpor : std_logic;
  50 SIGNAL ww_LEDS : std_logic_vector(7 DOWNTO 0);
  51 SIGNAL ww_CLK : std_logic;
  52 SIGNAL ww_RESET : std_logic;
  53 SIGNAL \inst1|altpll_component|pll_INCLK_bus\ : std_logic_vector(1 DOWNTO 0);
  54 SIGNAL \inst1|altpll_component|pll_CLK_bus\ : std_logic_vector(2 DOWNTO 0);
  55 SIGNAL \inst1|altpll_component|_clk0~clkctrl_I_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
  56 SIGNAL \inst1|altpll_component|pll~CLK1\ : std_logic;
  57 SIGNAL \inst1|altpll_component|pll~CLK2\ : std_logic;
  58 SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~20\ : std_logic;
  59 SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~22\ : std_logic;
  60 SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[6]~24\ : std_logic;
  61 SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~22\ : std_logic;
  62 SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[6]~28\ : std_logic;
  63 SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[54]~25\ : std_logic;
  64 SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[53]~26\ : std_logic;
  65 SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[52]~27\ : std_logic;
  66 SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[50]~21\ : std_logic;
  67 SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[49]~22\ : std_logic;
  68 SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[59]~638\ : std_logic;
  69 SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[62]~641\ : std_logic;
  70 SIGNAL \inst|ledstate_next~434\ : std_logic;
  71 SIGNAL \inst|ledstate_next~435\ : std_logic;
  72 SIGNAL \CLK~combout\ : std_logic;
  73 SIGNAL \inst1|altpll_component|_clk0\ : std_logic;
  74 SIGNAL \inst1|altpll_component|_clk0~clkctrl\ : std_logic;
  75 SIGNAL \inst|Add0~101\ : std_logic;
  76 SIGNAL \inst|Add0~103\ : std_logic;
  77 SIGNAL \inst|Add0~105\ : std_logic;
  78 SIGNAL \inst|Add0~107\ : std_logic;
  79 SIGNAL \inst|Add0~108\ : std_logic;
  80 SIGNAL \inst|Add0~104\ : std_logic;
  81 SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~19\ : std_logic;
  82 SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~21\ : std_logic;
  83 SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~23\ : std_logic;
  84 SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[6]~25\ : std_logic;
  85 SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\ : std_logic;
  86 SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[48]~31\ : std_logic;
  87 SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[48]~23\ : std_logic;
  88 SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[1]~18\ : std_logic;
  89 SIGNAL \inst|Add0~96\ : std_logic;
  90 SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[54]~17\ : std_logic;
  91 SIGNAL \inst|Add0~106\ : std_logic;
  92 SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[53]~18\ : std_logic;
  93 SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[52]~19\ : std_logic;
  94 SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~16\ : std_logic;
  95 SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[50]~29\ : std_logic;
  96 SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~21\ : std_logic;
  97 SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~23\ : std_logic;
  98 SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~25\ : std_logic;
  99 SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~27\ : std_logic;
 100 SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[6]~29\ : std_logic;
 101 SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[7]~31\ : std_logic;
 102 SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ : std_logic;
 103 SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[57]~636\ : std_logic;
 104 SIGNAL \RESET~combout\ : std_logic;
 105 SIGNAL \inst|Add0~97\ : std_logic;
 106 SIGNAL \inst|Add0~98\ : std_logic;
 107 SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[49]~30\ : std_logic;
 108 SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~20\ : std_logic;
 109 SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[58]~639\ : std_logic;
 110 SIGNAL \inst|Add0~99\ : std_logic;
 111 SIGNAL \inst|Add0~100\ : std_logic;
 112 SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~17\ : std_logic;
 113 SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~18\ : std_logic;
 114 SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[51]~28\ : std_logic;
 115 SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~24\ : std_logic;
 116 SIGNAL \inst|Add0~102\ : std_logic;
 117 SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[51]~20\ : std_logic;
 118 SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[60]~642\ : std_logic;
 119 SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~26\ : std_logic;
 120 SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[61]~640\ : std_logic;
 121 SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[0]~34\ : std_logic;
 122 SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[56]~637\ : std_logic;
 123 SIGNAL \inst|Equal1~58\ : std_logic;
 124 SIGNAL \inst|Equal1~59\ : std_logic;
 125 SIGNAL \inst|knightlight~1269\ : std_logic;
 126 SIGNAL \inst|knightlight~1270\ : std_logic;
 127 SIGNAL \inst|knightlight~1271\ : std_logic;
 128 SIGNAL \inst|knightlight~1272\ : std_logic;
 129 SIGNAL \inst|knightlight~1273\ : std_logic;
 130 SIGNAL \inst|knightlight~1274\ : std_logic;
 131 SIGNAL \inst|knightlight~1277\ : std_logic;
 132 SIGNAL \inst|knightlight~1275\ : std_logic;
 133 SIGNAL \inst|knightlight~1276\ : std_logic;
 134 SIGNAL \inst|ledstate_next~431\ : std_logic;
 135 SIGNAL \inst|ledstate_next~432\ : std_logic;
 136 SIGNAL \inst|ledstate_next~433\ : std_logic;
 137 SIGNAL \inst|ledstate_next~436\ : std_logic;
 138 SIGNAL \inst|ledstate\ : std_logic;
 139 SIGNAL \inst|knightlight~1267\ : std_logic;
 140 SIGNAL \inst|knightlight~1268\ : std_logic;
 141 SIGNAL \inst|knightlight~1265\ : std_logic;
 142 SIGNAL \inst|knightlight~1266\ : std_logic;
 143 SIGNAL \inst|knightlight~1264\ : std_logic;
 144 SIGNAL \inst|knightlight\ : std_logic_vector(7 DOWNTO 0);
 145 SIGNAL \inst|counter\ : std_logic_vector(6 DOWNTO 0);
 146 SIGNAL \inst|ALT_INV_knightlight\ : std_logic_vector(7 DOWNTO 0);
 147 SIGNAL \ALT_INV_RESET~combout\ : std_logic;
 148
 149 BEGIN
 150
 151 LEDS <= ww_LEDS;
 152 ww_CLK <= CLK;
 153 ww_RESET <= RESET;
 154 ww_devoe <= devoe;
 155 ww_devclrn <= devclrn;
 156 ww_devpor <= devpor;
 157
 158 \inst1|altpll_component|pll_INCLK_bus\ <= (gnd & \CLK~combout\);
 159
 160 \inst1|altpll_component|_clk0\ <= \inst1|altpll_component|pll_CLK_bus\(0);
 161 \inst1|altpll_component|pll~CLK1\ <= \inst1|altpll_component|pll_CLK_bus\(1);
 162 \inst1|altpll_component|pll~CLK2\ <= \inst1|altpll_component|pll_CLK_bus\(2);
 163
 164 \inst1|altpll_component|_clk0~clkctrl_I_INCLK_bus\ <= (gnd & gnd & gnd & \inst1|altpll_component|_clk0\);
 165 \inst|ALT_INV_knightlight\(7) <= NOT \inst|knightlight\(7);
 166 \inst|ALT_INV_knightlight\(6) <= NOT \inst|knightlight\(6);
 167 \inst|ALT_INV_knightlight\(5) <= NOT \inst|knightlight\(5);
 168 \inst|ALT_INV_knightlight\(4) <= NOT \inst|knightlight\(4);
 169 \inst|ALT_INV_knightlight\(3) <= NOT \inst|knightlight\(3);
 170 \inst|ALT_INV_knightlight\(2) <= NOT \inst|knightlight\(2);
 171 \inst|ALT_INV_knightlight\(1) <= NOT \inst|knightlight\(1);
 172 \inst|ALT_INV_knightlight\(0) <= NOT \inst|knightlight\(0);
 173 \ALT_INV_RESET~combout\ <= NOT \RESET~combout\;
 174
 175 \inst|counter[3]~I\ : cycloneii_lcell_ff
 176 PORT MAP (
 177         clk => \inst1|altpll_component|_clk0~clkctrl\,
 178         datain => \inst|Mod0|auto_generated|divider|divider|StageOut[59]~638\,
 179         sclr => \ALT_INV_RESET~combout\,
 180         devclrn => ww_devclrn,
 181         devpor => ww_devpor,
 182         regout => \inst|counter\(3));
 183
 184 \inst|counter[6]~I\ : cycloneii_lcell_ff
 185 PORT MAP (
 186         clk => \inst1|altpll_component|_clk0~clkctrl\,
 187         datain => \inst|Mod0|auto_generated|divider|divider|StageOut[62]~641\,
 188         sclr => \ALT_INV_RESET~combout\,
 189         devclrn => ww_devclrn,
 190         devpor => ww_devpor,
 191         regout => \inst|counter\(6));
 192
 193 \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~20_I\ : cycloneii_lcell_comb
 194 -- Equation(s):
 195 -- \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~20\ = \inst|Add0~104\ & (GND # !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~19\) # !\inst|Add0~104\ &
 196 -- (\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~19\ $ GND)
 197 -- \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~21\ = CARRY(\inst|Add0~104\ # !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~19\)
 198
 199 -- pragma translate_off
 200 GENERIC MAP (
 201         lut_mask => "0011110011001111",
 202         sum_lutc_input => "cin")
 203 -- pragma translate_on
 204 PORT MAP (
 205         datab => \inst|Add0~104\,
 206         datad => VCC,
 207         cin => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~19\,
 208         combout => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~20\,
 209         cout => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~21\);
 210
 211 \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~22_I\ : cycloneii_lcell_comb
 212 -- Equation(s):
 213 -- \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~22\ = \inst|Add0~106\ & !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~21\ # !\inst|Add0~106\ & (\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~21\ #
 214 -- GND)
 215 -- \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~23\ = CARRY(!\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~21\ # !\inst|Add0~106\)
 216
 217 -- pragma translate_off
 218 GENERIC MAP (
 219         lut_mask => "0101101001011111",
 220         sum_lutc_input => "cin")
 221 -- pragma translate_on
 222 PORT MAP (
 223         dataa => \inst|Add0~106\,
 224         datad => VCC,
 225         cin => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~21\,
 226         combout => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~22\,
 227         cout => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~23\);
 228
 229 \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[6]~24_I\ : cycloneii_lcell_comb
 230 -- Equation(s):
 231 -- \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[6]~24\ = \inst|Add0~108\ & (\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~23\ $ GND) # !\inst|Add0~108\ &
 232 -- !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~23\ & VCC
 233 -- \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[6]~25\ = CARRY(\inst|Add0~108\ & !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~23\)
 234
 235 -- pragma translate_off
 236 GENERIC MAP (
 237         lut_mask => "1100001100001100",
 238         sum_lutc_input => "cin")
 239 -- pragma translate_on
 240 PORT MAP (
 241         datab => \inst|Add0~108\,
 242         datad => VCC,
 243         cin => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~23\,
 244         combout => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[6]~24\,
 245         cout => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[6]~25\);
 246
 247 \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~22_I\ : cycloneii_lcell_comb
 248 -- Equation(s):
 249 -- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~22\ = \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~21\ & (\inst|Mod0|auto_generated|divider|divider|StageOut[50]~21\ #
 250 -- \inst|Mod0|auto_generated|divider|divider|StageOut[50]~29\) # !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~21\ & !\inst|Mod0|auto_generated|divider|divider|StageOut[50]~21\ &
 251 -- !\inst|Mod0|auto_generated|divider|divider|StageOut[50]~29\
 252 -- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~23\ = CARRY(!\inst|Mod0|auto_generated|divider|divider|StageOut[50]~21\ & !\inst|Mod0|auto_generated|divider|divider|StageOut[50]~29\ &
 253 -- !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~21\)
 254
 255 -- pragma translate_off
 256 GENERIC MAP (
 257         lut_mask => "1110000100000001",
 258         sum_lutc_input => "cin")
 259 -- pragma translate_on
 260 PORT MAP (
 261         dataa => \inst|Mod0|auto_generated|divider|divider|StageOut[50]~21\,
 262         datab => \inst|Mod0|auto_generated|divider|divider|StageOut[50]~29\,
 263         datad => VCC,
 264         cin => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~21\,
 265         combout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~22\,
 266         cout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~23\);
 267
 268 \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[6]~28_I\ : cycloneii_lcell_comb
 269 -- Equation(s):
 270 -- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[6]~28\ = \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~27\ & (\inst|Mod0|auto_generated|divider|divider|StageOut[53]~26\ #
 271 -- \inst|Mod0|auto_generated|divider|divider|StageOut[53]~18\) # !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~27\ & ((\inst|Mod0|auto_generated|divider|divider|StageOut[53]~26\ #
 272 -- \inst|Mod0|auto_generated|divider|divider|StageOut[53]~18\))
 273 -- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[6]~29\ = CARRY(!\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~27\ & (\inst|Mod0|auto_generated|divider|divider|StageOut[53]~26\ #
 274 -- \inst|Mod0|auto_generated|divider|divider|StageOut[53]~18\))
 275
 276 -- pragma translate_off
 277 GENERIC MAP (
 278         lut_mask => "1110000100001110",
 279         sum_lutc_input => "cin")
 280 -- pragma translate_on
 281 PORT MAP (
 282         dataa => \inst|Mod0|auto_generated|divider|divider|StageOut[53]~26\,
 283         datab => \inst|Mod0|auto_generated|divider|divider|StageOut[53]~18\,
 284         datad => VCC,
 285         cin => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~27\,
 286         combout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[6]~28\,
 287         cout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[6]~29\);
 288
 289 \inst|Mod0|auto_generated|divider|divider|StageOut[54]~25_I\ : cycloneii_lcell_comb
 290 -- Equation(s):
 291 -- \inst|Mod0|auto_generated|divider|divider|StageOut[54]~25\ = !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\ & \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[6]~24\
 292
 293 -- pragma translate_off
 294 GENERIC MAP (
 295         lut_mask => "0000111100000000",
 296         sum_lutc_input => "datac")
 297 -- pragma translate_on
 298 PORT MAP (
 299         datac => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
 300         datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[6]~24\,
 301         combout => \inst|Mod0|auto_generated|divider|divider|StageOut[54]~25\);
 302
 303 \inst|Mod0|auto_generated|divider|divider|StageOut[53]~26_I\ : cycloneii_lcell_comb
 304 -- Equation(s):
 305 -- \inst|Mod0|auto_generated|divider|divider|StageOut[53]~26\ = \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~22\ & !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\
 306
 307 -- pragma translate_off
 308 GENERIC MAP (
 309         lut_mask => "0000000010101010",
 310         sum_lutc_input => "datac")
 311 -- pragma translate_on
 312 PORT MAP (
 313         dataa => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~22\,
 314         datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
 315         combout => \inst|Mod0|auto_generated|divider|divider|StageOut[53]~26\);
 316
 317 \inst|Mod0|auto_generated|divider|divider|StageOut[52]~27_I\ : cycloneii_lcell_comb
 318 -- Equation(s):
 319 -- \inst|Mod0|auto_generated|divider|divider|StageOut[52]~27\ = \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~20\ & !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\
 320
 321 -- pragma translate_off
 322 GENERIC MAP (
 323         lut_mask => "0000000011110000",
 324         sum_lutc_input => "datac")
 325 -- pragma translate_on
 326 PORT MAP (
 327         datac => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~20\,
 328         datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
 329         combout => \inst|Mod0|auto_generated|divider|divider|StageOut[52]~27\);
 330
 331 \inst|Mod0|auto_generated|divider|divider|StageOut[50]~21_I\ : cycloneii_lcell_comb
 332 -- Equation(s):
 333 -- \inst|Mod0|auto_generated|divider|divider|StageOut[50]~21\ = \inst|Add0~100\ & \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\
 334
 335 -- pragma translate_off
 336 GENERIC MAP (
 337         lut_mask => "1111000000000000",
 338         sum_lutc_input => "datac")
 339 -- pragma translate_on
 340 PORT MAP (
 341         datac => \inst|Add0~100\,
 342         datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
 343         combout => \inst|Mod0|auto_generated|divider|divider|StageOut[50]~21\);
 344
 345 \inst|Mod0|auto_generated|divider|divider|StageOut[49]~22_I\ : cycloneii_lcell_comb
 346 -- Equation(s):
 347 -- \inst|Mod0|auto_generated|divider|divider|StageOut[49]~22\ = \inst|Add0~98\ & \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\
 348
 349 -- pragma translate_off
 350 GENERIC MAP (
 351         lut_mask => "1100110000000000",
 352         sum_lutc_input => "datac")
 353 -- pragma translate_on
 354 PORT MAP (
 355         datab => \inst|Add0~98\,
 356         datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
 357         combout => \inst|Mod0|auto_generated|divider|divider|StageOut[49]~22\);
 358
 359 \inst|Mod0|auto_generated|divider|divider|StageOut[59]~638_I\ : cycloneii_lcell_comb
 360 -- Equation(s):
 361 -- \inst|Mod0|auto_generated|divider|divider|StageOut[59]~638\ = \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ & (\inst|Mod0|auto_generated|divider|divider|StageOut[50]~29\ # \inst|Mod0|auto_generated|divider|divider|StageOut[50]~21\)
 362 -- # !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ & (\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~22\)
 363
 364 -- pragma translate_off
 365 GENERIC MAP (
 366         lut_mask => "1110111011110000",
 367         sum_lutc_input => "datac")
 368 -- pragma translate_on
 369 PORT MAP (
 370         dataa => \inst|Mod0|auto_generated|divider|divider|StageOut[50]~29\,
 371         datab => \inst|Mod0|auto_generated|divider|divider|StageOut[50]~21\,
 372         datac => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~22\,
 373         datad => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\,
 374         combout => \inst|Mod0|auto_generated|divider|divider|StageOut[59]~638\);
 375
 376 \inst|Mod0|auto_generated|divider|divider|StageOut[62]~641_I\ : cycloneii_lcell_comb
 377 -- Equation(s):
 378 -- \inst|Mod0|auto_generated|divider|divider|StageOut[62]~641\ = \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ & (\inst|Mod0|auto_generated|divider|divider|StageOut[53]~26\ # \inst|Mod0|auto_generated|divider|divider|StageOut[53]~18\)
 379 -- # !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ & (\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[6]~28\)
 380
 381 -- pragma translate_off
 382 GENERIC MAP (
 383         lut_mask => "1111101011001100",
 384         sum_lutc_input => "datac")
 385 -- pragma translate_on
 386 PORT MAP (
 387         dataa => \inst|Mod0|auto_generated|divider|divider|StageOut[53]~26\,
 388         datab => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[6]~28\,
 389         datac => \inst|Mod0|auto_generated|divider|divider|StageOut[53]~18\,
 390         datad => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\,
 391         combout => \inst|Mod0|auto_generated|divider|divider|StageOut[62]~641\);
 392
 393 \inst|ledstate_next~434_I\ : cycloneii_lcell_comb
 394 -- Equation(s):
 395 -- \inst|ledstate_next~434\ = \inst|knightlight\(3) $ \inst|Equal1~59\
 396
 397 -- pragma translate_off
 398 GENERIC MAP (
 399         lut_mask => "0000111111110000",
 400         sum_lutc_input => "datac")
 401 -- pragma translate_on
 402 PORT MAP (
 403         datac => \inst|knightlight\(3),
 404         datad => \inst|Equal1~59\,
 405         combout => \inst|ledstate_next~434\);
 406
 407 \inst|ledstate_next~435_I\ : cycloneii_lcell_comb
 408 -- Equation(s):
 409 -- \inst|ledstate_next~435\ = \inst|knightlight\(4) & (\inst|ledstate\ # \inst|ledstate_next~434\) # !\inst|knightlight\(4) & (\inst|ledstate_next~434\ & \inst|ledstate\ # !\inst|ledstate_next~434\ & (\inst|knightlight\(7)))
 410
 411 -- pragma translate_off
 412 GENERIC MAP (
 413         lut_mask => "1110101111101000",
 414         sum_lutc_input => "datac")
 415 -- pragma translate_on
 416 PORT MAP (
 417         dataa => \inst|ledstate\,
 418         datab => \inst|knightlight\(4),
 419         datac => \inst|ledstate_next~434\,
 420         datad => \inst|knightlight\(7),
 421         combout => \inst|ledstate_next~435\);
 422
 423 \CLK~I\ : cycloneii_io
 424 -- pragma translate_off
 425 GENERIC MAP (
 426         input_async_reset => "none",
 427         input_power_up => "low",
 428         input_register_mode => "none",
 429         input_sync_reset => "none",
 430         oe_async_reset => "none",
 431         oe_power_up => "low",
 432         oe_register_mode => "none",
 433         oe_sync_reset => "none",
 434         operation_mode => "input",
 435         output_async_reset => "none",
 436         output_power_up => "low",
 437         output_register_mode => "none",
 438         output_sync_reset => "none")
 439 -- pragma translate_on
 440 PORT MAP (
 441         devclrn => ww_devclrn,
 442         devpor => ww_devpor,
 443         devoe => ww_devoe,
 444         oe => GND,
 445         padio => ww_CLK,
 446         combout => \CLK~combout\);
 447
 448 \inst1|altpll_component|pll\ : cycloneii_pll
 449 -- pragma translate_off
 450 GENERIC MAP (
 451         bandwidth => 0,
 452         bandwidth_type => "auto",
 453         c0_high => 4,
 454         c0_initial => 1,
 455         c0_low => 4,
 456         c0_mode => "even",
 457         c0_ph => 0,
 458         c1_mode => "bypass",
 459         c1_ph => 0,
 460         c2_mode => "bypass",
 461         c2_ph => 0,
 462         charge_pump_current => 80,
 463         clk0_counter => "c0",
 464         clk0_divide_by => 1,
 465         clk0_duty_cycle => 50,
 466         clk0_multiply_by => 4,
 467         clk0_phase_shift => "0",
 468         clk1_duty_cycle => 50,
 469         clk1_phase_shift => "0",
 470         clk2_duty_cycle => 50,
 471         clk2_phase_shift => "0",
 472         compensate_clock => "clk0",
 473         gate_lock_counter => 0,
 474         gate_lock_signal => "no",
 475         inclk0_input_frequency => 40000,
 476         inclk1_input_frequency => 40000,
 477         invalid_lock_multiplier => 5,
 478         loop_filter_c => 3,
 479         loop_filter_r => " 2.500000",
 480         m => 32,
 481         m_initial => 1,
 482         m_ph => 0,
 483         n => 1,
 484         operation_mode => "normal",
 485         pfd_max => 100000,
 486         pfd_min => 2484,
 487         pll_compensation_delay => 5370,
 488         self_reset_on_gated_loss_lock => "off",
 489         simulation_type => "timing",
 490         valid_lock_multiplier => 1,
 491         vco_center => 1333,
 492         vco_max => 2000,
 493         vco_min => 1000)
 494 -- pragma translate_on
 495 PORT MAP (
 496         inclk => \inst1|altpll_component|pll_INCLK_bus\,
 497         clk => \inst1|altpll_component|pll_CLK_bus\);
 498
 499 \inst1|altpll_component|_clk0~clkctrl_I\ : cycloneii_clkctrl
 500 -- pragma translate_off
 501 GENERIC MAP (
 502         clock_type => "global clock",
 503         ena_register_mode => "falling edge")
 504 -- pragma translate_on
 505 PORT MAP (
 506         inclk => \inst1|altpll_component|_clk0~clkctrl_I_INCLK_bus\,
 507         devclrn => ww_devclrn,
 508         devpor => ww_devpor,
 509         outclk => \inst1|altpll_component|_clk0~clkctrl\);
 510
 511 \inst|Add0~100_I\ : cycloneii_lcell_comb
 512 -- Equation(s):
 513 -- \inst|Add0~100\ = \inst|counter\(3) & (\inst|Add0~99\ $ GND) # !\inst|counter\(3) & !\inst|Add0~99\ & VCC
 514 -- \inst|Add0~101\ = CARRY(\inst|counter\(3) & !\inst|Add0~99\)
 515
 516 -- pragma translate_off
 517 GENERIC MAP (
 518         lut_mask => "1010010100001010",
 519         sum_lutc_input => "cin")
 520 -- pragma translate_on
 521 PORT MAP (
 522         dataa => \inst|counter\(3),
 523         datad => VCC,
 524         cin => \inst|Add0~99\,
 525         combout => \inst|Add0~100\,
 526         cout => \inst|Add0~101\);
 527
 528 \inst|Add0~102_I\ : cycloneii_lcell_comb
 529 -- Equation(s):
 530 -- \inst|Add0~102\ = \inst|counter\(4) & !\inst|Add0~101\ # !\inst|counter\(4) & (\inst|Add0~101\ # GND)
 531 -- \inst|Add0~103\ = CARRY(!\inst|Add0~101\ # !\inst|counter\(4))
 532
 533 -- pragma translate_off
 534 GENERIC MAP (
 535         lut_mask => "0011110000111111",
 536         sum_lutc_input => "cin")
 537 -- pragma translate_on
 538 PORT MAP (
 539         datab => \inst|counter\(4),
 540         datad => VCC,
 541         cin => \inst|Add0~101\,
 542         combout => \inst|Add0~102\,
 543         cout => \inst|Add0~103\);
 544
 545 \inst|Add0~104_I\ : cycloneii_lcell_comb
 546 -- Equation(s):
 547 -- \inst|Add0~104\ = \inst|counter\(5) & (\inst|Add0~103\ $ GND) # !\inst|counter\(5) & !\inst|Add0~103\ & VCC
 548 -- \inst|Add0~105\ = CARRY(\inst|counter\(5) & !\inst|Add0~103\)
 549
 550 -- pragma translate_off
 551 GENERIC MAP (
 552         lut_mask => "1010010100001010",
 553         sum_lutc_input => "cin")
 554 -- pragma translate_on
 555 PORT MAP (
 556         dataa => \inst|counter\(5),
 557         datad => VCC,
 558         cin => \inst|Add0~103\,
 559         combout => \inst|Add0~104\,
 560         cout => \inst|Add0~105\);
 561
 562 \inst|Add0~106_I\ : cycloneii_lcell_comb
 563 -- Equation(s):
 564 -- \inst|Add0~106\ = \inst|counter\(6) & !\inst|Add0~105\ # !\inst|counter\(6) & (\inst|Add0~105\ # GND)
 565 -- \inst|Add0~107\ = CARRY(!\inst|Add0~105\ # !\inst|counter\(6))
 566
 567 -- pragma translate_off
 568 GENERIC MAP (
 569         lut_mask => "0101101001011111",
 570         sum_lutc_input => "cin")
 571 -- pragma translate_on
 572 PORT MAP (
 573         dataa => \inst|counter\(6),
 574         datad => VCC,
 575         cin => \inst|Add0~105\,
 576         combout => \inst|Add0~106\,
 577         cout => \inst|Add0~107\);
 578
 579 \inst|Add0~108_I\ : cycloneii_lcell_comb
 580 -- Equation(s):
 581 -- \inst|Add0~108\ = !\inst|Add0~107\
 582
 583 -- pragma translate_off
 584 GENERIC MAP (
 585         lut_mask => "0000111100001111",
 586         sum_lutc_input => "cin")
 587 -- pragma translate_on
 588 PORT MAP (
 589         cin => \inst|Add0~107\,
 590         combout => \inst|Add0~108\);
 591
 592 \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~18_I\ : cycloneii_lcell_comb
 593 -- Equation(s):
 594 -- \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~18\ = \inst|Add0~102\ & \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~17\ & VCC # !\inst|Add0~102\ &
 595 -- !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~17\
 596 -- \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~19\ = CARRY(!\inst|Add0~102\ & !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~17\)
 597
 598 -- pragma translate_off
 599 GENERIC MAP (
 600         lut_mask => "1010010100000101",
 601         sum_lutc_input => "cin")
 602 -- pragma translate_on
 603 PORT MAP (
 604         dataa => \inst|Add0~102\,
 605         datad => VCC,
 606         cin => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~17\,
 607         combout => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~18\,
 608         cout => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~19\);
 609
 610 \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26_I\ : cycloneii_lcell_comb
 611 -- Equation(s):
 612 -- \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\ = !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[6]~25\
 613
 614 -- pragma translate_off
 615 GENERIC MAP (
 616         lut_mask => "0000111100001111",
 617         sum_lutc_input => "cin")
 618 -- pragma translate_on
 619 PORT MAP (
 620         cin => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[6]~25\,
 621         combout => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\);
 622
 623 \inst|Mod0|auto_generated|divider|divider|StageOut[48]~31_I\ : cycloneii_lcell_comb
 624 -- Equation(s):
 625 -- \inst|Mod0|auto_generated|divider|divider|StageOut[48]~31\ = \inst|Add0~96\ & !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\
 626
 627 -- pragma translate_off
 628 GENERIC MAP (
 629         lut_mask => "0000000010101010",
 630         sum_lutc_input => "datac")
 631 -- pragma translate_on
 632 PORT MAP (
 633         dataa => \inst|Add0~96\,
 634         datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
 635         combout => \inst|Mod0|auto_generated|divider|divider|StageOut[48]~31\);
 636
 637 \inst|Mod0|auto_generated|divider|divider|StageOut[48]~23_I\ : cycloneii_lcell_comb
 638 -- Equation(s):
 639 -- \inst|Mod0|auto_generated|divider|divider|StageOut[48]~23\ = \inst|Add0~96\ & \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\
 640
 641 -- pragma translate_off
 642 GENERIC MAP (
 643         lut_mask => "1010101000000000",
 644         sum_lutc_input => "datac")
 645 -- pragma translate_on
 646 PORT MAP (
 647         dataa => \inst|Add0~96\,
 648         datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
 649         combout => \inst|Mod0|auto_generated|divider|divider|StageOut[48]~23\);
 650
 651 \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[1]~18_I\ : cycloneii_lcell_comb
 652 -- Equation(s):
 653 -- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[1]~18\ = \inst|Mod0|auto_generated|divider|divider|StageOut[48]~31\ # \inst|Mod0|auto_generated|divider|divider|StageOut[48]~23\
 654
 655 -- pragma translate_off
 656 GENERIC MAP (
 657         lut_mask => "1111111111110000",
 658         sum_lutc_input => "datac")
 659 -- pragma translate_on
 660 PORT MAP (
 661         datac => \inst|Mod0|auto_generated|divider|divider|StageOut[48]~31\,
 662         datad => \inst|Mod0|auto_generated|divider|divider|StageOut[48]~23\,
 663         combout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[1]~18\);
 664
 665 \inst|Add0~96_I\ : cycloneii_lcell_comb
 666 -- Equation(s):
 667 -- \inst|Add0~96\ = \inst|counter\(0) & (\inst|counter\(1) $ VCC) # !\inst|counter\(0) & \inst|counter\(1) & VCC
 668 -- \inst|Add0~97\ = CARRY(\inst|counter\(0) & \inst|counter\(1))
 669
 670 -- pragma translate_off
 671 GENERIC MAP (
 672         lut_mask => "0110011010001000",
 673         sum_lutc_input => "datac")
 674 -- pragma translate_on
 675 PORT MAP (
 676         dataa => \inst|counter\(0),
 677         datab => \inst|counter\(1),
 678         datad => VCC,
 679         combout => \inst|Add0~96\,
 680         cout => \inst|Add0~97\);
 681
 682 \inst|Mod0|auto_generated|divider|divider|StageOut[54]~17_I\ : cycloneii_lcell_comb
 683 -- Equation(s):
 684 -- \inst|Mod0|auto_generated|divider|divider|StageOut[54]~17\ = \inst|Add0~108\ & \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\
 685
 686 -- pragma translate_off
 687 GENERIC MAP (
 688         lut_mask => "1100110000000000",
 689         sum_lutc_input => "datac")
 690 -- pragma translate_on
 691 PORT MAP (
 692         datab => \inst|Add0~108\,
 693         datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
 694         combout => \inst|Mod0|auto_generated|divider|divider|StageOut[54]~17\);
 695
 696 \inst|Mod0|auto_generated|divider|divider|StageOut[53]~18_I\ : cycloneii_lcell_comb
 697 -- Equation(s):
 698 -- \inst|Mod0|auto_generated|divider|divider|StageOut[53]~18\ = \inst|Add0~106\ & \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\
 699
 700 -- pragma translate_off
 701 GENERIC MAP (
 702         lut_mask => "1100110000000000",
 703         sum_lutc_input => "datac")
 704 -- pragma translate_on
 705 PORT MAP (
 706         datab => \inst|Add0~106\,
 707         datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
 708         combout => \inst|Mod0|auto_generated|divider|divider|StageOut[53]~18\);
 709
 710 \inst|Mod0|auto_generated|divider|divider|StageOut[52]~19_I\ : cycloneii_lcell_comb
 711 -- Equation(s):
 712 -- \inst|Mod0|auto_generated|divider|divider|StageOut[52]~19\ = \inst|Add0~104\ & \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\
 713
 714 -- pragma translate_off
 715 GENERIC MAP (
 716         lut_mask => "1100110000000000",
 717         sum_lutc_input => "datac")
 718 -- pragma translate_on
 719 PORT MAP (
 720         datab => \inst|Add0~104\,
 721         datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
 722         combout => \inst|Mod0|auto_generated|divider|divider|StageOut[52]~19\);
 723
 724 \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~16_I\ : cycloneii_lcell_comb
 725 -- Equation(s):
 726 -- \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~16\ = \inst|Add0~100\ $ VCC
 727 -- \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~17\ = CARRY(\inst|Add0~100\)
 728
 729 -- pragma translate_off
 730 GENERIC MAP (
 731         lut_mask => "0011001111001100",
 732         sum_lutc_input => "datac")
 733 -- pragma translate_on
 734 PORT MAP (
 735         datab => \inst|Add0~100\,
 736         datad => VCC,
 737         combout => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~16\,
 738         cout => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~17\);
 739
 740 \inst|Mod0|auto_generated|divider|divider|StageOut[50]~29_I\ : cycloneii_lcell_comb
 741 -- Equation(s):
 742 -- \inst|Mod0|auto_generated|divider|divider|StageOut[50]~29\ = \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~16\ & !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\
 743
 744 -- pragma translate_off
 745 GENERIC MAP (
 746         lut_mask => "0000000011110000",
 747         sum_lutc_input => "datac")
 748 -- pragma translate_on
 749 PORT MAP (
 750         datac => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~16\,
 751         datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
 752         combout => \inst|Mod0|auto_generated|divider|divider|StageOut[50]~29\);
 753
 754 \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~20_I\ : cycloneii_lcell_comb
 755 -- Equation(s):
 756 -- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~20\ = (\inst|Mod0|auto_generated|divider|divider|StageOut[49]~22\ # \inst|Mod0|auto_generated|divider|divider|StageOut[49]~30\)
 757 -- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~21\ = CARRY(\inst|Mod0|auto_generated|divider|divider|StageOut[49]~22\ # \inst|Mod0|auto_generated|divider|divider|StageOut[49]~30\)
 758
 759 -- pragma translate_off
 760 GENERIC MAP (
 761         lut_mask => "0001000111101110",
 762         sum_lutc_input => "datac")
 763 -- pragma translate_on
 764 PORT MAP (
 765         dataa => \inst|Mod0|auto_generated|divider|divider|StageOut[49]~22\,
 766         datab => \inst|Mod0|auto_generated|divider|divider|StageOut[49]~30\,
 767         datad => VCC,
 768         combout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~20\,
 769         cout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~21\);
 770
 771 \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~24_I\ : cycloneii_lcell_comb
 772 -- Equation(s):
 773 -- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~24\ = \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~23\ & ((\inst|Mod0|auto_generated|divider|divider|StageOut[51]~20\ #
 774 -- \inst|Mod0|auto_generated|divider|divider|StageOut[51]~28\)) # !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~23\ & (\inst|Mod0|auto_generated|divider|divider|StageOut[51]~20\ #
 775 -- \inst|Mod0|auto_generated|divider|divider|StageOut[51]~28\ # GND)
 776 -- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~25\ = CARRY(\inst|Mod0|auto_generated|divider|divider|StageOut[51]~20\ # \inst|Mod0|auto_generated|divider|divider|StageOut[51]~28\ #
 777 -- !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~23\)
 778
 779 -- pragma translate_off
 780 GENERIC MAP (
 781         lut_mask => "0001111011101111",
 782         sum_lutc_input => "cin")
 783 -- pragma translate_on
 784 PORT MAP (
 785         dataa => \inst|Mod0|auto_generated|divider|divider|StageOut[51]~20\,
 786         datab => \inst|Mod0|auto_generated|divider|divider|StageOut[51]~28\,
 787         datad => VCC,
 788         cin => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~23\,
 789         combout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~24\,
 790         cout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~25\);
 791
 792 \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~26_I\ : cycloneii_lcell_comb
 793 -- Equation(s):
 794 -- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~26\ = \inst|Mod0|auto_generated|divider|divider|StageOut[52]~27\ & (!\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~25\) #
 795 -- !\inst|Mod0|auto_generated|divider|divider|StageOut[52]~27\ & (\inst|Mod0|auto_generated|divider|divider|StageOut[52]~19\ & !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~25\ #
 796 -- !\inst|Mod0|auto_generated|divider|divider|StageOut[52]~19\ & (\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~25\ # GND))
 797 -- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~27\ = CARRY(!\inst|Mod0|auto_generated|divider|divider|StageOut[52]~27\ & !\inst|Mod0|auto_generated|divider|divider|StageOut[52]~19\ #
 798 -- !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~25\)
 799
 800 -- pragma translate_off
 801 GENERIC MAP (
 802         lut_mask => "0001111000011111",
 803         sum_lutc_input => "cin")
 804 -- pragma translate_on
 805 PORT MAP (
 806         dataa => \inst|Mod0|auto_generated|divider|divider|StageOut[52]~27\,
 807         datab => \inst|Mod0|auto_generated|divider|divider|StageOut[52]~19\,
 808         datad => VCC,
 809         cin => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~25\,
 810         combout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~26\,
 811         cout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~27\);
 812
 813 \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[7]~31_I\ : cycloneii_lcell_comb
 814 -- Equation(s):
 815 -- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[7]~31\ = CARRY(!\inst|Mod0|auto_generated|divider|divider|StageOut[54]~25\ & !\inst|Mod0|auto_generated|divider|divider|StageOut[54]~17\ &
 816 -- !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[6]~29\)
 817
 818 -- pragma translate_off
 819 GENERIC MAP (
 820         lut_mask => "0000000000000001",
 821         sum_lutc_input => "cin")
 822 -- pragma translate_on
 823 PORT MAP (
 824         dataa => \inst|Mod0|auto_generated|divider|divider|StageOut[54]~25\,
 825         datab => \inst|Mod0|auto_generated|divider|divider|StageOut[54]~17\,
 826         datad => VCC,
 827         cin => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[6]~29\,
 828         cout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[7]~31\);
 829
 830 \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32_I\ : cycloneii_lcell_comb
 831 -- Equation(s):
 832 -- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ = \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[7]~31\
 833
 834 -- pragma translate_off
 835 GENERIC MAP (
 836         lut_mask => "1111000011110000",
 837         sum_lutc_input => "cin")
 838 -- pragma translate_on
 839 PORT MAP (
 840         cin => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[7]~31\,
 841         combout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\);
 842
 843 \inst|Mod0|auto_generated|divider|divider|StageOut[57]~636_I\ : cycloneii_lcell_comb
 844 -- Equation(s):
 845 -- \inst|Mod0|auto_generated|divider|divider|StageOut[57]~636\ = \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ & (\inst|Add0~96\) # !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ &
 846 -- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[1]~18\
 847
 848 -- pragma translate_off
 849 GENERIC MAP (
 850         lut_mask => "1111000011001100",
 851         sum_lutc_input => "datac")
 852 -- pragma translate_on
 853 PORT MAP (
 854         datab => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[1]~18\,
 855         datac => \inst|Add0~96\,
 856         datad => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\,
 857         combout => \inst|Mod0|auto_generated|divider|divider|StageOut[57]~636\);
 858
 859 \RESET~I\ : cycloneii_io
 860 -- pragma translate_off
 861 GENERIC MAP (
 862         input_async_reset => "none",
 863         input_power_up => "low",
 864         input_register_mode => "none",
 865         input_sync_reset => "none",
 866         oe_async_reset => "none",
 867         oe_power_up => "low",
 868         oe_register_mode => "none",
 869         oe_sync_reset => "none",
 870         operation_mode => "input",
 871         output_async_reset => "none",
 872         output_power_up => "low",
 873         output_register_mode => "none",
 874         output_sync_reset => "none")
 875 -- pragma translate_on
 876 PORT MAP (
 877         devclrn => ww_devclrn,
 878         devpor => ww_devpor,
 879         devoe => ww_devoe,
 880         oe => GND,
 881         padio => ww_RESET,
 882         combout => \RESET~combout\);
 883
 884 \inst|counter[1]~I\ : cycloneii_lcell_ff
 885 PORT MAP (
 886         clk => \inst1|altpll_component|_clk0~clkctrl\,
 887         datain => \inst|Mod0|auto_generated|divider|divider|StageOut[57]~636\,
 888         sclr => \ALT_INV_RESET~combout\,
 889         devclrn => ww_devclrn,
 890         devpor => ww_devpor,
 891         regout => \inst|counter\(1));
 892
 893 \inst|Add0~98_I\ : cycloneii_lcell_comb
 894 -- Equation(s):
 895 -- \inst|Add0~98\ = \inst|counter\(2) & !\inst|Add0~97\ # !\inst|counter\(2) & (\inst|Add0~97\ # GND)
 896 -- \inst|Add0~99\ = CARRY(!\inst|Add0~97\ # !\inst|counter\(2))
 897
 898 -- pragma translate_off
 899 GENERIC MAP (
 900         lut_mask => "0011110000111111",
 901         sum_lutc_input => "cin")
 902 -- pragma translate_on
 903 PORT MAP (
 904         datab => \inst|counter\(2),
 905         datad => VCC,
 906         cin => \inst|Add0~97\,
 907         combout => \inst|Add0~98\,
 908         cout => \inst|Add0~99\);
 909
 910 \inst|Mod0|auto_generated|divider|divider|StageOut[49]~30_I\ : cycloneii_lcell_comb
 911 -- Equation(s):
 912 -- \inst|Mod0|auto_generated|divider|divider|StageOut[49]~30\ = \inst|Add0~98\ & !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\
 913
 914 -- pragma translate_off
 915 GENERIC MAP (
 916         lut_mask => "0000000011001100",
 917         sum_lutc_input => "datac")
 918 -- pragma translate_on
 919 PORT MAP (
 920         datab => \inst|Add0~98\,
 921         datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
 922         combout => \inst|Mod0|auto_generated|divider|divider|StageOut[49]~30\);
 923
 924 \inst|Mod0|auto_generated|divider|divider|StageOut[58]~639_I\ : cycloneii_lcell_comb
 925 -- Equation(s):
 926 -- \inst|Mod0|auto_generated|divider|divider|StageOut[58]~639\ = \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ & \inst|Add0~98\ # !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ &
 927 -- (\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~20\)
 928
 929 -- pragma translate_off
 930 GENERIC MAP (
 931         lut_mask => "1010101011110000",
 932         sum_lutc_input => "datac")
 933 -- pragma translate_on
 934 PORT MAP (
 935         dataa => \inst|Add0~98\,
 936         datac => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~20\,
 937         datad => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\,
 938         combout => \inst|Mod0|auto_generated|divider|divider|StageOut[58]~639\);
 939
 940 \inst|counter[2]~I\ : cycloneii_lcell_ff
 941 PORT MAP (
 942         clk => \inst1|altpll_component|_clk0~clkctrl\,
 943         datain => \inst|Mod0|auto_generated|divider|divider|StageOut[58]~639\,
 944         sclr => \ALT_INV_RESET~combout\,
 945         devclrn => ww_devclrn,
 946         devpor => ww_devpor,
 947         regout => \inst|counter\(2));
 948
 949 \inst|Mod0|auto_generated|divider|divider|StageOut[51]~28_I\ : cycloneii_lcell_comb
 950 -- Equation(s):
 951 -- \inst|Mod0|auto_generated|divider|divider|StageOut[51]~28\ = \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~18\ & !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\
 952
 953 -- pragma translate_off
 954 GENERIC MAP (
 955         lut_mask => "0000000011110000",
 956         sum_lutc_input => "datac")
 957 -- pragma translate_on
 958 PORT MAP (
 959         datac => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~18\,
 960         datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
 961         combout => \inst|Mod0|auto_generated|divider|divider|StageOut[51]~28\);
 962
 963 \inst|Mod0|auto_generated|divider|divider|StageOut[51]~20_I\ : cycloneii_lcell_comb
 964 -- Equation(s):
 965 -- \inst|Mod0|auto_generated|divider|divider|StageOut[51]~20\ = \inst|Add0~102\ & \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\
 966
 967 -- pragma translate_off
 968 GENERIC MAP (
 969         lut_mask => "1111000000000000",
 970         sum_lutc_input => "datac")
 971 -- pragma translate_on
 972 PORT MAP (
 973         datac => \inst|Add0~102\,
 974         datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
 975         combout => \inst|Mod0|auto_generated|divider|divider|StageOut[51]~20\);
 976
 977 \inst|Mod0|auto_generated|divider|divider|StageOut[60]~642_I\ : cycloneii_lcell_comb
 978 -- Equation(s):
 979 -- \inst|Mod0|auto_generated|divider|divider|StageOut[60]~642\ = \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ & (\inst|Mod0|auto_generated|divider|divider|StageOut[51]~28\ # \inst|Mod0|auto_generated|divider|divider|StageOut[51]~20\)
 980 -- # !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ & (\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~24\)
 981
 982 -- pragma translate_off
 983 GENERIC MAP (
 984         lut_mask => "1111101011001100",
 985         sum_lutc_input => "datac")
 986 -- pragma translate_on
 987 PORT MAP (
 988         dataa => \inst|Mod0|auto_generated|divider|divider|StageOut[51]~28\,
 989         datab => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~24\,
 990         datac => \inst|Mod0|auto_generated|divider|divider|StageOut[51]~20\,
 991         datad => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\,
 992         combout => \inst|Mod0|auto_generated|divider|divider|StageOut[60]~642\);
 993
 994 \inst|counter[4]~I\ : cycloneii_lcell_ff
 995 PORT MAP (
 996         clk => \inst1|altpll_component|_clk0~clkctrl\,
 997         datain => \inst|Mod0|auto_generated|divider|divider|StageOut[60]~642\,
 998         sclr => \ALT_INV_RESET~combout\,
 999         devclrn => ww_devclrn,
1000         devpor => ww_devpor,
1001         regout => \inst|counter\(4));
1002
1003 \inst|Mod0|auto_generated|divider|divider|StageOut[61]~640_I\ : cycloneii_lcell_comb
1004 -- Equation(s):
1005 -- \inst|Mod0|auto_generated|divider|divider|StageOut[61]~640\ = \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ & (\inst|Mod0|auto_generated|divider|divider|StageOut[52]~27\ # \inst|Mod0|auto_generated|divider|divider|StageOut[52]~19\)
1006 -- # !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ & (\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~26\)
1007
1008 -- pragma translate_off
1009 GENERIC MAP (
1010         lut_mask => "1110111011110000",
1011         sum_lutc_input => "datac")
1012 -- pragma translate_on
1013 PORT MAP (
1014         dataa => \inst|Mod0|auto_generated|divider|divider|StageOut[52]~27\,
1015         datab => \inst|Mod0|auto_generated|divider|divider|StageOut[52]~19\,
1016         datac => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~26\,
1017         datad => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\,
1018         combout => \inst|Mod0|auto_generated|divider|divider|StageOut[61]~640\);
1019
1020 \inst|counter[5]~I\ : cycloneii_lcell_ff
1021 PORT MAP (
1022         clk => \inst1|altpll_component|_clk0~clkctrl\,
1023         datain => \inst|Mod0|auto_generated|divider|divider|StageOut[61]~640\,
1024         sclr => \ALT_INV_RESET~combout\,
1025         devclrn => ww_devclrn,
1026         devpor => ww_devpor,
1027         regout => \inst|counter\(5));
1028
1029 \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[0]~34_I\ : cycloneii_lcell_comb
1030 -- Equation(s):
1031 -- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[0]~34\ = !\inst|counter\(0)
1032
1033 -- pragma translate_off
1034 GENERIC MAP (
1035         lut_mask => "0000000011111111",
1036         sum_lutc_input => "datac")
1037 -- pragma translate_on
1038 PORT MAP (
1039         datad => \inst|counter\(0),
1040         combout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[0]~34\);
1041
1042 \inst|Mod0|auto_generated|divider|divider|StageOut[56]~637_I\ : cycloneii_lcell_comb
1043 -- Equation(s):
1044 -- \inst|Mod0|auto_generated|divider|divider|StageOut[56]~637\ = \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ & (!\inst|counter\(0)) # !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ &
1045 -- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[0]~34\
1046
1047 -- pragma translate_off
1048 GENERIC MAP (
1049         lut_mask => "0000111111001100",
1050         sum_lutc_input => "datac")
1051 -- pragma translate_on
1052 PORT MAP (
1053         datab => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[0]~34\,
1054         datac => \inst|counter\(0),
1055         datad => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\,
1056         combout => \inst|Mod0|auto_generated|divider|divider|StageOut[56]~637\);
1057
1058 \inst|counter[0]~I\ : cycloneii_lcell_ff
1059 PORT MAP (
1060         clk => \inst1|altpll_component|_clk0~clkctrl\,
1061         datain => \inst|Mod0|auto_generated|divider|divider|StageOut[56]~637\,
1062         sclr => \ALT_INV_RESET~combout\,
1063         devclrn => ww_devclrn,
1064         devpor => ww_devpor,
1065         regout => \inst|counter\(0));
1066
1067 \inst|Equal1~58_I\ : cycloneii_lcell_comb
1068 -- Equation(s):
1069 -- \inst|Equal1~58\ = !\inst|counter\(3) & \inst|counter\(0) & \inst|counter\(1) & !\inst|counter\(2)
1070
1071 -- pragma translate_off
1072 GENERIC MAP (
1073         lut_mask => "0000000001000000",
1074         sum_lutc_input => "datac")
1075 -- pragma translate_on
1076 PORT MAP (
1077         dataa => \inst|counter\(3),
1078         datab => \inst|counter\(0),
1079         datac => \inst|counter\(1),
1080         datad => \inst|counter\(2),
1081         combout => \inst|Equal1~58\);
1082
1083 \inst|Equal1~59_I\ : cycloneii_lcell_comb
1084 -- Equation(s):
1085 -- \inst|Equal1~59\ = \inst|counter\(6) & !\inst|counter\(4) & \inst|counter\(5) & \inst|Equal1~58\
1086
1087 -- pragma translate_off
1088 GENERIC MAP (
1089         lut_mask => "0010000000000000",
1090         sum_lutc_input => "datac")
1091 -- pragma translate_on
1092 PORT MAP (
1093         dataa => \inst|counter\(6),
1094         datab => \inst|counter\(4),
1095         datac => \inst|counter\(5),
1096         datad => \inst|Equal1~58\,
1097         combout => \inst|Equal1~59\);
1098
1099 \inst|knightlight~1269_I\ : cycloneii_lcell_comb
1100 -- Equation(s):
1101 -- \inst|knightlight~1269\ = \inst|ledstate\ & (\inst|knightlight\(5)) # !\inst|ledstate\ & \inst|knightlight\(3)
1102
1103 -- pragma translate_off
1104 GENERIC MAP (
1105         lut_mask => "1111101001010000",
1106         sum_lutc_input => "datac")
1107 -- pragma translate_on
1108 PORT MAP (
1109         dataa => \inst|ledstate\,
1110         datac => \inst|knightlight\(3),
1111         datad => \inst|knightlight\(5),
1112         combout => \inst|knightlight~1269\);
1113
1114 \inst|knightlight~1270_I\ : cycloneii_lcell_comb
1115 -- Equation(s):
1116 -- \inst|knightlight~1270\ = \inst|Equal1~59\ & \inst|knightlight~1269\ # !\inst|Equal1~59\ & (\inst|knightlight\(4))
1117
1118 -- pragma translate_off
1119 GENERIC MAP (
1120         lut_mask => "1100110011110000",
1121         sum_lutc_input => "datac")
1122 -- pragma translate_on
1123 PORT MAP (
1124         datab => \inst|knightlight~1269\,
1125         datac => \inst|knightlight\(4),
1126         datad => \inst|Equal1~59\,
1127         combout => \inst|knightlight~1270\);
1128
1129 \inst|knightlight[4]~I\ : cycloneii_lcell_ff
1130 PORT MAP (
1131         clk => \inst1|altpll_component|_clk0~clkctrl\,
1132         datain => \inst|knightlight~1270\,
1133         sclr => \ALT_INV_RESET~combout\,
1134         devclrn => ww_devclrn,
1135         devpor => ww_devpor,
1136         regout => \inst|knightlight\(4));
1137
1138 \inst|knightlight~1271_I\ : cycloneii_lcell_comb
1139 -- Equation(s):
1140 -- \inst|knightlight~1271\ = \inst|ledstate\ & (\inst|knightlight\(4)) # !\inst|ledstate\ & \inst|knightlight\(2)
1141
1142 -- pragma translate_off
1143 GENERIC MAP (
1144         lut_mask => "1111110000001100",
1145         sum_lutc_input => "datac")
1146 -- pragma translate_on
1147 PORT MAP (
1148         datab => \inst|knightlight\(2),
1149         datac => \inst|ledstate\,
1150         datad => \inst|knightlight\(4),
1151         combout => \inst|knightlight~1271\);
1152
1153 \inst|knightlight~1272_I\ : cycloneii_lcell_comb
1154 -- Equation(s):
1155 -- \inst|knightlight~1272\ = \inst|Equal1~59\ & (\inst|knightlight~1271\) # !\inst|Equal1~59\ & \inst|knightlight\(3)
1156
1157 -- pragma translate_off
1158 GENERIC MAP (
1159         lut_mask => "1111110000110000",
1160         sum_lutc_input => "datac")
1161 -- pragma translate_on
1162 PORT MAP (
1163         datab => \inst|Equal1~59\,
1164         datac => \inst|knightlight\(3),
1165         datad => \inst|knightlight~1271\,
1166         combout => \inst|knightlight~1272\);
1167
1168 \inst|knightlight[3]~I\ : cycloneii_lcell_ff
1169 PORT MAP (
1170         clk => \inst1|altpll_component|_clk0~clkctrl\,
1171         datain => \inst|knightlight~1272\,
1172         sclr => \ALT_INV_RESET~combout\,
1173         devclrn => ww_devclrn,
1174         devpor => ww_devpor,
1175         regout => \inst|knightlight\(3));
1176
1177 \inst|knightlight~1273_I\ : cycloneii_lcell_comb
1178 -- Equation(s):
1179 -- \inst|knightlight~1273\ = \inst|ledstate\ & (\inst|knightlight\(3)) # !\inst|ledstate\ & \inst|knightlight\(1)
1180
1181 -- pragma translate_off
1182 GENERIC MAP (
1183         lut_mask => "1100101011001010",
1184         sum_lutc_input => "datac")
1185 -- pragma translate_on
1186 PORT MAP (
1187         dataa => \inst|knightlight\(1),
1188         datab => \inst|knightlight\(3),
1189         datac => \inst|ledstate\,
1190         combout => \inst|knightlight~1273\);
1191
1192 \inst|knightlight~1274_I\ : cycloneii_lcell_comb
1193 -- Equation(s):
1194 -- \inst|knightlight~1274\ = \inst|Equal1~59\ & (\inst|knightlight~1273\) # !\inst|Equal1~59\ & \inst|knightlight\(2)
1195
1196 -- pragma translate_off
1197 GENERIC MAP (
1198         lut_mask => "1111101001010000",
1199         sum_lutc_input => "datac")
1200 -- pragma translate_on
1201 PORT MAP (
1202         dataa => \inst|Equal1~59\,
1203         datac => \inst|knightlight\(2),
1204         datad => \inst|knightlight~1273\,
1205         combout => \inst|knightlight~1274\);
1206
1207 \inst|knightlight[2]~I\ : cycloneii_lcell_ff
1208 PORT MAP (
1209         clk => \inst1|altpll_component|_clk0~clkctrl\,
1210         datain => \inst|knightlight~1274\,
1211         sdata => VCC,
1212         sload => \ALT_INV_RESET~combout\,
1213         devclrn => ww_devclrn,
1214         devpor => ww_devpor,
1215         regout => \inst|knightlight\(2));
1216
1217 \inst|knightlight~1277_I\ : cycloneii_lcell_comb
1218 -- Equation(s):
1219 -- \inst|knightlight~1277\ = \inst|Equal1~59\ & \inst|ledstate\ & (\inst|knightlight\(1)) # !\inst|Equal1~59\ & (\inst|knightlight\(0))
1220
1221 -- pragma translate_off
1222 GENERIC MAP (
1223         lut_mask => "1101100001010000",
1224         sum_lutc_input => "datac")
1225 -- pragma translate_on
1226 PORT MAP (
1227         dataa => \inst|Equal1~59\,
1228         datab => \inst|ledstate\,
1229         datac => \inst|knightlight\(0),
1230         datad => \inst|knightlight\(1),
1231         combout => \inst|knightlight~1277\);
1232
1233 \inst|knightlight[0]~I\ : cycloneii_lcell_ff
1234 PORT MAP (
1235         clk => \inst1|altpll_component|_clk0~clkctrl\,
1236         datain => \inst|knightlight~1277\,
1237         sdata => VCC,
1238         sload => \ALT_INV_RESET~combout\,
1239         devclrn => ww_devclrn,
1240         devpor => ww_devpor,
1241         regout => \inst|knightlight\(0));
1242
1243 \inst|knightlight~1275_I\ : cycloneii_lcell_comb
1244 -- Equation(s):
1245 -- \inst|knightlight~1275\ = \inst|ledstate\ & \inst|knightlight\(2) # !\inst|ledstate\ & (\inst|knightlight\(0))
1246
1247 -- pragma translate_off
1248 GENERIC MAP (
1249         lut_mask => "1100111111000000",
1250         sum_lutc_input => "datac")
1251 -- pragma translate_on
1252 PORT MAP (
1253         datab => \inst|knightlight\(2),
1254         datac => \inst|ledstate\,
1255         datad => \inst|knightlight\(0),
1256         combout => \inst|knightlight~1275\);
1257
1258 \inst|knightlight~1276_I\ : cycloneii_lcell_comb
1259 -- Equation(s):
1260 -- \inst|knightlight~1276\ = \inst|Equal1~59\ & (\inst|knightlight~1275\) # !\inst|Equal1~59\ & \inst|knightlight\(1)
1261
1262 -- pragma translate_off
1263 GENERIC MAP (
1264         lut_mask => "1111101001010000",
1265         sum_lutc_input => "datac")
1266 -- pragma translate_on
1267 PORT MAP (
1268         dataa => \inst|Equal1~59\,
1269         datac => \inst|knightlight\(1),
1270         datad => \inst|knightlight~1275\,
1271         combout => \inst|knightlight~1276\);
1272
1273 \inst|knightlight[1]~I\ : cycloneii_lcell_ff
1274 PORT MAP (
1275         clk => \inst1|altpll_component|_clk0~clkctrl\,
1276         datain => \inst|knightlight~1276\,
1277         sdata => VCC,
1278         sload => \ALT_INV_RESET~combout\,
1279         devclrn => ww_devclrn,
1280         devpor => ww_devpor,
1281         regout => \inst|knightlight\(1));
1282
1283 \inst|ledstate_next~431_I\ : cycloneii_lcell_comb
1284 -- Equation(s):
1285 -- \inst|ledstate_next~431\ = \inst|knightlight\(2) & (\inst|knightlight\(6) # \inst|knightlight\(5)) # !\inst|knightlight\(2) & \inst|knightlight\(6) & \inst|knightlight\(5)
1286
1287 -- pragma translate_off
1288 GENERIC MAP (
1289         lut_mask => "1111110011000000",
1290         sum_lutc_input => "datac")
1291 -- pragma translate_on
1292 PORT MAP (
1293         datab => \inst|knightlight\(2),
1294         datac => \inst|knightlight\(6),
1295         datad => \inst|knightlight\(5),
1296         combout => \inst|ledstate_next~431\);
1297
1298 \inst|ledstate_next~432_I\ : cycloneii_lcell_comb
1299 -- Equation(s):
1300 -- \inst|ledstate_next~432\ = \inst|ledstate\ & \inst|knightlight\(2) & \inst|knightlight\(1) & !\inst|ledstate_next~431\ # !\inst|ledstate\ & !\inst|knightlight\(2) & !\inst|knightlight\(1) & \inst|ledstate_next~431\
1301
1302 -- pragma translate_off
1303 GENERIC MAP (
1304         lut_mask => "0000000110000000",
1305         sum_lutc_input => "datac")
1306 -- pragma translate_on
1307 PORT MAP (
1308         dataa => \inst|ledstate\,
1309         datab => \inst|knightlight\(2),
1310         datac => \inst|knightlight\(1),
1311         datad => \inst|ledstate_next~431\,
1312         combout => \inst|ledstate_next~432\);
1313
1314 \inst|ledstate_next~433_I\ : cycloneii_lcell_comb
1315 -- Equation(s):
1316 -- \inst|ledstate_next~433\ = \inst|knightlight\(0) # \inst|knightlight\(3)
1317
1318 -- pragma translate_off
1319 GENERIC MAP (
1320         lut_mask => "1111111111001100",
1321         sum_lutc_input => "datac")
1322 -- pragma translate_on
1323 PORT MAP (
1324         datab => \inst|knightlight\(0),
1325         datad => \inst|knightlight\(3),
1326         combout => \inst|ledstate_next~433\);
1327
1328 \inst|ledstate_next~436_I\ : cycloneii_lcell_comb
1329 -- Equation(s):
1330 -- \inst|ledstate_next~436\ = \inst|ledstate_next~435\ & (\inst|ledstate\ # \inst|ledstate_next~432\ & !\inst|ledstate_next~433\) # !\inst|ledstate_next~435\ & \inst|ledstate\ & (!\inst|ledstate_next~433\ # !\inst|ledstate_next~432\)
1331
1332 -- pragma translate_off
1333 GENERIC MAP (
1334         lut_mask => "1011000011111000",
1335         sum_lutc_input => "datac")
1336 -- pragma translate_on
1337 PORT MAP (
1338         dataa => \inst|ledstate_next~435\,
1339         datab => \inst|ledstate_next~432\,
1340         datac => \inst|ledstate\,
1341         datad => \inst|ledstate_next~433\,
1342         combout => \inst|ledstate_next~436\);
1343
1344 \inst|ledstate~I\ : cycloneii_lcell_ff
1345 PORT MAP (
1346         clk => \inst1|altpll_component|_clk0~clkctrl\,
1347         datain => \inst|ledstate_next~436\,
1348         sclr => \ALT_INV_RESET~combout\,
1349         devclrn => ww_devclrn,
1350         devpor => ww_devpor,
1351         regout => \inst|ledstate\);
1352
1353 \inst|knightlight~1267_I\ : cycloneii_lcell_comb
1354 -- Equation(s):
1355 -- \inst|knightlight~1267\ = \inst|ledstate\ & \inst|knightlight\(6) # !\inst|ledstate\ & (\inst|knightlight\(4))
1356
1357 -- pragma translate_off
1358 GENERIC MAP (
1359         lut_mask => "1100111111000000",
1360         sum_lutc_input => "datac")
1361 -- pragma translate_on
1362 PORT MAP (
1363         datab => \inst|knightlight\(6),
1364         datac => \inst|ledstate\,
1365         datad => \inst|knightlight\(4),
1366         combout => \inst|knightlight~1267\);
1367
1368 \inst|knightlight~1268_I\ : cycloneii_lcell_comb
1369 -- Equation(s):
1370 -- \inst|knightlight~1268\ = \inst|Equal1~59\ & (\inst|knightlight~1267\) # !\inst|Equal1~59\ & \inst|knightlight\(5)
1371
1372 -- pragma translate_off
1373 GENERIC MAP (
1374         lut_mask => "1111110000110000",
1375         sum_lutc_input => "datac")
1376 -- pragma translate_on
1377 PORT MAP (
1378         datab => \inst|Equal1~59\,
1379         datac => \inst|knightlight\(5),
1380         datad => \inst|knightlight~1267\,
1381         combout => \inst|knightlight~1268\);
1382
1383 \inst|knightlight[5]~I\ : cycloneii_lcell_ff
1384 PORT MAP (
1385         clk => \inst1|altpll_component|_clk0~clkctrl\,
1386         datain => \inst|knightlight~1268\,
1387         sclr => \ALT_INV_RESET~combout\,
1388         devclrn => ww_devclrn,
1389         devpor => ww_devpor,
1390         regout => \inst|knightlight\(5));
1391
1392 \inst|knightlight~1265_I\ : cycloneii_lcell_comb
1393 -- Equation(s):
1394 -- \inst|knightlight~1265\ = \inst|ledstate\ & (\inst|knightlight\(7)) # !\inst|ledstate\ & \inst|knightlight\(5)
1395
1396 -- pragma translate_off
1397 GENERIC MAP (
1398         lut_mask => "1111110000001100",
1399         sum_lutc_input => "datac")
1400 -- pragma translate_on
1401 PORT MAP (
1402         datab => \inst|knightlight\(5),
1403         datac => \inst|ledstate\,
1404         datad => \inst|knightlight\(7),
1405         combout => \inst|knightlight~1265\);
1406
1407 \inst|knightlight~1266_I\ : cycloneii_lcell_comb
1408 -- Equation(s):
1409 -- \inst|knightlight~1266\ = \inst|Equal1~59\ & (\inst|knightlight~1265\) # !\inst|Equal1~59\ & \inst|knightlight\(6)
1410
1411 -- pragma translate_off
1412 GENERIC MAP (
1413         lut_mask => "1111110000110000",
1414         sum_lutc_input => "datac")
1415 -- pragma translate_on
1416 PORT MAP (
1417         datab => \inst|Equal1~59\,
1418         datac => \inst|knightlight\(6),
1419         datad => \inst|knightlight~1265\,
1420         combout => \inst|knightlight~1266\);
1421
1422 \inst|knightlight[6]~I\ : cycloneii_lcell_ff
1423 PORT MAP (
1424         clk => \inst1|altpll_component|_clk0~clkctrl\,
1425         datain => \inst|knightlight~1266\,
1426         sclr => \ALT_INV_RESET~combout\,
1427         devclrn => ww_devclrn,
1428         devpor => ww_devpor,
1429         regout => \inst|knightlight\(6));
1430
1431 \inst|knightlight~1264_I\ : cycloneii_lcell_comb
1432 -- Equation(s):
1433 -- \inst|knightlight~1264\ = \inst|Equal1~59\ & !\inst|ledstate\ & \inst|knightlight\(6) # !\inst|Equal1~59\ & (\inst|knightlight\(7))
1434
1435 -- pragma translate_off
1436 GENERIC MAP (
1437         lut_mask => "0100010011110000",
1438         sum_lutc_input => "datac")
1439 -- pragma translate_on
1440 PORT MAP (
1441         dataa => \inst|ledstate\,
1442         datab => \inst|knightlight\(6),
1443         datac => \inst|knightlight\(7),
1444         datad => \inst|Equal1~59\,
1445         combout => \inst|knightlight~1264\);
1446
1447 \inst|knightlight[7]~I\ : cycloneii_lcell_ff
1448 PORT MAP (
1449         clk => \inst1|altpll_component|_clk0~clkctrl\,
1450         datain => \inst|knightlight~1264\,
1451         sclr => \ALT_INV_RESET~combout\,
1452         devclrn => ww_devclrn,
1453         devpor => ww_devpor,
1454         regout => \inst|knightlight\(7));
1455
1456 \LEDS[7]~I\ : cycloneii_io
1457 -- pragma translate_off
1458 GENERIC MAP (
1459         input_async_reset => "none",
1460         input_power_up => "low",
1461         input_register_mode => "none",
1462         input_sync_reset => "none",
1463         oe_async_reset => "none",
1464         oe_power_up => "low",
1465         oe_register_mode => "none",
1466         oe_sync_reset => "none",
1467         operation_mode => "output",
1468         output_async_reset => "none",
1469         output_power_up => "low",
1470         output_register_mode => "none",
1471         output_sync_reset => "none")
1472 -- pragma translate_on
1473 PORT MAP (
1474         datain => \inst|ALT_INV_knightlight\(7),
1475         devclrn => ww_devclrn,
1476         devpor => ww_devpor,
1477         devoe => ww_devoe,
1478         oe => VCC,
1479         padio => ww_LEDS(7));
1480
1481 \LEDS[6]~I\ : cycloneii_io
1482 -- pragma translate_off
1483 GENERIC MAP (
1484         input_async_reset => "none",
1485         input_power_up => "low",
1486         input_register_mode => "none",
1487         input_sync_reset => "none",
1488         oe_async_reset => "none",
1489         oe_power_up => "low",
1490         oe_register_mode => "none",
1491         oe_sync_reset => "none",
1492         operation_mode => "output",
1493         output_async_reset => "none",
1494         output_power_up => "low",
1495         output_register_mode => "none",
1496         output_sync_reset => "none")
1497 -- pragma translate_on
1498 PORT MAP (
1499         datain => \inst|ALT_INV_knightlight\(6),
1500         devclrn => ww_devclrn,
1501         devpor => ww_devpor,
1502         devoe => ww_devoe,
1503         oe => VCC,
1504         padio => ww_LEDS(6));
1505
1506 \LEDS[5]~I\ : cycloneii_io
1507 -- pragma translate_off
1508 GENERIC MAP (
1509         input_async_reset => "none",
1510         input_power_up => "low",
1511         input_register_mode => "none",
1512         input_sync_reset => "none",
1513         oe_async_reset => "none",
1514         oe_power_up => "low",
1515         oe_register_mode => "none",
1516         oe_sync_reset => "none",
1517         operation_mode => "output",
1518         output_async_reset => "none",
1519         output_power_up => "low",
1520         output_register_mode => "none",
1521         output_sync_reset => "none")
1522 -- pragma translate_on
1523 PORT MAP (
1524         datain => \inst|ALT_INV_knightlight\(5),
1525         devclrn => ww_devclrn,
1526         devpor => ww_devpor,
1527         devoe => ww_devoe,
1528         oe => VCC,
1529         padio => ww_LEDS(5));
1530
1531 \LEDS[4]~I\ : cycloneii_io
1532 -- pragma translate_off
1533 GENERIC MAP (
1534         input_async_reset => "none",
1535         input_power_up => "low",
1536         input_register_mode => "none",
1537         input_sync_reset => "none",
1538         oe_async_reset => "none",
1539         oe_power_up => "low",
1540         oe_register_mode => "none",
1541         oe_sync_reset => "none",
1542         operation_mode => "output",
1543         output_async_reset => "none",
1544         output_power_up => "low",
1545         output_register_mode => "none",
1546         output_sync_reset => "none")
1547 -- pragma translate_on
1548 PORT MAP (
1549         datain => \inst|ALT_INV_knightlight\(4),
1550         devclrn => ww_devclrn,
1551         devpor => ww_devpor,
1552         devoe => ww_devoe,
1553         oe => VCC,
1554         padio => ww_LEDS(4));
1555
1556 \LEDS[3]~I\ : cycloneii_io
1557 -- pragma translate_off
1558 GENERIC MAP (
1559         input_async_reset => "none",
1560         input_power_up => "low",
1561         input_register_mode => "none",
1562         input_sync_reset => "none",
1563         oe_async_reset => "none",
1564         oe_power_up => "low",
1565         oe_register_mode => "none",
1566         oe_sync_reset => "none",
1567         operation_mode => "output",
1568         output_async_reset => "none",
1569         output_power_up => "low",
1570         output_register_mode => "none",
1571         output_sync_reset => "none")
1572 -- pragma translate_on
1573 PORT MAP (
1574         datain => \inst|ALT_INV_knightlight\(3),
1575         devclrn => ww_devclrn,
1576         devpor => ww_devpor,
1577         devoe => ww_devoe,
1578         oe => VCC,
1579         padio => ww_LEDS(3));
1580
1581 \LEDS[2]~I\ : cycloneii_io
1582 -- pragma translate_off
1583 GENERIC MAP (
1584         input_async_reset => "none",
1585         input_power_up => "low",
1586         input_register_mode => "none",
1587         input_sync_reset => "none",
1588         oe_async_reset => "none",
1589         oe_power_up => "low",
1590         oe_register_mode => "none",
1591         oe_sync_reset => "none",
1592         operation_mode => "output",
1593         output_async_reset => "none",
1594         output_power_up => "low",
1595         output_register_mode => "none",
1596         output_sync_reset => "none")
1597 -- pragma translate_on
1598 PORT MAP (
1599         datain => \inst|ALT_INV_knightlight\(2),
1600         devclrn => ww_devclrn,
1601         devpor => ww_devpor,
1602         devoe => ww_devoe,
1603         oe => VCC,
1604         padio => ww_LEDS(2));
1605
1606 \LEDS[1]~I\ : cycloneii_io
1607 -- pragma translate_off
1608 GENERIC MAP (
1609         input_async_reset => "none",
1610         input_power_up => "low",
1611         input_register_mode => "none",
1612         input_sync_reset => "none",
1613         oe_async_reset => "none",
1614         oe_power_up => "low",
1615         oe_register_mode => "none",
1616         oe_sync_reset => "none",
1617         operation_mode => "output",
1618         output_async_reset => "none",
1619         output_power_up => "low",
1620         output_register_mode => "none",
1621         output_sync_reset => "none")
1622 -- pragma translate_on
1623 PORT MAP (
1624         datain => \inst|ALT_INV_knightlight\(1),
1625         devclrn => ww_devclrn,
1626         devpor => ww_devpor,
1627         devoe => ww_devoe,
1628         oe => VCC,
1629         padio => ww_LEDS(1));
1630
1631 \LEDS[0]~I\ : cycloneii_io
1632 -- pragma translate_off
1633 GENERIC MAP (
1634         input_async_reset => "none",
1635         input_power_up => "low",
1636         input_register_mode => "none",
1637         input_sync_reset => "none",
1638         oe_async_reset => "none",
1639         oe_power_up => "low",
1640         oe_register_mode => "none",
1641         oe_sync_reset => "none",
1642         operation_mode => "output",
1643         output_async_reset => "none",
1644         output_power_up => "low",
1645         output_register_mode => "none",
1646         output_sync_reset => "none")
1647 -- pragma translate_on
1648 PORT MAP (
1649         datain => \inst|ALT_INV_knightlight\(0),
1650         devclrn => ww_devclrn,
1651         devpor => ww_devpor,
1652         devoe => ww_devoe,
1653         oe => VCC,
1654         padio => ww_LEDS(0));
1655 END structure;
1656
1657