demo/quartus/db/demo.hier_info

   1 |demo_top
   2 LEDS[0] <= demo:inst.leds[0]
   3 LEDS[1] <= demo:inst.leds[1]
   4 LEDS[2] <= demo:inst.leds[2]
   5 LEDS[3] <= demo:inst.leds[3]
   6 LEDS[4] <= demo:inst.leds[4]
   7 LEDS[5] <= demo:inst.leds[5]
   8 LEDS[6] <= demo:inst.leds[6]
   9 LEDS[7] <= demo:inst.leds[7]
  10 CLK => pll:inst1.inclk0
  11 RESET => demo:inst.reset
  12
  13
  14 |demo_top|demo:inst
  15 clk => counter[0].CLK
  16 clk => counter[1].CLK
  17 clk => counter[2].CLK
  18 clk => counter[3].CLK
  19 clk => counter[4].CLK
  20 clk => counter[5].CLK
  21 clk => counter[6].CLK
  22 clk => ledstate.CLK
  23 clk => knightlight[0].CLK
  24 clk => knightlight[1].CLK
  25 clk => knightlight[2].CLK
  26 clk => knightlight[3].CLK
  27 clk => knightlight[4].CLK
  28 clk => knightlight[5].CLK
  29 clk => knightlight[6].CLK
  30 clk => knightlight[7].CLK
  31 reset => knightlight~0.OUTPUTSELECT
  32 reset => knightlight~1.OUTPUTSELECT
  33 reset => knightlight~2.OUTPUTSELECT
  34 reset => knightlight~3.OUTPUTSELECT
  35 reset => knightlight~4.OUTPUTSELECT
  36 reset => knightlight~5.OUTPUTSELECT
  37 reset => knightlight~6.OUTPUTSELECT
  38 reset => knightlight~7.OUTPUTSELECT
  39 reset => ledstate~0.OUTPUTSELECT
  40 reset => counter~0.OUTPUTSELECT
  41 reset => counter~1.OUTPUTSELECT
  42 reset => counter~2.OUTPUTSELECT
  43 reset => counter~3.OUTPUTSELECT
  44 reset => counter~4.OUTPUTSELECT
  45 reset => counter~5.OUTPUTSELECT
  46 reset => counter~6.OUTPUTSELECT
  47 leds[0] <= knightlight[0].DB_MAX_OUTPUT_PORT_TYPE
  48 leds[1] <= knightlight[1].DB_MAX_OUTPUT_PORT_TYPE
  49 leds[2] <= knightlight[2].DB_MAX_OUTPUT_PORT_TYPE
  50 leds[3] <= knightlight[3].DB_MAX_OUTPUT_PORT_TYPE
  51 leds[4] <= knightlight[4].DB_MAX_OUTPUT_PORT_TYPE
  52 leds[5] <= knightlight[5].DB_MAX_OUTPUT_PORT_TYPE
  53 leds[6] <= knightlight[6].DB_MAX_OUTPUT_PORT_TYPE
  54 leds[7] <= knightlight[7].DB_MAX_OUTPUT_PORT_TYPE
  55
  56
  57 |demo_top|pll:inst1
  58 inclk0 => altpll:altpll_component.inclk[0]
  59 c0 <= altpll:altpll_component.clk[0]
  60
  61
  62 |demo_top|pll:inst1|altpll:altpll_component
  63 inclk[0] => pll.CLK
  64 inclk[1] => ~NO_FANOUT~
  65 fbin => ~NO_FANOUT~
  66 pllena => ~NO_FANOUT~
  67 clkswitch => ~NO_FANOUT~
  68 areset => ~NO_FANOUT~
  69 pfdena => ~NO_FANOUT~
  70 clkena[0] => ~NO_FANOUT~
  71 clkena[1] => ~NO_FANOUT~
  72 clkena[2] => ~NO_FANOUT~
  73 clkena[3] => ~NO_FANOUT~
  74 clkena[4] => ~NO_FANOUT~
  75 clkena[5] => ~NO_FANOUT~
  76 extclkena[0] => ~NO_FANOUT~
  77 extclkena[1] => ~NO_FANOUT~
  78 extclkena[2] => ~NO_FANOUT~
  79 extclkena[3] => ~NO_FANOUT~
  80 scanclk => ~NO_FANOUT~
  81 scanclkena => ~NO_FANOUT~
  82 scanaclr => ~NO_FANOUT~
  83 scanread => ~NO_FANOUT~
  84 scanwrite => ~NO_FANOUT~
  85 scandata => ~NO_FANOUT~
  86 phasecounterselect[0] => ~NO_FANOUT~
  87 phasecounterselect[1] => ~NO_FANOUT~
  88 phasecounterselect[2] => ~NO_FANOUT~
  89 phasecounterselect[3] => ~NO_FANOUT~
  90 phaseupdown => ~NO_FANOUT~
  91 phasestep => ~NO_FANOUT~
  92 configupdate => ~NO_FANOUT~
  93 clk[0] <= clk[0]~0.DB_MAX_OUTPUT_PORT_TYPE
  94 clk[1] <= <GND>
  95 clk[2] <= <GND>
  96 clk[3] <= <GND>
  97 clk[4] <= <GND>
  98 clk[5] <= <GND>
  99 extclk[0] <= <GND>
 100 extclk[1] <= <GND>
 101 extclk[2] <= <GND>
 102 extclk[3] <= <GND>
 103 clkbad[0] <= <GND>
 104 clkbad[1] <= <GND>
 105 enable1 <= <GND>
 106 enable0 <= <GND>
 107 activeclock <= <GND>
 108 clkloss <= <GND>
 109 locked <= <GND>
 110 scandataout <= <GND>
 111 scandone <= <GND>
 112 sclkout0 <= <GND>
 113 sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE
 114 phasedone <= <GND>
 115 vcooverrange <= <GND>
 116 vcounderrange <= <GND>
 117 fbout <= <GND>
 118
 119