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[hwmod.git] / demo / quartus / db / demo.tan.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 30 19:53:31 2009 " "Info: Processing started: Mon Mar 30 19:53:31 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off demo -c demo --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off demo -c demo --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTAN_USE_ENABLE_CLOCK_LATENCY_FOR_PLL" "" "Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" {  } {  } 0 0 "Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" 0 0}
{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "pll:inst1\|altpll:altpll_component\|_clk0 register demo:inst\|counter\[3\] register demo:inst\|counter\[1\] 3.604 ns " "Info: Slack time is 3.604 ns for clock \"pll:inst1\|altpll:altpll_component\|_clk0\" between source register \"demo:inst\|counter\[3\]\" and destination register \"demo:inst\|counter\[1\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "156.35 MHz 6.396 ns " "Info: Fmax is 156.35 MHz (period= 6.396 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "9.786 ns + Largest register register " "Info: + Largest register to register requirement is 9.786 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "10.000 ns + " "Info: + Setup relationship between source and destination is 10.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 7.622 ns " "Info: + Latch edge is 7.622 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination pll:inst1\|altpll:altpll_component\|_clk0 10.000 ns -2.378 ns  50 " "Info: Clock period of Destination clock \"pll:inst1\|altpll:altpll_component\|_clk0\" is 10.000 ns with  offset of -2.378 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.378 ns " "Info: - Launch edge is -2.378 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source pll:inst1\|altpll:altpll_component\|_clk0 10.000 ns -2.378 ns  50 " "Info: Clock period of Source clock \"pll:inst1\|altpll:altpll_component\|_clk0\" is 10.000 ns with  offset of -2.378 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll:inst1\|altpll:altpll_component\|_clk0 destination 2.650 ns + Shortest register " "Info: + Shortest clock path from clock \"pll:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.650 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll:inst1\|altpll:altpll_component\|_clk0'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "" { pll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns pll:inst1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'pll:inst1\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "1.091 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.022 ns) + CELL(0.537 ns) 2.650 ns demo:inst\|counter\[1\] 3 REG LCFF_X55_Y31_N1 3 " "Info: 3: + IC(1.022 ns) + CELL(0.537 ns) = 2.650 ns; Loc. = LCFF_X55_Y31_N1; Fanout = 3; REG Node = 'demo:inst\|counter\[1\]'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "1.559 ns" { pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[1] } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.26 % ) " "Info: Total cell delay = 0.537 ns ( 20.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.113 ns ( 79.74 % ) " "Info: Total interconnect delay = 2.113 ns ( 79.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[1] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[1] } { 0.000ns 1.091ns 1.022ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll:inst1\|altpll:altpll_component\|_clk0 source 2.650 ns - Longest register " "Info: - Longest clock path from clock \"pll:inst1\|altpll:altpll_component\|_clk0\" to source register is 2.650 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll:inst1\|altpll:altpll_component\|_clk0'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "" { pll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns pll:inst1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'pll:inst1\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "1.091 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.022 ns) + CELL(0.537 ns) 2.650 ns demo:inst\|counter\[3\] 3 REG LCFF_X57_Y31_N31 3 " "Info: 3: + IC(1.022 ns) + CELL(0.537 ns) = 2.650 ns; Loc. = LCFF_X57_Y31_N31; Fanout = 3; REG Node = 'demo:inst\|counter\[3\]'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "1.559 ns" { pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[3] } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.26 % ) " "Info: Total cell delay = 0.537 ns ( 20.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.113 ns ( 79.74 % ) " "Info: Total interconnect delay = 2.113 ns ( 79.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[3] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[3] } { 0.000ns 1.091ns 1.022ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[1] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[1] } { 0.000ns 1.091ns 1.022ns } { 0.000ns 0.000ns 0.537ns } "" } } { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[3] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[3] } { 0.000ns 1.091ns 1.022ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" {  } { { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 82 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns - " "Info: - Micro setup delay of destination is -0.036 ns" {  } { { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 82 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[1] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[1] } { 0.000ns 1.091ns 1.022ns } { 0.000ns 0.000ns 0.537ns } "" } } { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[3] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[3] } { 0.000ns 1.091ns 1.022ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.182 ns - Longest register register " "Info: - Longest register to register delay is 6.182 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns demo:inst\|counter\[3\] 1 REG LCFF_X57_Y31_N31 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X57_Y31_N31; Fanout = 3; REG Node = 'demo:inst\|counter\[3\]'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "" { demo:inst|counter[3] } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.741 ns) + CELL(0.414 ns) 1.155 ns demo:inst\|Add0~101 2 COMB LCCOMB_X55_Y31_N18 2 " "Info: 2: + IC(0.741 ns) + CELL(0.414 ns) = 1.155 ns; Loc. = LCCOMB_X55_Y31_N18; Fanout = 2; COMB Node = 'demo:inst\|Add0~101'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "1.155 ns" { demo:inst|counter[3] demo:inst|Add0~101 } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 86 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 1.565 ns demo:inst\|Add0~102 3 COMB LCCOMB_X55_Y31_N20 3 " "Info: 3: + IC(0.000 ns) + CELL(0.410 ns) = 1.565 ns; Loc. = LCCOMB_X55_Y31_N20; Fanout = 3; COMB Node = 'demo:inst\|Add0~102'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.410 ns" { demo:inst|Add0~101 demo:inst|Add0~102 } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 86 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.277 ns) + CELL(0.414 ns) 2.256 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[3\]~19 4 COMB LCCOMB_X55_Y31_N4 2 " "Info: 4: + IC(0.277 ns) + CELL(0.414 ns) = 2.256 ns; Loc. = LCCOMB_X55_Y31_N4; Fanout = 2; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[3\]~19'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.691 ns" { demo:inst|Add0~102 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[3]~19 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 57 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.327 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[4\]~21 5 COMB LCCOMB_X55_Y31_N6 2 " "Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 2.327 ns; Loc. = LCCOMB_X55_Y31_N6; Fanout = 2; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[4\]~21'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.071 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[3]~19 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[4]~21 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 57 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.398 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[5\]~23 6 COMB LCCOMB_X55_Y31_N8 2 " "Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 2.398 ns; Loc. = LCCOMB_X55_Y31_N8; Fanout = 2; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[5\]~23'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.071 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[4]~21 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[5]~23 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 57 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.469 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[6\]~25 7 COMB LCCOMB_X55_Y31_N10 1 " "Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 2.469 ns; Loc. = LCCOMB_X55_Y31_N10; Fanout = 1; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[6\]~25'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.071 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[5]~23 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[6]~25 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 57 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 2.879 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[7\]~26 8 COMB LCCOMB_X55_Y31_N12 14 " "Info: 8: + IC(0.000 ns) + CELL(0.410 ns) = 2.879 ns; Loc. = LCCOMB_X55_Y31_N12; Fanout = 14; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_6_result_int\[7\]~26'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.410 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[6]~25 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[7]~26 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 57 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.705 ns) + CELL(0.150 ns) 3.734 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|StageOut\[49\]~22 9 COMB LCCOMB_X57_Y31_N10 2 " "Info: 9: + IC(0.705 ns) + CELL(0.150 ns) = 3.734 ns; Loc. = LCCOMB_X57_Y31_N10; Fanout = 2; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|StageOut\[49\]~22'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.855 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[7]~26 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[49]~22 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 79 10 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.263 ns) + CELL(0.504 ns) 4.501 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[2\]~21 10 COMB LCCOMB_X57_Y31_N14 2 " "Info: 10: + IC(0.263 ns) + CELL(0.504 ns) = 4.501 ns; Loc. = LCCOMB_X57_Y31_N14; Fanout = 2; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[2\]~21'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.767 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[49]~22 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[2]~21 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 62 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.572 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[3\]~23 11 COMB LCCOMB_X57_Y31_N16 2 " "Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 4.572 ns; Loc. = LCCOMB_X57_Y31_N16; Fanout = 2; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[3\]~23'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.071 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[2]~21 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[3]~23 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 62 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.643 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[4\]~25 12 COMB LCCOMB_X57_Y31_N18 2 " "Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 4.643 ns; Loc. = LCCOMB_X57_Y31_N18; Fanout = 2; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[4\]~25'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.071 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[3]~23 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[4]~25 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 62 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.714 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[5\]~27 13 COMB LCCOMB_X57_Y31_N20 2 " "Info: 13: + IC(0.000 ns) + CELL(0.071 ns) = 4.714 ns; Loc. = LCCOMB_X57_Y31_N20; Fanout = 2; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[5\]~27'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.071 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[4]~25 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[5]~27 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 62 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.785 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[6\]~29 14 COMB LCCOMB_X57_Y31_N22 1 " "Info: 14: + IC(0.000 ns) + CELL(0.071 ns) = 4.785 ns; Loc. = LCCOMB_X57_Y31_N22; Fanout = 1; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[6\]~29'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.071 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[5]~27 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[6]~29 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 62 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.856 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[7\]~31 15 COMB LCCOMB_X57_Y31_N24 1 " "Info: 15: + IC(0.000 ns) + CELL(0.071 ns) = 4.856 ns; Loc. = LCCOMB_X57_Y31_N24; Fanout = 1; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[7\]~31'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.071 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[6]~29 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[7]~31 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 62 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 5.266 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[8\]~32 16 COMB LCCOMB_X57_Y31_N26 7 " "Info: 16: + IC(0.000 ns) + CELL(0.410 ns) = 5.266 ns; Loc. = LCCOMB_X57_Y31_N26; Fanout = 7; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[8\]~32'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.410 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[7]~31 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[8]~32 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 62 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.682 ns) + CELL(0.150 ns) 6.098 ns demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|StageOut\[57\]~636 17 COMB LCCOMB_X55_Y31_N0 1 " "Info: 17: + IC(0.682 ns) + CELL(0.150 ns) = 6.098 ns; Loc. = LCCOMB_X55_Y31_N0; Fanout = 1; COMB Node = 'demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|StageOut\[57\]~636'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.832 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[8]~32 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[57]~636 } "NODE_NAME" } } { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 79 10 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 6.182 ns demo:inst\|counter\[1\] 18 REG LCFF_X55_Y31_N1 3 " "Info: 18: + IC(0.000 ns) + CELL(0.084 ns) = 6.182 ns; Loc. = LCFF_X55_Y31_N1; Fanout = 3; REG Node = 'demo:inst\|counter\[1\]'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.084 ns" { demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[57]~636 demo:inst|counter[1] } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.514 ns ( 56.84 % ) " "Info: Total cell delay = 3.514 ns ( 56.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.668 ns ( 43.16 % ) " "Info: Total interconnect delay = 2.668 ns ( 43.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "6.182 ns" { demo:inst|counter[3] demo:inst|Add0~101 demo:inst|Add0~102 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[3]~19 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[4]~21 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[5]~23 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[6]~25 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[7]~26 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[49]~22 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[2]~21 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[3]~23 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[4]~25 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[5]~27 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[6]~29 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[7]~31 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[8]~32 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[57]~636 demo:inst|counter[1] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "6.182 ns" { demo:inst|counter[3] demo:inst|Add0~101 demo:inst|Add0~102 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[3]~19 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[4]~21 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[5]~23 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[6]~25 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[7]~26 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[49]~22 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[2]~21 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[3]~23 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[4]~25 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[5]~27 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[6]~29 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[7]~31 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[8]~32 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[57]~636 demo:inst|counter[1] } { 0.000ns 0.741ns 0.000ns 0.277ns 0.000ns 0.000ns 0.000ns 0.000ns 0.705ns 0.263ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.682ns 0.000ns } { 0.000ns 0.414ns 0.410ns 0.414ns 0.071ns 0.071ns 0.071ns 0.410ns 0.150ns 0.504ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.410ns 0.150ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[1] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[1] } { 0.000ns 1.091ns 1.022ns } { 0.000ns 0.000ns 0.537ns } "" } } { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[3] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[3] } { 0.000ns 1.091ns 1.022ns } { 0.000ns 0.000ns 0.537ns } "" } } { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "6.182 ns" { demo:inst|counter[3] demo:inst|Add0~101 demo:inst|Add0~102 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[3]~19 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[4]~21 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[5]~23 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[6]~25 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[7]~26 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[49]~22 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[2]~21 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[3]~23 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[4]~25 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[5]~27 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[6]~29 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[7]~31 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[8]~32 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[57]~636 demo:inst|counter[1] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "6.182 ns" { demo:inst|counter[3] demo:inst|Add0~101 demo:inst|Add0~102 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[3]~19 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[4]~21 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[5]~23 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[6]~25 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_6_result_int[7]~26 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[49]~22 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[2]~21 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[3]~23 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[4]~25 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[5]~27 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[6]~29 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[7]~31 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|add_sub_7_result_int[8]~32 demo:inst|lpm_divide:Mod0|lpm_divide_85m:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_00f:divider|StageOut[57]~636 demo:inst|counter[1] } { 0.000ns 0.741ns 0.000ns 0.277ns 0.000ns 0.000ns 0.000ns 0.000ns 0.705ns 0.263ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.682ns 0.000ns } { 0.000ns 0.414ns 0.410ns 0.414ns 0.071ns 0.071ns 0.071ns 0.410ns 0.150ns 0.504ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.410ns 0.150ns 0.084ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "CLK " "Info: No valid register-to-register data paths exist for clock \"CLK\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "pll:inst1\|altpll:altpll_component\|_clk0 register demo:inst\|knightlight\[5\] register demo:inst\|knightlight\[5\] 391 ps " "Info: Minimum slack time is 391 ps for clock \"pll:inst1\|altpll:altpll_component\|_clk0\" between source register \"demo:inst\|knightlight\[5\]\" and destination register \"demo:inst\|knightlight\[5\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.407 ns + Shortest register register " "Info: + Shortest register to register delay is 0.407 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns demo:inst\|knightlight\[5\] 1 REG LCFF_X33_Y27_N29 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X33_Y27_N29; Fanout = 5; REG Node = 'demo:inst\|knightlight\[5\]'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "" { demo:inst|knightlight[5] } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.323 ns) 0.323 ns demo:inst\|knightlight~1268 2 COMB LCCOMB_X33_Y27_N28 1 " "Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X33_Y27_N28; Fanout = 1; COMB Node = 'demo:inst\|knightlight~1268'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.323 ns" { demo:inst|knightlight[5] demo:inst|knightlight~1268 } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.407 ns demo:inst\|knightlight\[5\] 3 REG LCFF_X33_Y27_N29 5 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X33_Y27_N29; Fanout = 5; REG Node = 'demo:inst\|knightlight\[5\]'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.084 ns" { demo:inst|knightlight~1268 demo:inst|knightlight[5] } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.407 ns ( 100.00 % ) " "Info: Total cell delay = 0.407 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.407 ns" { demo:inst|knightlight[5] demo:inst|knightlight~1268 demo:inst|knightlight[5] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "0.407 ns" { demo:inst|knightlight[5] demo:inst|knightlight~1268 demo:inst|knightlight[5] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.323ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.016 ns - Smallest register register " "Info: - Smallest register to register requirement is 0.016 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -2.378 ns " "Info: + Latch edge is -2.378 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination pll:inst1\|altpll:altpll_component\|_clk0 10.000 ns -2.378 ns  50 " "Info: Clock period of Destination clock \"pll:inst1\|altpll:altpll_component\|_clk0\" is 10.000 ns with  offset of -2.378 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.378 ns " "Info: - Launch edge is -2.378 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source pll:inst1\|altpll:altpll_component\|_clk0 10.000 ns -2.378 ns  50 " "Info: Clock period of Source clock \"pll:inst1\|altpll:altpll_component\|_clk0\" is 10.000 ns with  offset of -2.378 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll:inst1\|altpll:altpll_component\|_clk0 destination 2.602 ns + Longest register " "Info: + Longest clock path from clock \"pll:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.602 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll:inst1\|altpll:altpll_component\|_clk0'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "" { pll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns pll:inst1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'pll:inst1\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "1.091 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.974 ns) + CELL(0.537 ns) 2.602 ns demo:inst\|knightlight\[5\] 3 REG LCFF_X33_Y27_N29 5 " "Info: 3: + IC(0.974 ns) + CELL(0.537 ns) = 2.602 ns; Loc. = LCFF_X33_Y27_N29; Fanout = 5; REG Node = 'demo:inst\|knightlight\[5\]'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "1.511 ns" { pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[5] } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.64 % ) " "Info: Total cell delay = 0.537 ns ( 20.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.065 ns ( 79.36 % ) " "Info: Total interconnect delay = 2.065 ns ( 79.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[5] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[5] } { 0.000ns 1.091ns 0.974ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll:inst1\|altpll:altpll_component\|_clk0 source 2.602 ns - Shortest register " "Info: - Shortest clock path from clock \"pll:inst1\|altpll:altpll_component\|_clk0\" to source register is 2.602 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll:inst1\|altpll:altpll_component\|_clk0'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "" { pll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns pll:inst1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'pll:inst1\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "1.091 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.974 ns) + CELL(0.537 ns) 2.602 ns demo:inst\|knightlight\[5\] 3 REG LCFF_X33_Y27_N29 5 " "Info: 3: + IC(0.974 ns) + CELL(0.537 ns) = 2.602 ns; Loc. = LCFF_X33_Y27_N29; Fanout = 5; REG Node = 'demo:inst\|knightlight\[5\]'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "1.511 ns" { pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[5] } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.64 % ) " "Info: Total cell delay = 0.537 ns ( 20.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.065 ns ( 79.36 % ) " "Info: Total interconnect delay = 2.065 ns ( 79.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[5] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[5] } { 0.000ns 1.091ns 0.974ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[5] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[5] } { 0.000ns 1.091ns 0.974ns } { 0.000ns 0.000ns 0.537ns } "" } } { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[5] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[5] } { 0.000ns 1.091ns 0.974ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" {  } { { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 40 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 40 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[5] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[5] } { 0.000ns 1.091ns 0.974ns } { 0.000ns 0.000ns 0.537ns } "" } } { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[5] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[5] } { 0.000ns 1.091ns 0.974ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0}  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "0.407 ns" { demo:inst|knightlight[5] demo:inst|knightlight~1268 demo:inst|knightlight[5] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "0.407 ns" { demo:inst|knightlight[5] demo:inst|knightlight~1268 demo:inst|knightlight[5] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.323ns 0.084ns } "" } } { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[5] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[5] } { 0.000ns 1.091ns 0.974ns } { 0.000ns 0.000ns 0.537ns } "" } } { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[5] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[5] } { 0.000ns 1.091ns 0.974ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "demo:inst\|knightlight\[7\] RESET CLK 7.774 ns register " "Info: tsu for register \"demo:inst\|knightlight\[7\]\" (data pin = \"RESET\", clock pin = \"CLK\") is 7.774 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.034 ns + Longest pin register " "Info: + Longest pin to register delay is 8.034 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.850 ns) 0.850 ns RESET 1 PIN PIN_B3 16 " "Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_B3; Fanout = 16; PIN Node = 'RESET'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "" { RESET } "NODE_NAME" } } { "../src/demo_top.bdf" "" { Schematic "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo_top.bdf" { { 296 416 584 312 "RESET" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.674 ns) + CELL(0.510 ns) 8.034 ns demo:inst\|knightlight\[7\] 2 REG LCFF_X33_Y27_N15 4 " "Info: 2: + IC(6.674 ns) + CELL(0.510 ns) = 8.034 ns; Loc. = LCFF_X33_Y27_N15; Fanout = 4; REG Node = 'demo:inst\|knightlight\[7\]'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "7.184 ns" { RESET demo:inst|knightlight[7] } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.360 ns ( 16.93 % ) " "Info: Total cell delay = 1.360 ns ( 16.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.674 ns ( 83.07 % ) " "Info: Total interconnect delay = 6.674 ns ( 83.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "8.034 ns" { RESET demo:inst|knightlight[7] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "8.034 ns" { RESET RESET~combout demo:inst|knightlight[7] } { 0.000ns 0.000ns 6.674ns } { 0.000ns 0.850ns 0.510ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 40 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_PLL_OFFSET" "CLK pll:inst1\|altpll:altpll_component\|_clk0 -2.378 ns - " "Info: - Offset between input clock \"CLK\" and output clock \"pll:inst1\|altpll:altpll_component\|_clk0\" is -2.378 ns" {  } { { "../src/demo_top.bdf" "" { Schematic "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo_top.bdf" { { 56 136 304 72 "CLK" "" } } } } { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll:inst1\|altpll:altpll_component\|_clk0 destination 2.602 ns - Shortest register " "Info: - Shortest clock path from clock \"pll:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.602 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll:inst1\|altpll:altpll_component\|_clk0'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "" { pll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns pll:inst1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'pll:inst1\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "1.091 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.974 ns) + CELL(0.537 ns) 2.602 ns demo:inst\|knightlight\[7\] 3 REG LCFF_X33_Y27_N15 4 " "Info: 3: + IC(0.974 ns) + CELL(0.537 ns) = 2.602 ns; Loc. = LCFF_X33_Y27_N15; Fanout = 4; REG Node = 'demo:inst\|knightlight\[7\]'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "1.511 ns" { pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[7] } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.64 % ) " "Info: Total cell delay = 0.537 ns ( 20.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.065 ns ( 79.36 % ) " "Info: Total interconnect delay = 2.065 ns ( 79.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[7] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[7] } { 0.000ns 1.091ns 0.974ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "8.034 ns" { RESET demo:inst|knightlight[7] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "8.034 ns" { RESET RESET~combout demo:inst|knightlight[7] } { 0.000ns 0.000ns 6.674ns } { 0.000ns 0.850ns 0.510ns } "" } } { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[7] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.602 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[7] } { 0.000ns 1.091ns 0.974ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK LEDS\[0\] demo:inst\|knightlight\[0\] 9.507 ns register " "Info: tco from clock \"CLK\" to destination pin \"LEDS\[0\]\" through register \"demo:inst\|knightlight\[0\]\" is 9.507 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "CLK pll:inst1\|altpll:altpll_component\|_clk0 -2.378 ns + " "Info: + Offset between input clock \"CLK\" and output clock \"pll:inst1\|altpll:altpll_component\|_clk0\" is -2.378 ns" {  } { { "../src/demo_top.bdf" "" { Schematic "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo_top.bdf" { { 56 136 304 72 "CLK" "" } } } } { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll:inst1\|altpll:altpll_component\|_clk0 source 2.648 ns + Longest register " "Info: + Longest clock path from clock \"pll:inst1\|altpll:altpll_component\|_clk0\" to source register is 2.648 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll:inst1\|altpll:altpll_component\|_clk0'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "" { pll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns pll:inst1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'pll:inst1\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "1.091 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.020 ns) + CELL(0.537 ns) 2.648 ns demo:inst\|knightlight\[0\] 3 REG LCFF_X54_Y31_N19 4 " "Info: 3: + IC(1.020 ns) + CELL(0.537 ns) = 2.648 ns; Loc. = LCFF_X54_Y31_N19; Fanout = 4; REG Node = 'demo:inst\|knightlight\[0\]'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "1.557 ns" { pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[0] } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.28 % ) " "Info: Total cell delay = 0.537 ns ( 20.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.111 ns ( 79.72 % ) " "Info: Total interconnect delay = 2.111 ns ( 79.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.648 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[0] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.648 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[0] } { 0.000ns 1.091ns 1.020ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 40 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.987 ns + Longest register pin " "Info: + Longest register to pin delay is 8.987 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns demo:inst\|knightlight\[0\] 1 REG LCFF_X54_Y31_N19 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X54_Y31_N19; Fanout = 4; REG Node = 'demo:inst\|knightlight\[0\]'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "" { demo:inst|knightlight[0] } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.365 ns) + CELL(2.622 ns) 8.987 ns LEDS\[0\] 2 PIN PIN_W5 0 " "Info: 2: + IC(6.365 ns) + CELL(2.622 ns) = 8.987 ns; Loc. = PIN_W5; Fanout = 0; PIN Node = 'LEDS\[0\]'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "8.987 ns" { demo:inst|knightlight[0] LEDS[0] } "NODE_NAME" } } { "../src/demo_top.bdf" "" { Schematic "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo_top.bdf" { { 144 896 1072 160 "LEDS\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.622 ns ( 29.18 % ) " "Info: Total cell delay = 2.622 ns ( 29.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.365 ns ( 70.82 % ) " "Info: Total interconnect delay = 6.365 ns ( 70.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "8.987 ns" { demo:inst|knightlight[0] LEDS[0] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "8.987 ns" { demo:inst|knightlight[0] LEDS[0] } { 0.000ns 6.365ns } { 0.000ns 2.622ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.648 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[0] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.648 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|knightlight[0] } { 0.000ns 1.091ns 1.020ns } { 0.000ns 0.000ns 0.537ns } "" } } { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "8.987 ns" { demo:inst|knightlight[0] LEDS[0] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "8.987 ns" { demo:inst|knightlight[0] LEDS[0] } { 0.000ns 6.365ns } { 0.000ns 2.622ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "demo:inst\|counter\[0\] RESET CLK -7.313 ns register " "Info: th for register \"demo:inst\|counter\[0\]\" (data pin = \"RESET\", clock pin = \"CLK\") is -7.313 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "CLK pll:inst1\|altpll:altpll_component\|_clk0 -2.378 ns + " "Info: + Offset between input clock \"CLK\" and output clock \"pll:inst1\|altpll:altpll_component\|_clk0\" is -2.378 ns" {  } { { "../src/demo_top.bdf" "" { Schematic "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo_top.bdf" { { 56 136 304 72 "CLK" "" } } } } { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll:inst1\|altpll:altpll_component\|_clk0 destination 2.650 ns + Longest register " "Info: + Longest clock path from clock \"pll:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.650 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll:inst1\|altpll:altpll_component\|_clk0'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "" { pll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns pll:inst1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'pll:inst1\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "1.091 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.022 ns) + CELL(0.537 ns) 2.650 ns demo:inst\|counter\[0\] 3 REG LCFF_X55_Y31_N29 5 " "Info: 3: + IC(1.022 ns) + CELL(0.537 ns) = 2.650 ns; Loc. = LCFF_X55_Y31_N29; Fanout = 5; REG Node = 'demo:inst\|counter\[0\]'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "1.559 ns" { pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[0] } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.26 % ) " "Info: Total cell delay = 0.537 ns ( 20.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.113 ns ( 79.74 % ) " "Info: Total interconnect delay = 2.113 ns ( 79.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[0] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[0] } { 0.000ns 1.091ns 1.022ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 82 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.851 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.851 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.850 ns) 0.850 ns RESET 1 PIN PIN_B3 16 " "Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_B3; Fanout = 16; PIN Node = 'RESET'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "" { RESET } "NODE_NAME" } } { "../src/demo_top.bdf" "" { Schematic "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo_top.bdf" { { 296 416 584 312 "RESET" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.491 ns) + CELL(0.510 ns) 7.851 ns demo:inst\|counter\[0\] 2 REG LCFF_X55_Y31_N29 5 " "Info: 2: + IC(6.491 ns) + CELL(0.510 ns) = 7.851 ns; Loc. = LCFF_X55_Y31_N29; Fanout = 5; REG Node = 'demo:inst\|counter\[0\]'" {  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "7.001 ns" { RESET demo:inst|counter[0] } "NODE_NAME" } } { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.360 ns ( 17.32 % ) " "Info: Total cell delay = 1.360 ns ( 17.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.491 ns ( 82.68 % ) " "Info: Total interconnect delay = 6.491 ns ( 82.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "7.851 ns" { RESET demo:inst|counter[0] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "7.851 ns" { RESET RESET~combout demo:inst|counter[0] } { 0.000ns 0.000ns 6.491ns } { 0.000ns 0.850ns 0.510ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[0] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "2.650 ns" { pll:inst1|altpll:altpll_component|_clk0 pll:inst1|altpll:altpll_component|_clk0~clkctrl demo:inst|counter[0] } { 0.000ns 1.091ns 1.022ns } { 0.000ns 0.000ns 0.537ns } "" } } { "/opt/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/linux/TimingClosureFloorplan.fld" "" "7.851 ns" { RESET demo:inst|counter[0] } "NODE_NAME" } } { "/opt/quartus/linux/Technology_Viewer.qrui" "" { "Technology Map Viewer" "/opt/quartus/linux/Technology_Viewer.qrui" "7.851 ns" { RESET RESET~combout demo:inst|counter[0] } { 0.000ns 0.000ns 6.491ns } { 0.000ns 0.850ns 0.510ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITAN_REQUIREMENTS_MET_SLOW" "" "Info: All timing requirements were met for slow timing model timing analysis. See Report window for more details." {  } {  } 0 0 "All timing requirements were met for slow timing model timing analysis. See Report window for more details." 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 30 19:53:32 2009 " "Info: Processing ended: Mon Mar 30 19:53:32 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}