one place for all my love

[hwmod.git] / demo / quartus / db / demo.map.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 30 19:52:35 2009 " "Info: Processing started: Mon Mar 30 19:52:35 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off demo -c demo " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off demo -c demo" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../src/demo_pkg.vhd 1 0 " "Info: Found 1 design units, including 0 entities, in source file ../src/demo_pkg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 demo_pkg " "Info: Found design unit 1: demo_pkg" {  } { { "../src/demo_pkg.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo_pkg.vhd" 4 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../src/demo.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../src/demo.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 demo-behav " "Info: Found design unit 1: demo-behav" {  } { { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 demo " "Info: Found entity 1: demo" {  } { { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../src/pll.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../src/pll.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pll-SYN " "Info: Found design unit 1: pll-SYN" {  } { { "../src/pll.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/pll.vhd" 51 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 pll " "Info: Found entity 1: pll" {  } { { "../src/pll.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/pll.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../src/demo_top.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../src/demo_top.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 demo_top " "Info: Found entity 1: demo_top" {  } { { "../src/demo_top.bdf" "" { Schematic "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo_top.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "demo_top " "Info: Elaborating entity \"demo_top\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "demo demo:inst " "Info: Elaborating entity \"demo\" for hierarchy \"demo:inst\"" {  } { { "../src/demo_top.bdf" "inst" { Schematic "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo_top.bdf" { { 120 696 856 216 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll pll:inst1 " "Info: Elaborating entity \"pll\" for hierarchy \"pll:inst1\"" {  } { { "../src/demo_top.bdf" "inst1" { Schematic "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo_top.bdf" { { 56 352 592 216 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/opt/quartus/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file /opt/quartus/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "/opt/quartus/libraries/megafunctions/altpll.tdf" 454 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll pll:inst1\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"pll:inst1\|altpll:altpll_component\"" {  } { { "../src/pll.vhd" "altpll_component" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/pll.vhd" 130 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "pll:inst1\|altpll:altpll_component " "Info: Elaborated megafunction instantiation \"pll:inst1\|altpll:altpll_component\"" {  } { { "../src/pll.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/pll.vhd" 130 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/opt/quartus/libraries/megafunctions/lpm_divide.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file /opt/quartus/libraries/megafunctions/lpm_divide.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide " "Info: Found entity 1: lpm_divide" {  } { { "lpm_divide.tdf" "" { Text "/opt/quartus/libraries/megafunctions/lpm_divide.tdf" 118 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "demo:inst\|lpm_divide:Mod0 " "Info: Elaborated megafunction instantiation \"demo:inst\|lpm_divide:Mod0\"" {  } { { "../src/demo.vhd" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/src/demo.vhd" 86 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_85m.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_85m.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_85m " "Info: Found entity 1: lpm_divide_85m" {  } { { "db/lpm_divide_85m.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/lpm_divide_85m.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_fkh.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_fkh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_fkh " "Info: Found entity 1: sign_div_unsign_fkh" {  } { { "db/sign_div_unsign_fkh.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/sign_div_unsign_fkh.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_00f.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_00f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_00f " "Info: Found entity 1: alt_u_div_00f" {  } { { "db/alt_u_div_00f.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_lkc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_lkc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_lkc " "Info: Found entity 1: add_sub_lkc" {  } { { "db/add_sub_lkc.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/add_sub_lkc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_mkc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_mkc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_mkc " "Info: Found entity 1: add_sub_mkc" {  } { { "db/add_sub_mkc.tdf" "" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/add_sub_mkc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISCL_SCL_WANNA_REM_USR_WIRE" "" "Info: Found the following redundant logic cells in design" { { "Info" "ISCL_SCL_CELL_NAME" "demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[0\]~34 " "Info: Logic cell \"demo:inst\|lpm_divide:Mod0\|lpm_divide_85m:auto_generated\|sign_div_unsign_fkh:divider\|alt_u_div_00f:divider\|add_sub_7_result_int\[0\]~34\"" {  } { { "db/alt_u_div_00f.tdf" "add_sub_7_result_int\[0\]~34" { Text "/homes/lechner/Lehre/SS09/HW-Modelling/VO_2009/designflow_presentation/quartus/db/alt_u_div_00f.tdf" 62 22 0 } }  } 0 0 "Logic cell \"%1!s!\"" 0 0}  } {  } 0 0 "Found the following redundant logic cells in design" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "84 " "Info: Implemented 84 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "73 " "Info: Implemented 73 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_PLLS" "1 " "Info: Implemented 1 ClockLock PLLs" {  } {  } 0 0 "Implemented %1!d! ClockLock PLLs" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 30 19:52:38 2009 " "Info: Processing ended: Mon Mar 30 19:52:38 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}