demo/quartus/db/sign_div_unsign_dnh.tdf

   1 --sign_div_unsign DEN_REPRESENTATION="UNSIGNED" DEN_WIDTH=25 LPM_PIPELINE=0 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="UNSIGNED" NUM_WIDTH=25 SKIP_BITS=0 denominator numerator quotient remainder
   2 --VERSION_BEGIN 7.0 cbx_cycloneii 2006:09:30:03:03:26:SJ cbx_lpm_abs 2006:04:25:22:52:42:SJ cbx_lpm_add_sub 2006:10:11:06:03:24:SJ cbx_lpm_divide 2006:01:19:01:01:10:SJ cbx_mgl 2006:10:28:00:08:48:SJ cbx_stratix 2006:09:18:18:47:42:SJ cbx_stratixii 2006:10:13:22:01:30:SJ cbx_util_mgl 2006:11:03:18:32:30:SJ  VERSION_END
   3
   4
   5 --  Copyright (C) 1991-2007 Altera Corporation
   6 --  Your use of Altera Corporation's design tools, logic functions
   7 --  and other software and tools, and its AMPP partner logic
   8 --  functions, and any output files from any of the foregoing
   9 --  (including device programming or simulation files), and any
  10 --  associated documentation or information are expressly subject
  11 --  to the terms and conditions of the Altera Program License
  12 --  Subscription Agreement, Altera MegaCore Function License
  13 --  Agreement, or other applicable license agreement, including,
  14 --  without limitation, that your use is for the sole purpose of
  15 --  programming logic devices manufactured by Altera and sold by
  16 --  Altera or its authorized distributors.  Please refer to the
  17 --  applicable agreement for further details.
  18
  19
  20 FUNCTION alt_u_div_s5f (denominator[24..0], numerator[24..0])
  21 RETURNS ( den_out[24..0], quotient[24..0], remainder[24..0]);
  22
  23 --synthesis_resources = lut 371
  24 SUBDESIGN sign_div_unsign_dnh
  25 (
  26         denominator[24..0]      :       input;
  27         numerator[24..0]        :       input;
  28         quotient[24..0] :       output;
  29         remainder[24..0]        :       output;
  30 )
  31 VARIABLE
  32         divider : alt_u_div_s5f;
  33         adder_result_int[25..0] :       WIRE;
  34         adder_cin       :       WIRE;
  35         adder_dataa[24..0]      :       WIRE;
  36         adder_datab[24..0]      :       WIRE;
  37         adder_result[24..0]     :       WIRE;
  38         gnd_wire        : WIRE;
  39         norm_num[24..0] : WIRE;
  40         protect_quotient[24..0] : WIRE;
  41         protect_remainder[24..0]        : WIRE;
  42
  43 BEGIN
  44         divider.denominator[] = denominator[];
  45         divider.numerator[] = norm_num[];
  46         adder_result_int[] = (adder_dataa[], 0) - (adder_datab[], !adder_cin);
  47         adder_result[] = adder_result_int[25..1];
  48         adder_cin = gnd_wire;
  49         adder_dataa[] = denominator[];
  50         adder_datab[] = protect_remainder[];
  51         gnd_wire = B"0";
  52         norm_num[] = numerator[];
  53         protect_quotient[] = divider.quotient[];
  54         protect_remainder[] = divider.remainder[];
  55         quotient[] = protect_quotient[];
  56         remainder[] = protect_remainder[];
  57 END;
  58 --VALID FILE