7seg added to dt_inc.s
[calu.git] / cpu /
2010-11-29 Stefan Rebernigst
2010-11-29 Markus Hofstätterldi add finished
2010-11-29 Markus Hofstätteradded: alu ldi
2010-11-29 Stefan Rebernigdecoder add ldi
2010-11-29 Markus HofstätterAdded: LDST_OP
2010-11-26 Stefan Rebernigforward unit testcases (from assignments), everything...
2010-11-18 Manfred5 abgabe finish
2010-11-18 Manfredblabla
2010-11-18 Manfrednew testbench
2010-11-17 Stefan Rebernigkleine Änderungen
2010-11-16 Stefan Rebernigkleinigkeit ausgebessert
2010-11-16 Stefan Rebernig2nd forward unit - 58MHz with 31bit shift...
2010-11-16 Stefan Rebernignop insertion added
2010-11-15 Stefan Rebernigpipeline erste version mit 31bit shifter (kostet 7MHz...
2010-11-15 Stefan Rebernigtest pipe 2
2010-11-15 Stefan Rebernigpipe v1
2010-11-15 Markus HofstätterFixed some bugs.
2010-11-15 Markus Hofstättergpm module and exec first buggy version.
2010-11-15 Stefan Rebernigblub
2010-11-15 Stefan Rebernigwriteback stage
2010-11-15 Markus HofstätterMerge branch 'master' of wien.tomnetworks.com:calu
2010-11-15 Stefandisplacement
2010-11-15 Markus HOFSTAETTERexec impl.
2010-11-15 Stefanadded pipe 2 reg, testbench, top_level_entity, ...
2010-11-15 Stefanpipe2
2010-11-14 Markus HofstätterSeperation to differen execute operations.
2010-11-14 Stefanquartus tcl script für meinen cyclone II, top level...
2010-11-14 Stefangitignore für sim
2010-11-14 Stefando file for testbench - a few test instructions added...
2010-11-14 Stefanfetch und decode kompilierbar, generelle tb, änderung...
2010-11-14 Markus HofstätterAdded interface types
2010-11-14 Markus HofstaetterAdded arithmetic and logical vhdl functions
2010-11-13 Stefandecode stage die erste
2010-11-10 Stefanupdate blockdiagramm
2010-11-10 StefanBlockdiagramm: PC in PIPE1 verschoben
2010-11-10 U-Thor\Schakaladded rw-r port ram
2010-11-10 StefanVHDL Grundkonstrukt