gitignore für sim

diff --git a/cpu/sim/.gitignore b/cpu/sim/.gitignore
new file mode 100644 (file)
index 0000000..891db2f
--- /dev/null
+++ b/cpu/sim/.gitignore
@@ -0,0 +1,3 @@
+*.ini
+*.wlf
+/work/*

diff --git a/cpu/src/fetch_stage_b.vhd b/cpu/src/fetch_stage_b.vhd
index e774901a01dc6b93b514d15d9d6e707886ccc8fb..67dde3cc764e392975ca730a19f9f76ad68f1130 100644 (file)
--- a/cpu/src/fetch_stage_b.vhd
+++ b/cpu/src/fetch_stage_b.vhd
@@ -45,13 +45,17 @@ begin
 end process; 
 
 
-asyn: process(instr_r_addr, jump_result, prediction_result, branch_prediction_bit, alu_jump_bit, instr_rd_data)
+asyn: process(reset, instr_r_addr, jump_result, prediction_result, branch_prediction_bit, alu_jump_bit, instr_rd_data)
 
 begin
 
        instruction <= instr_rd_data;
        instr_r_addr_nxt <= std_logic_vector(unsigned(instr_r_addr) + 1);
 
+       if (reset = RESET_VALUE) then
+               instr_r_addr_nxt <= (others => '0');
+       end if;
+
        if (alu_jump_bit = LOGIC_ACT) then
                instr_r_addr_nxt <= jump_result;        
        elsif (branch_prediction_bit = LOGIC_ACT) then

diff --git a/cpu/src/r2_w_ram_b.vhd b/cpu/src/r2_w_ram_b.vhd
index 84a3a94b150f6747a4319645f7c37f86e01810c3..3c71ade0c41a6d254832c95865d877cf64f11b35 100644 (file)
--- a/cpu/src/r2_w_ram_b.vhd
+++ b/cpu/src/r2_w_ram_b.vhd
@@ -10,7 +10,12 @@ architecture behaviour of r2_w_ram is
        subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
        type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
        
-       signal ram : RAM_TYPE := (others=> x"00000001");
+       signal ram : RAM_TYPE := (
+                               0 => x"00000010",
+                               1 => x"00110010",
+                               2 => x"000000FF",
+                               3 => x"00AB00BA",
+                               others=> x"00000000");
 
 begin
        process(clk)

diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd
index 9e530fad63d42eddf6d7b0d6c5204642e408bdd1..f03388593c6ec05dddd76dd1604e820f0a3641f7 100644 (file)
--- a/cpu/src/r_w_ram_b.vhd
+++ b/cpu/src/r_w_ram_b.vhd
@@ -10,7 +10,11 @@ architecture behaviour of r_w_ram is
        subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
        type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
        
-       signal ram : RAM_TYPE := ((others => b"11100000000000001001000000000000"));
+       signal ram : RAM_TYPE := (0 => "11100000000000011001000000000000", 
+                                 1 => "11100000000000001001000000000000", 
+                                 2 => "11100000000010001001000000000000", 
+                                 3 => "11100001000110010111011001101100", 
+                                 others => x"00000000");
 
 begin
        process(clk)