Fixed some bugs.

diff --git a/cpu/sim/testcore.do b/cpu/sim/testcore.do
index da92a48b390eaa2b7cc894f55eb8d925ef31251c..6f5b7c880a0a78a5ce5892f088e2a64011c463c4 100644 (file)
--- a/cpu/sim/testcore.do
+++ b/cpu/sim/testcore.do
@@ -14,6 +14,31 @@ vcom -work work ../src/fetch_stage.vhd
 vcom -work work ../src/fetch_stage_b.vhd
 vcom -work work ../src/decode_stage.vhd
 vcom -work work ../src/decode_stage_b.vhd
+
+vcom -work work ../src/alu_pkg.vhd
+vcom -work work ../src/extension_pkg.vhd
+vcom -work work ../src/gpm_pkg.vhd
+
+vcom -work work ../src/exec_op.vhd
+vcom -work work ../src/exec_op/add_op_b.vhd
+vcom -work work ../src/exec_op/and_op_b.vhd
+vcom -work work ../src/exec_op/or_op_b.vhd
+vcom -work work ../src/exec_op/xor_op_b.vhd
+vcom -work work ../src/exec_op/shift_op_b.vhd
+
+vcom -work work ../src/alu.vhd
+vcom -work work ../src/alu_b.vhd
+
+vcom -work work ../src/gpm.vhd
+vcom -work work ../src/gpm_b.vhd
+
+vcom -work work ../src/execute_stage.vhd
+vcom -work work ../src/execute_stage_b.vhd
+
+
+vcom -work work ../src/writeback_stage.vhd
+vcom -work work ../src/writeback_stage_b.vhd
+
 vcom -work work ../src/pipeline_tb.vhd
 
 vsim work.pipeline_conf_beh -t ns

diff --git a/cpu/src/alu.vhd b/cpu/src/alu.vhd
index 02401dbbd062ea82aaa6604497b02573dcf8e02b..7950c6c4ef8cd713bd8c8a06dfe9b0fe6fc92192 100755 (executable)
--- a/cpu/src/alu.vhd
+++ b/cpu/src/alu.vhd
@@ -13,7 +13,7 @@ entity alu is
                        clk : in std_logic;\r
                        reset : in std_logic;\r
        --operation inputs\r
-                       condition : in condition_t;\r
+                       cond : in condition_t;\r
                        op_group : in op_info_t;\r
                        left_operand : in gp_register_t;\r
                        right_operand : in gp_register_t;\r

diff --git a/cpu/src/alu_b.vhd b/cpu/src/alu_b.vhd
index 78696f2e619635e818e91a10fd46c1e10d566e3a..3fb3434827af3647c95b48f6a2770de187f20901 100755 (executable)
--- a/cpu/src/alu_b.vhd
+++ b/cpu/src/alu_b.vhd
@@ -38,7 +38,7 @@ begin
        shift_inst : exec_op\r
        port map(clk,reset,left_operand, right_operand, op_detail, alu_state, shift_result);\r
 \r
-calc: process(condition, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result)\r
+calc: process(cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result)\r
        variable result_v : alu_result_rec;\r
        variable res_prod : std_logic;\r
        variable cond_met : std_logic;\r
@@ -49,9 +49,9 @@ begin
        result_v.result := add_result.result;\r
        res_prod := '1';\r
        mem_en := '0';
-        addr <= add_result;\r
+        addr <= add_result.result;\r
        \r
-       case condition is\r
+       case cond is\r
        when COND_NZERO =>\r
                cond_met := not(alu_state.status.zero);\r
        when COND_ZERO =>\r
@@ -83,7 +83,8 @@ begin
        when COND_ALWAYS =>\r
                cond_met := '1';\r
        when COND_NEVER =>\r
-               cond_met := '0';\r
+               cond_met := '0';
+       when others => null;\r
        end case;\r
        \r
        case op_group is\r
@@ -109,11 +110,11 @@ begin
                result_v.status := alu_state.status;\r
        end if;\r
        \r
-       result_v.new_val := not(op_detail(NO_DST_OPT)) and res_prod and cond_met;\r
+       result_v.reg_op := not(op_detail(NO_DST_OPT)) and res_prod and cond_met;\r
        result_v.mem_en := mem_en and cond_met;
 
         \r
-       data <= add_result;\r
+       data <= add_result.result;\r
        alu_result <= result_v;\r
        \r
 end process calc; \r

diff --git a/cpu/src/alu_pkg.vhd b/cpu/src/alu_pkg.vhd
index 893653594aabf6e751da78fe7413990330c387e9..ead1ac694b63759ebbac2405d92dafb8bb1798cc 100755 (executable)
--- a/cpu/src/alu_pkg.vhd
+++ b/cpu/src/alu_pkg.vhd
@@ -28,7 +28,7 @@ package alu_pkg is
                status : status_rec;\r
                --stackpointer : gp_register_t;\r
 \r
-               alu_jmp : std_logic;\r
+               alu_jump : std_logic;\r
                brpr : std_logic;\r
                reg_op : std_logic;\r
                mem_op  : std_logic;\r
@@ -80,7 +80,7 @@ package alu_pkg is
                        clk : in std_logic;\r
                        reset : in std_logic;\r
        --operation inputs\r
-                       condition : in condition_t;\r
+                       cond : in condition_t;\r
                        op_group : in op_info_t;\r
                        left_operand : in gp_register_t;\r
                        right_operand : in gp_register_t;\r

diff --git a/cpu/src/core_pkg.vhd b/cpu/src/core_pkg.vhd
index 24d06a29afef22c7757152cdd91f99c73c69b89a..13ac38243997008feb252339661fa1bd8eea3c1b 100644 (file)
--- a/cpu/src/core_pkg.vhd
+++ b/cpu/src/core_pkg.vhd
@@ -74,17 +74,32 @@ package core_pkg is
        end component decoder;
 
        component execute_stage is
+       
        generic (
                        -- active reset value
-                       RESET_VALUE : std_logic;
+                       RESET_VALUE : std_logic
                        -- active logic value
-                       LOGIC_ACT : std_logic
+                       --LOGIC_ACT : std_logic;
                        
                        );
        port(
                --System inputs
                        clk : in std_logic;
-                       reset : in std_logic
+                       reset : in std_logic;
+                        dec_instr : in dec_op;
+
+                --System output
+                        result : out gp_register_t;--reg
+                        result_addr : out gp_addr_t;--reg
+                        addr : out word_t; --memaddr
+                        data : out gp_register_t; --mem data --ureg
+                        alu_jump : out std_logic;--reg
+                        brpr  : out std_logic;  --reg
+                        wr_en : out std_logic;--regop --reg
+                        dmem  : out std_logic;--memop
+                        dmem_write_en : out std_logic;
+                        hword  : out std_logic;
+                        byte_s : out std_logic
                );
        end component execute_stage;
 
@@ -101,7 +116,7 @@ package core_pkg is
        port(
                --System inputs
                        clk : in std_logic;
-                       reset : in std_logic
+                       reset : in std_logic;
 
                        result : in gp_register_t;      --reg  (alu result or jumpaddr)
                        result_addr : in gp_addr_t;     --reg

diff --git a/cpu/src/exec_op/add_op_b.vhd b/cpu/src/exec_op/add_op_b.vhd
index 919c795d23a76eae9f9149eae22dda568226ddec..88e34d432b75e0ba2cf046959ef60f3e8e7a1e67 100644 (file)
--- a/cpu/src/exec_op/add_op_b.vhd
+++ b/cpu/src/exec_op/add_op_b.vhd
@@ -31,7 +31,7 @@ begin
                l_neg := left_operand(gp_register_t'high);
                
                carry_res := unsigned('0' & left_operand)+addcarry;
-               oflo1 := add_oflo(l_neg,'0',std_logic_vector(carry_res)(gp_register_t'high));
+               oflo1 := add_oflo(l_neg,'0',carry_res(gp_register_t'high));
                
                if sub = '1' then
                        tmp_right_operand := unsigned('0' & complement);
@@ -39,15 +39,15 @@ begin
                        tmp_right_operand := unsigned('0' & right_operand);
                end if;
                
-               l_neg := std_logic_vector(carry_res)(gp_register_t'high);
-               r_neg := std_logic_vector(tmp_right_operand)(gp_register_t'high);
+               l_neg := carry_res(gp_register_t'high);
+               r_neg := tmp_right_operand(gp_register_t'high);
                
                carry_res := carry_res + tmp_right_operand;
-               oflo2 := add_oflo(l_neg,r_neg,std_logic_vector(carry_res)(gp_register_t'high));
+               oflo2 := add_oflo(l_neg,r_neg,carry_res(gp_register_t'high));
                
 
-               alu_result_v.result := std_logic_vector(carry_res)(gp_register_t'range);
-               alu_result_v.status.carry := std_logic_vector(carry_res)(carry_res'high);
+               alu_result_v.result := std_logic_vector(carry_res(gp_register_t'range));
+               alu_result_v.status.carry := carry_res(carry_res'high);
                
                
                alu_result_v.status.carry := oflo1 or oflo2;

diff --git a/cpu/src/exec_op/shift_op_b.vhd b/cpu/src/exec_op/shift_op_b.vhd
index 7f00dcfb6a4d2b74e5b440d9c85ca77b9d2cc1b6..6e17280c833aed0a1619e81dd44727e79528a26c 100644 (file)
--- a/cpu/src/exec_op/shift_op_b.vhd
+++ b/cpu/src/exec_op/shift_op_b.vhd
@@ -7,17 +7,12 @@ use work.alu_pkg.all;
 
 architecture shift_op of exec_op is
 
-       signal logic, ls, carry : std_logic;
+       signal arith, rs, carry : std_logic;
 
 begin
 
-<<<<<<< HEAD
        arith <=  op_detail(ARITH_OPT);
        rs      <=  op_detail(RIGHT_OPT);
-=======
-       logic <=  op_detail(ARITH_OPT);
-       ls      <=  op_detail(RIGHT_OPT);
->>>>>>> 05fc0d5300956fef107bbb8507a6480ee11695ff
        carry <= op_detail(CARRY_OPT);
 
 calc: process(left_operand, right_operand, arith,rs, carry, alu_state)
@@ -30,13 +25,13 @@ begin
                 if rs = '1' then   
                        tmp_sb := (carry and alu_state.status.carry and not(arith)) or (arith and left_operand(gp_register_t'high));
                        tmp_shift := to_bitvector(tmp_sb & left_operand & alu_state.status.carry);
-                       tmp_shift := tmp_shift sra to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0));
+                       tmp_shift := tmp_shift sra to_integer(unsigned(right_operand(SHIFT_WIDTH-1 downto 0)));
                        
                        alu_result_v.status.carry := to_stdlogicvector(tmp_shift)(0);
                else 
                        tmp_sb := (carry and alu_state.status.carry and not(arith));
                        tmp_shift :=  to_bitvector(alu_state.status.carry & left_operand & tmp_sb);
-                       tmp_shift :=  tmp_shift sla to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0));
+                       tmp_shift :=  tmp_shift sla to_integer(unsigned(right_operand(SHIFT_WIDTH-1 downto 0)));
                        
                        alu_result_v.status.carry := to_stdlogicvector(tmp_shift)(tmp_shift'high);
                end if;

diff --git a/cpu/src/execute_stage.vhd b/cpu/src/execute_stage.vhd
index 9ca96bcf2e9921f9386e4e34c4993b05d3025937..c5d6817aa9c957c84bba51182291a0cc2fc9944d 100644 (file)
--- a/cpu/src/execute_stage.vhd
+++ b/cpu/src/execute_stage.vhd
@@ -2,11 +2,15 @@ library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 
+use work.common_pkg.all;
+use work.alu_pkg.all;
+use work.gpm_pkg.all;
+
 entity execute_stage is
 
        generic (
                        -- active reset value
-                       RESET_VALUE : std_logic;
+                       RESET_VALUE : std_logic
                        -- active logic value
                        --LOGIC_ACT : std_logic;
                        
@@ -26,7 +30,7 @@ entity execute_stage is
                         brpr  : out std_logic;  --reg
                         wr_en : out std_logic;--regop --reg
                         dmem  : out std_logic;--memop
-                        dmem_wr_en : out std_logic;
+                        dmem_write_en : out std_logic;
                         hword  : out std_logic;
                         byte_s : out std_logic
                );

diff --git a/cpu/src/execute_stage_b.vhd b/cpu/src/execute_stage_b.vhd
index 080fb00accba7186704cd9e474927f4c8c5a4beb..1f2c194ac263470f6bfa560da6ae9c9abd1bdfb9 100644 (file)
--- a/cpu/src/execute_stage_b.vhd
+++ b/cpu/src/execute_stage_b.vhd
@@ -4,6 +4,7 @@ use IEEE.numeric_std.all;
 
 use work.common_pkg.all;
 use work.alu_pkg.all;
+use work.gpm_pkg.all;
 
 architecture behav of execute_stage is
 
@@ -28,14 +29,18 @@ begin
 
 alu_inst : alu
 port map(clk, reset, condition, op_group, 
-        op_detail, left_operand, right_operand, alu_state, alu_nxt,addr,data);
+         left_operand, right_operand, op_detail, alu_state, alu_nxt,addr,data);
+
+gpm_inst : gpm
+        generic map(RESET_VALUE)
+        port map(clk,reset,alu_nxt,psw);
 
 syn: process(clk, reset)
 
 begin
 
        if reset = RESET_VALUE then
-               reg.alu_jmp <= '0';
+               reg.alu_jump <= '0';
                 reg.brpr <= '0';
                 reg.wr_en <= '0';
                 reg.result <= (others =>'0');
@@ -69,14 +74,14 @@ begin
         reg_nxt.alu_jump <= alu_nxt.alu_jump;
         reg_nxt.wr_en <= alu_nxt.reg_op;
         reg_nxt.result <= alu_nxt.result;
-        reg_nxt.reg_addr <= alu_nxt.result_addr;
+        reg_nxt.res_addr <= alu_nxt.result_addr;
 
 end process asyn;
 
 result <= reg.result;
 result_addr <= reg.res_addr;
-alu_jmp <= reg.alu_jump;
-brbr <= reg.brpr;
+alu_jump <= reg.alu_jump;
+brpr <= reg.brpr;
 wr_en <= reg.wr_en;
 dmem <= alu_nxt.mem_op;
 dmem_write_en <= alu_nxt.mem_en;

diff --git a/cpu/src/extension_pkg.vhd b/cpu/src/extension_pkg.vhd
index bf58a277b9ca66d3ef677f206cc2f5f8d22f5185..be46852dbdaeb06ba218cb94f5b349e4acd0e7ac 100644 (file)
--- a/cpu/src/extension_pkg.vhd
+++ b/cpu/src/extension_pkg.vhd
@@ -15,8 +15,8 @@ package extension_pkg is
                 
                 wr_en : std_logic;
                 byte_en : std_logic_vector(gp_register_t'length/byte_t'length-1 downto 0); 
-                data : data_ram_word_t;
-                addr : data_addr_t;          
+                data : gp_register_t;
+                addr : gp_register_t;          
         end record; 
        
        

diff --git a/cpu/src/gpm.vhd b/cpu/src/gpm.vhd
index 428bdbb3454c7867428e0e2cf105bdb03f3ddba9..1012c7b317dc3cac28285eb5b8c791f17756a452 100644 (file)
--- a/cpu/src/gpm.vhd
+++ b/cpu/src/gpm.vhd
@@ -4,13 +4,13 @@ use IEEE.numeric_std.all;
 
 use work.common_pkg.all;
 use work.alu_pkg.all;
-use work.extension_pgk.all;
+use work.extension_pkg.all;
 
 entity gpm is
 
        generic (
                        -- active reset value
-                       RESET_VALUE : std_logic;
+                       RESET_VALUE : std_logic
                        -- active logic value
                        --LOGIC_ACT : std_logic
                        
@@ -26,7 +26,7 @@ entity gpm is
                 --input
                 
                 --output
-                psw     : out status_rec;
+                psw     : out status_rec
                 --to memcnt
                 --addr : out gp_register_t;
                 --mem_en : out std_logic;

diff --git a/cpu/src/gpm_b.vhd b/cpu/src/gpm_b.vhd
index 081830471f9d9f36c9df855d6c610bff530e1e72..7327a9f6c0b62f1778a27345cbf85b8a14bd226b 100644 (file)
--- a/cpu/src/gpm_b.vhd
+++ b/cpu/src/gpm_b.vhd
@@ -5,59 +5,28 @@ use IEEE.numeric_std.all;
 use work.common_pkg.all;
 use work.alu_pkg.all;
 
-entity gpm is
-
-       generic (
-                       -- active reset value
-                       RESET_VALUE : std_logic;
-                       -- active logic value
-                       --LOGIC_ACT : std_logic
-                       
-                       );
-       port(
-               --System inputs
-                clk : in std_logic;
-               reset : in std_logic;
-
-                --exti : in extmod_rec;
-                --alu outpus
-                alu_nxt : in alu_result_rec;
-                --input
-                
-                --output
-                psw     : out status_rec;
-                --to memcnt
-                --addr : out gp_register_t;
-                --mem_en : out std_logic;
-                --ldst : out std_logic;
-                --, hw,byte: std_logic;
-                --to output bus
-                --exto : out data_ram_word_t
-                        
-        );
-               
-end gpm;
-
 architecture behaviour of gpm is
 type gpm_internal is record
         status : status_rec;
 end record gpm_internal;
 
-reg, reg_nxt : gpm_internal;
+signal reg, reg_nxt : gpm_internal;
 
 begin
 syn : process (clk, reset)
-        if reset = RESET_VALUE then
-                reg <= (('0','0','0','0'));
+begin
+        if (reset = RESET_VALUE) then
+                reg.status <= ('0','0','0','0');
         elsif rising_edge(clk) then
                 reg <= reg_nxt;
         end if;
 end process syn;
 
 asyn : process (clk, reset)
-        reg_nxt <= alu_nxt.status;
+begin
+        reg_nxt.status <= alu_nxt.status;
 end process asyn;
 
-psw <= reg;
+psw <= reg.status;
         
 end architecture behaviour;

diff --git a/cpu/src/gpm_pkg.vhd b/cpu/src/gpm_pkg.vhd
new file mode 100644 (file)
index 0000000..281878b
--- /dev/null
+++ b/cpu/src/gpm_pkg.vhd
@@ -0,0 +1,41 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.common_pkg.all;
+use work.alu_pkg.all;
+
+package gpm_pkg is
+        component gpm is
+
+               generic (
+                               -- active reset value
+                               RESET_VALUE : std_logic
+                               -- active logic value
+                               --LOGIC_ACT : std_logic
+                               
+                               );
+               port(
+                       --System inputs
+                        clk : in std_logic;
+                       reset : in std_logic;
+
+                        --exti : in extmod_rec;
+                        --alu outpus
+                        alu_nxt : in alu_result_rec;
+                        --input
+                        
+                        --output
+                        psw     : out status_rec
+                        --to memcnt
+                        --addr : out gp_register_t;
+                        --mem_en : out std_logic;
+                        --ldst : out std_logic;
+                        --, hw,byte: std_logic;
+                        --to output bus
+                        --exto : out data_ram_word_t
+                                
+                );
+                       
+        end component gpm;
+end package gpm_pkg;

diff --git a/cpu/src/pipeline_tb.vhd b/cpu/src/pipeline_tb.vhd
index e856e69ec98343498a5a36bc4c5846c24a22a541..c1c6b0c79f978416379359ce24f45f9a995a5f47 100644 (file)
--- a/cpu/src/pipeline_tb.vhd
+++ b/cpu/src/pipeline_tb.vhd
@@ -4,7 +4,6 @@ use IEEE.numeric_std.all;
 
 use work.common_pkg.all;
 use work.core_pkg.all;
-
 -------------------------------------------------------------------------------
 -- ENTITY
 -------------------------------------------------------------------------------
@@ -37,6 +36,18 @@ architecture behavior of pipeline_tb is
                signal reg_we_pin : std_logic;
                signal to_next_stage_pin : dec_op;
 
+                 signal result_pin : gp_register_t;--reg
+                 signal result_addr_pin : gp_addr_t;--reg
+                 signal addr_pin : word_t; --memaddr
+                 signal data_pin : gp_register_t; --mem data --ureg
+                 signal alu_jump_pin : std_logic;--reg
+                 signal brpr_pin  : std_logic;  --reg
+                 signal wr_en_pin : std_logic;--regop --reg
+                 signal dmem_pin  : std_logic;--memop
+                 signal dmem_wr_en_pin : std_logic;
+                 signal hword_pin  : std_logic;
+                 signal byte_s_pin : std_logic;
+
 begin
 
 --             instruction_ram : r_w_ram
@@ -101,6 +112,16 @@ begin
                        to_next_stage => to_next_stage_pin
                        
                );
+          exec_st : execute_stage
+                generic map('0')
+                port map(sys_clk_pin, sys_res_n_pin,to_next_stage_pin, result_pin, result_addr_pin,addr_pin,
+                data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin);
+
+          writeback_st : writeback_stage
+                generic map('0', '1')
+                port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, 
+                wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
+                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin);
 
 
 
@@ -133,9 +154,9 @@ begin
     -- initial reset
     -----------------------------------------------------------------------------
        sys_res_n_pin <= '0';
-       reg_w_addr_pin <= (others => '0');
-       reg_wr_data_pin <= (others => '0');
-       reg_we_pin <= '0';
+--     reg_w_addr_pin <= (others => '0');
+--     reg_wr_data_pin <= (others => '0');
+--     reg_we_pin <= '0';
 
        icwait(10);
        dummy <= '1';
@@ -166,6 +187,10 @@ configuration pipeline_conf_beh of pipeline_tb is
     end for;
     for decode_st : decode_stage use entity work.decode_stage(behav);
     end for;
+    for exec_st : execute_stage use entity work.execute_stage(behav);
+    end for;
+    for writeback_st : writeback_stage use entity work.writeback_stage(behav);
+    end for;
 
   end for;
 end pipeline_conf_beh;

diff --git a/cpu/src/writeback_stage.vhd b/cpu/src/writeback_stage.vhd
index 7d6e3c2abe68ba3c671af34ebc2e0b711782cd10..256fa55783fb168781b568c4a31da661958a7cae 100644 (file)
--- a/cpu/src/writeback_stage.vhd
+++ b/cpu/src/writeback_stage.vhd
@@ -2,13 +2,15 @@ library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 
+use work.common_pkg.all;
+
 entity writeback_stage is
 
        generic (
                        -- active reset value
                        RESET_VALUE : std_logic;
                        -- active logic value
-                       LOGIC_ACT : std_logic;
+                       LOGIC_ACT : std_logic
                        
                        );
        port(

diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd
index eb09e1e5e7ba8c7ca3f44fa32003f5ab1dafc04f..94af88c05e09567d340993b4150934620b50330e 100644 (file)
--- a/cpu/src/writeback_stage_b.vhd
+++ b/cpu/src/writeback_stage_b.vhd
@@ -2,34 +2,38 @@ library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 
+use work.common_pkg.all;
 use work.core_pkg.all;
 
-architecture behav of writeback_stage is
+use work.mem_pkg.all;
 
+architecture behav of writeback_stage is
 
-begin
 
 signal data_ram_read : word_t;
 
 signal wb_reg, wb_reg_nxt : writeback_rec;
 
+begin
+
+
        data_ram : r_w_ram
                generic map (
-                       PHYS_DATA_ADDR_WIDTH,
+                       DATA_ADDR_WIDTH,
                        WORD_WIDTH
                )
                
                port map (
                        clk,
-                       wb_reg_nxt.address(PHYS_DATA_ADDR_WIDTH+1 downto 2),
-                       wb_reg_nxt.address(PHYS_DATA_ADDR_WIDTH+1 downto 2),
+                       wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 2),
+                       wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 2),
                        wb_reg_nxt.dmem_write_en,
                        ram_data,
                        data_ram_read
                );
 
 
-syn: process(sys_clk, reset)
+syn: process(clk, reset)
 
 begin
 
@@ -39,7 +43,7 @@ begin
                wb_reg_nxt.dmem_write_en <= '0';
                wb_reg_nxt.hword <= '0';
                wb_reg_nxt.byte_s <= '0';
-       elsif rising_edge(sys_clk) then
+       elsif rising_edge(clk) then
                wb_reg <= wb_reg_nxt;
        end if;
        
@@ -54,7 +58,7 @@ end process;
 
 
 
-shift_input: process(data_ram_read, address, dmem_en, dmem_write_en, hword_hl, wb_reg, result)
+shift_input: process(data_ram_read, address, dmem_en, dmem_write_en, hword, wb_reg, result)
 
 begin
        wb_reg_nxt.address <= address;
@@ -82,6 +86,7 @@ begin
                                when "01" => regfile_val(7 downto 0) <= data_ram_read(15 downto 8);
                                when "10" => regfile_val(7 downto 0) <= data_ram_read(23 downto 16);
                                when "11" => regfile_val(7 downto 0) <= data_ram_read(31 downto 24);
+                               when others => null;
                        end case;
                end if; 
        end if;