added pipe 2 reg, testbench, top_level_entity, ...

diff --git a/cpu/sim/testcore.do b/cpu/sim/testcore.do
index 8682728cf91a83582a34e48a36992704d6c761cf..da92a48b390eaa2b7cc894f55eb8d925ef31251c 100644 (file)
--- a/cpu/sim/testcore.do
+++ b/cpu/sim/testcore.do
@@ -27,6 +27,7 @@ add wave  -radix hexadecimal /pipeline_tb/fetch_st/prediction_result
 
 add wave  -radix hexadecimal /pipeline_tb/decode_st/instruction
 add wave  -radix hexadecimal /pipeline_tb/decode_st/instr_spl
+add wave  -radix hexadecimal /pipeline_tb/decode_st/to_next_stage
 add wave  -radix hexadecimal /pipeline_tb/decode_st/reg1_mem_data
 add wave  -radix hexadecimal /pipeline_tb/decode_st/reg2_mem_data
 add wave  -radix hexadecimal /pipeline_tb/decode_st/rtw_rec

diff --git a/cpu/src/common_pkg.vhd b/cpu/src/common_pkg.vhd
index 1dca19632fab15a7625d759cf73a44a7c598eb4d..0e76f83f8e7e26f44b19fe62a9a3a87824026107 100755 (executable)
--- a/cpu/src/common_pkg.vhd
+++ b/cpu/src/common_pkg.vhd
@@ -49,11 +49,11 @@ package common_pkg is
        constant IMM_OPT : integer := 0; -- no sharing
        
        constant SUB_OPT : integer := 1;
-       constant LOG_OPT : integer := 1;
+       constant ARITH_OPT : integer := 1;
        
        constant CARRY_OPT : integer := 2;
        
-       constant LEFT_OPT : integer := 3;
+       constant RIGHT_OPT : integer := 3;
        
        constant NO_PSW_OPT : integer := 4;--no sharing
        constant NO_DST_OPT : integer := 5; --no sharing
@@ -73,13 +73,15 @@ package common_pkg is
                reg_src2_addr : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
 
                immediate : std_logic_vector(WORD_WIDTH-1 downto 0);
+--             immediate_set : std_logic;
                displacement : std_logic_vector(DISPL_WIDTH-1 downto 0);
 
                jmptype : std_logic_vector(1 downto 0);
 
-               carry, sreg_update, high_low, fill, signext, bp, arith, left_right : std_logic;
+               high_low, fill, signext, bp: std_logic;
 
-               op_detail : op_pot_t;
+               op_detail : op_opt_t;
+               op_group : op_info_t;
 
        end record;
 
@@ -90,6 +92,7 @@ package common_pkg is
                rtw_reg1 : std_logic;
                rtw_reg2 : std_logic;
                immediate : gp_register_t;
+               imm_set : std_logic;
 
        end record;
 

diff --git a/cpu/src/core_pkg.vhd b/cpu/src/core_pkg.vhd
index 335ffb6876eec9f85eb5eb2d1515d1522052c8b5..3f916fb3d3701906df26a56e0aaafac3ba85497f 100644 (file)
--- a/cpu/src/core_pkg.vhd
+++ b/cpu/src/core_pkg.vhd
@@ -54,10 +54,11 @@ package core_pkg is
                        reg_we : in std_logic;
 
                --Data outputs
-                       reg1_rd_data : out gp_register_t;
-                       reg2_rd_data : out gp_register_t;
+--                     reg1_rd_data : out gp_register_t;
+--                     reg2_rd_data : out gp_register_t;
                        branch_prediction_res : out instruction_word_t;
-                       branch_prediction_bit : out std_logic
+                       branch_prediction_bit : out std_logic;
+                       to_next_stage : out dec_op
                );
        end component decode_stage;
 

diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd
index a63616049cfa6dec151ab3649c00edda0cc505e9..7ec0743961062e2158db09df3d6cbbe669e657e8 100644 (file)
--- a/cpu/src/core_top.vhd
+++ b/cpu/src/core_top.vhd
@@ -11,9 +11,8 @@ entity core_top is
                --System input pins
                        sys_clk : in std_logic;
                        sys_res : in std_logic;
-                       reg1_rd_data : out gp_register_t;
-                       reg2_rd_data : out gp_register_t
 
+                       to_next_stage : out dec_op
                        
                );
 
@@ -30,6 +29,7 @@ architecture behav of core_top is
                signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
                signal reg_wr_data_pin : gp_register_t;
                signal reg_we_pin : std_logic;
+
 --             signal reg1_rd_data_pin : gp_register_t;
 --             signal reg2_rd_data_pin : gp_register_t;
 
@@ -78,11 +78,9 @@ begin
                        reg_we => reg_we_pin, --: in std_logic;
 
                --Data outputs
-                       reg1_rd_data => reg1_rd_data, --: gp_register_t;
-                       reg2_rd_data => reg2_rd_data, --: gp_register_t;
                        branch_prediction_res => prediction_result_pin, --: instruction_word_t;
-                       branch_prediction_bit => branch_prediction_bit_pin --: std_logic
-                       
+                       branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
+                       to_next_stage => to_next_stage
                );
 
                

diff --git a/cpu/src/decode_stage.vhd b/cpu/src/decode_stage.vhd
index 2b0cf49a62513e8c4060c39d4afca6ba2011977f..103822cb0463fef2d39433f637a01e5db047bede 100644 (file)
--- a/cpu/src/decode_stage.vhd
+++ b/cpu/src/decode_stage.vhd
@@ -27,10 +27,12 @@ entity decode_stage is
                        reg_we : in std_logic;
 
                --Data outputs
-                       reg1_rd_data : out gp_register_t;
-                       reg2_rd_data : out gp_register_t;
+--                     reg1_rd_data : out gp_register_t;
+--                     reg2_rd_data : out gp_register_t;
                        branch_prediction_res : out instruction_word_t;
-                       branch_prediction_bit : out std_logic
+                       branch_prediction_bit : out std_logic;
+
+                       to_next_stage : out dec_op
                        
                );
                

diff --git a/cpu/src/decode_stage_b.vhd b/cpu/src/decode_stage_b.vhd
index 54cf7284440f736dfcac200da4bf006ddb3944cd..fbaf0101d7804730f7ff60632e9fdae7f44dc765 100644 (file)
--- a/cpu/src/decode_stage_b.vhd
+++ b/cpu/src/decode_stage_b.vhd
@@ -13,7 +13,9 @@ architecture behav of decode_stage is
 signal instr_spl : instruction_rec;
 
 signal rtw_rec, rtw_rec_nxt : read_through_write_rec;
-signal reg1_mem_data, reg2_mem_data : gp_register_t;
+signal reg1_mem_data, reg2_mem_data, reg1_rd_data, reg2_rd_data : gp_register_t;
+signal dec_op_inst, dec_op_inst_nxt : dec_op;
+
 
 begin
 
@@ -52,13 +54,26 @@ begin
                rtw_rec.rtw_reg <= (others => '0');
                rtw_rec.rtw_reg1 <= '0';
                rtw_rec.rtw_reg2 <= '0';
+               rtw_rec.immediate <= (others => '0');
+               rtw_rec.imm_set <= '0';
+
+               dec_op_inst.condition <= (others => '0');
+               dec_op_inst.op_detail <= (others => '0');
+               dec_op_inst.brpr <= '0'; --branch_prediction_bit;
+               dec_op_inst.src1 <= (others => '0');
+               dec_op_inst.src2 <= (others => '0');
+               dec_op_inst.saddr1 <= (others => '0');
+               dec_op_inst.saddr2 <= (others => '0');
+               dec_op_inst.daddr <= (others => '0');
+
+
        elsif rising_edge(clk) then
                rtw_rec <= rtw_rec_nxt;
+               dec_op_inst <= dec_op_inst_nxt;
        end if;
        
 end process; 
 
-
 --     type dec_op is record
 --             condition : condition_t;
 --             op_group : op_info_t;
@@ -75,10 +90,30 @@ end process;
 --             
 --     end record;
 
-to_alu: process(instr_spl)
+-- output logic incl. bypassing reg-file
+output_next_stage: process(dec_op_inst, reg1_rd_data, reg2_rd_data)
 
 begin
 
+       to_next_stage <= dec_op_inst;
+       to_next_stage.src1 <= reg1_rd_data;
+       to_next_stage.src2 <= reg2_rd_data;
+
+end process;
+
+
+-- fills output register
+to_next: process(instr_spl)
+
+begin
+       dec_op_inst_nxt.condition <= instr_spl.predicates;
+       dec_op_inst_nxt.op_detail <= instr_spl.op_detail;
+       dec_op_inst_nxt.brpr <= instr_spl.bp; --branch_prediction_bit;
+       dec_op_inst_nxt.src1 <= (others => '0');
+       dec_op_inst_nxt.src2 <= (others => '0');
+       dec_op_inst_nxt.saddr1 <= instr_spl.reg_src1_addr;
+       dec_op_inst_nxt.saddr2 <= instr_spl.reg_src2_addr;
+       dec_op_inst_nxt.daddr <= (others => '0');
 
 end process;
 
@@ -97,26 +132,35 @@ begin
        else
                reg2_rd_data <= reg2_mem_data;
        end if;
+
+       if (rtw_rec.imm_set = '1') then
+               reg2_rd_data <= rtw_rec.immediate;
+       end if;
 end process;
 
 
 -- async process: checks forward condition
-forward: process(instr_spl, reg_w_addr, reg_wr_data)
+forward: process(instr_spl, reg_w_addr, reg_wr_data, reg_we)
 
 begin
 
        rtw_rec_nxt.rtw_reg <= reg_wr_data;
        rtw_rec_nxt.rtw_reg1 <= '0';
        rtw_rec_nxt.rtw_reg2 <= '0';
+       rtw_rec_nxt.immediate <= (others => '0');
+       rtw_rec_nxt.imm_set <= '0';
 
-       rtw_rec_nxt.immediate <= instr_spl.immediate;
+       if (instr_spl.op_detail(IMM_OPT) = '1') then
+               rtw_rec_nxt.immediate <= instr_spl.immediate;
+               rtw_rec_nxt.imm_set <= '1';
+       end if;
 
        if (reg_w_addr = instr_spl.reg_src1_addr) then
-               rtw_rec_nxt.rtw_reg1 <= '1';
+               rtw_rec_nxt.rtw_reg1 <= ('1' and reg_we);
        end if;
 
        if (reg_w_addr = instr_spl.reg_src2_addr) then
-               rtw_rec_nxt.rtw_reg2 <= '1';
+               rtw_rec_nxt.rtw_reg2 <= ('1' and reg_we);
        end if;
 
 end process;

diff --git a/cpu/src/decoder_b.vhd b/cpu/src/decoder_b.vhd
index 9e043b2a8a80488e67fab0c20f5c31947b368117..2585165aca1792ea8ce914980488aff231d73ab0 100644 (file)
--- a/cpu/src/decoder_b.vhd
+++ b/cpu/src/decoder_b.vhd
@@ -27,15 +27,16 @@ begin
        instr_s.immediate := (others => '0');
        instr_s.displacement := (others => '0');
        instr_s.jmptype := (others => '0');
-       instr_s.carry := '0';
-       instr_s.sreg_update := '0';
        instr_s.high_low := '0';
        instr_s.fill := '0';
        instr_s.signext := '0';
        instr_s.bp := '0';
-       instr_s.arith := '0';
        instr_s.op_detail := (others => '0');
 
+       instr_s.op_group := ADDSUB_OP;
+
+--     type op_info_t is (ADDSUB_OP,AND_OP,OR_OP, XOR_OP,SHIFT_OP);
+
 --  special function register operations missing
 
 --     case opcode is
@@ -45,11 +46,11 @@ begin
                instr_s.reg_dest_addr := instruction(22 downto 19);
                instr_s.reg_src1_addr := instruction(18 downto 15);
                instr_s.reg_src2_addr := instruction(14 downto 11);
-               instr_s.carry := instruction(1);
-               instr_s.sreg_update := instruction(0);
 
                instr_s.op_detail(NO_PSW_OPT) := instruction(0); --instr_s.sreg_update;
                
+               instr_s.op_group := ADDSUB_OP;
+
                if (instr_s.opcode = "00000") then              
                        instr_s.op_detail(CARRY_OPT) := instruction(1); --instr_s.carry;
                end if;
@@ -58,6 +59,19 @@ begin
                        instr_s.op_detail(SUB_OPT) := '1';
                        instr_s.op_detail(CARRY_OPT) := instruction(1); --instr_s.carry;
                end if;
+
+               if (instr_s.opcode = "00100") then
+                       instr_s.op_group := AND_OP;
+               end if;
+               
+               if (instr_s.opcode = "00110") then
+                       instr_s.op_group := OR_OP;
+               end if;
+               
+               if (instr_s.opcode = "01000") then
+                       instr_s.op_group := XOR_OP;
+               end if;
+
        end if;
 --     when "00001" =>         --sub
 --             instr_s.reg_dest_addr := instruction(22 downto 19);
@@ -96,8 +110,6 @@ begin
                instr_s.reg_src1_addr := instruction(18 downto 15);
                instr_s.immediate(11 downto 0) := instruction(14 downto 3);
                instr_s.signext := instruction(2);              
-               instr_s.carry := instruction(1);
-               instr_s.sreg_update := instruction(0);
 
                if (instr_s.signext = '1' and instr_s.immediate(11) = '1') then
                        instr_s.immediate(31 downto 12) := (others => '1');
@@ -107,6 +119,8 @@ begin
                instr_s.op_detail(CARRY_OPT) := instruction(1);
                instr_s.op_detail(NO_PSW_OPT) := instruction(0);
 
+               instr_s.op_group := ADDSUB_OP;
+
                if (instr_s.opcode = "00011") then
                        instr_s.op_detail(SUB_OPT) := '1';
                end if;
@@ -132,7 +146,6 @@ begin
                instr_s.immediate(15 downto 0) := instruction(18 downto 3);
                instr_s.high_low := instruction(2);             
                instr_s.fill := instruction(1);
-               instr_s.sreg_update := instruction(0);
 
                if (instr_s.fill = '1') then
                        instr_s.immediate(31 downto 16) := (others => '1');
@@ -140,6 +153,18 @@ begin
 
                instr_s.op_detail(IMM_OPT) := '1';
                instr_s.op_detail(NO_PSW_OPT) := instruction(0);
+
+               if (instr_s.opcode = "00111") then
+                       instr_s.op_group := AND_OP;
+               end if;
+
+               if (instr_s.opcode = "00111") then
+                       instr_s.op_group := OR_OP;
+               end if;
+
+               if (instr_s.opcode = "01001") then
+                       instr_s.op_group := XOR_OP;
+               end if;
        end if;
 
 --     when "00111" =>         --orx
@@ -165,15 +190,14 @@ begin
                instr_s.reg_dest_addr := instruction(22 downto 19);
                instr_s.reg_src1_addr := instruction(18 downto 15);
                instr_s.immediate(4 downto 0) := instruction(14 downto 10);
-               instr_s.left_right := instruction(3);           
-               instr_s.arith := instruction(2);                
-               instr_s.carry := instruction(1);
-               instr_s.sreg_update := instruction(0);
 
                instr_s.op_detail(RIGHT_OPT) := instruction(3);
                instr_s.op_detail(NO_PSW_OPT) := instruction(0);
                instr_s.op_detail(CARRY_OPT) := instruction(1);
                instr_s.op_detail(ARITH_OPT) := instruction(2);
+               instr_s.op_detail(IMM_OPT) := '1';
+
+               instr_s.op_group := SHIFT_OP;
        end if;
 
 --     when "01011" =>         --stackop

diff --git a/cpu/src/exec_op/add_op_b.vhd b/cpu/src/exec_op/add_op_b.vhd
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/cpu/src/exec_op/and_op_b.vhd b/cpu/src/exec_op/and_op_b.vhd
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/cpu/src/exec_op/or_op_b.vhd b/cpu/src/exec_op/or_op_b.vhd
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/cpu/src/exec_op/shift_op_b.vhd b/cpu/src/exec_op/shift_op_b.vhd
old mode 100755 (executable)
new mode 100644 (file)
index 0b5a73c..f0acce6
--- a/cpu/src/exec_op/shift_op_b.vhd
+++ b/cpu/src/exec_op/shift_op_b.vhd
@@ -11,8 +11,8 @@ architecture shift_op of exec_op is
 
 begin
 
-       logic <=  op_detail(LOG_OPT);
-       ls      <=  op_detail(LEFT_OPT);
+       logic <=  op_detail(ARITH_OPT);
+       ls      <=  op_detail(RIGHT_OPT);
        carry <= op_detail(CARRY_OPT);
 
 calc: process(left_operand, right_operand, logic,ls, carry, alu_state)

diff --git a/cpu/src/exec_op/xor_op_b.vhd b/cpu/src/exec_op/xor_op_b.vhd
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/cpu/src/pipeline_tb.vhd b/cpu/src/pipeline_tb.vhd
index 43c0c9870e000ab33017c0101a2e2c13ab3094ec..e856e69ec98343498a5a36bc4c5846c24a22a541 100644 (file)
--- a/cpu/src/pipeline_tb.vhd
+++ b/cpu/src/pipeline_tb.vhd
@@ -35,9 +35,7 @@ architecture behavior of pipeline_tb is
                signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
                signal reg_wr_data_pin : gp_register_t;
                signal reg_we_pin : std_logic;
-               signal reg1_rd_data_pin : gp_register_t;
-               signal reg2_rd_data_pin : gp_register_t;
-
+               signal to_next_stage_pin : dec_op;
 
 begin
 
@@ -98,10 +96,9 @@ begin
                        reg_we => reg_we_pin, --: in std_logic;
 
                --Data outputs
-                       reg1_rd_data => reg1_rd_data_pin, --: gp_register_t;
-                       reg2_rd_data => reg2_rd_data_pin, --: gp_register_t;
                        branch_prediction_res => prediction_result_pin, --: instruction_word_t;
-                       branch_prediction_bit => branch_prediction_bit_pin --: std_logic
+                       branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
+                       to_next_stage => to_next_stage_pin
                        
                );