forward unit testcases (from assignments), everything works fine!

diff --git a/cpu/src/r2_w_ram_b.vhd b/cpu/src/r2_w_ram_b.vhd
index c20c8b14ef5ed12e87e6f2b625f993b8ec3e3996..64c8da4e21f0ca689be0f3853d5acddfbcc893b3 100644 (file)
--- a/cpu/src/r2_w_ram_b.vhd
+++ b/cpu/src/r2_w_ram_b.vhd
@@ -12,9 +12,9 @@ architecture behaviour of r2_w_ram is
        
        signal ram : RAM_TYPE := (
                                0 => x"00000000",
-                               1 => x"00000001",
-                               2 => x"0000000A",
-                               3 => x"00000003",
+                               1 => x"00000000",
+                               2 => x"00000000",
+                               3 => x"00000000",
                                others=> (others => '0'));
 
 begin

diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd
index 7962706065a70e3c1d16a668b292ddb4c19c4aff..4f1a0e0e8d8080bf4ea0e40e91ca9e46c06873fb 100644 (file)
--- a/cpu/src/r_w_ram_b.vhd
+++ b/cpu/src/r_w_ram_b.vhd
@@ -12,28 +12,35 @@ architecture behaviour of r_w_ram is
        
                                                                        -- r0 = 0, r1 = 1, r2 = 3, r3 = A
 
-       signal ram : RAM_TYPE := (  0 => "11100000000100001000000000000000", --add r2, r1, r0    => r2 = 1
-                                   1 => "11100000000110001000000000000000", --add r3, r1, r0    => r3 = 1
-                                   2 => "11100000001000011001000000000000", --add r4, r3, r2    => r4 = 2
-                                   3 => "11100000000100001000000000000000", --add r2, r1, r0    => r2 = 1
-                                   4 => "11100000000110001000000000000000", --add r3, r1, r0    => r3 = 1
-                                   5 => "11100000001000011001000000000000", --add r4, r3, r2    => r4 = 2
-                                   6 => "11101100000000001000000000000000", --cmp r0 , r1       => 0-1 => 0100
-                                   7 => "00000000001010101010000000000001", --addnqd r5, r5, r4 => r5 = 2
-                                   8 => "00000000001010101010000000000000", --addnq r5, r5, r4  => r5 = 4
-                                   9 => "11101100001000100000000000000000", --cmp r4 , r4       => 2-2 => 1001
-                                  10 => "00000001001100001000000001010000", --addinq r6, r1, 0xA => nix
-                                  11 => "00010001001100001000000001010000", --addieq r6, r1, 0xA => r6 = 0xB
-                                  12 => "00010001101100110000000001010000", --subieq r6, r5, 0xA => r6 = 1
-                                  13 => "11100000000100001000000000000000", --add r2, r1, r0     => r2 = 1
-                                  14 => "11100010000100001000000000000000", --and r2, r1, r0     => r2 = 0
-                                  15 => "11101100000000001000000000000000", --cmp r0 , r1        => 0-1 => 0100
-                                  16 => "10000000001010101010000000000001", --addabd r5, r5, r4  => r5 = 6
-                                  17 => "10110011101110001000010000110001", --orxltd r7, 1086    => r7 = 1086
-                                  18 => "10110101001110001000010000000001", --shiftltd r7, r1, 1 => r7 = 2
-                                  19 => "01010101001110001000100000000001", --shiftltd r7, r1, 2 => r7 = 4
+       signal ram : RAM_TYPE := (  0 => "11100001000010001000000000111000", -- r1 = 7
+                                   1 => "11100001000100010000000000101000", -- r2 = 5
+                                   2 => "11100001000110011000000000100000", -- r3 = 4
+                                   3 => "11100000001000010001100000000000", -- r4 = r2 + r3
+                                   4 => "11100010001010100000100000000000", -- r5 = r4 and r1
                                  others => x"F0000000");
 
+--     signal ram : RAM_TYPE := (  0 => "11100000000100001000000000000000", --add r2, r1, r0    => r2 = 1
+--                                 1 => "11100000000110001000000000000000", --add r3, r1, r0    => r3 = 1
+--                                 2 => "11100000001000011001000000000000", --add r4, r3, r2    => r4 = 2
+--                                 3 => "11100000000100001000000000000000", --add r2, r1, r0    => r2 = 1
+--                                 4 => "11100000000110001000000000000000", --add r3, r1, r0    => r3 = 1
+--                                 5 => "11100000001000011001000000000000", --add r4, r3, r2    => r4 = 2
+--                                 6 => "11101100000000001000000000000000", --cmp r0 , r1       => 0-1 => 0100
+--                                 7 => "00000000001010101010000000000001", --addnqd r5, r5, r4 => r5 = 2
+--                                 8 => "00000000001010101010000000000000", --addnq r5, r5, r4  => r5 = 4
+--                                 9 => "11101100001000100000000000000000", --cmp r4 , r4       => 2-2 => 1001
+--                                10 => "00000001001100001000000001010000", --addinq r6, r1, 0xA => nix
+--                                11 => "00010001001100001000000001010000", --addieq r6, r1, 0xA => r6 = 0xB
+--                                12 => "00010001101100110000000001010000", --subieq r6, r5, 0xA => r6 = 1
+--                                13 => "11100000000100001000000000000000", --add r2, r1, r0     => r2 = 1
+--                                14 => "11100010000100001000000000000000", --and r2, r1, r0     => r2 = 0
+--                                15 => "11101100000000001000000000000000", --cmp r0 , r1        => 0-1 => 0100
+--                                16 => "10000000001010101010000000000001", --addabd r5, r5, r4  => r5 = 6
+--                                17 => "10110011101110001000010000110001", --orxltd r7, 1086    => r7 = 1086
+--                                18 => "10110101001110001000010000000001", --shiftltd r7, r1, 1 => r7 = 2
+--                                19 => "01010101001110001000100000000001", --shiftltd r7, r1, 2 => r7 = 4
+--                               others => x"F0000000");
+
 
 begin
        process(clk)