pipe2

diff --git a/cpu/src/common_pkg.vhd b/cpu/src/common_pkg.vhd
index 9398fb2cc705aff06990e5a76dca8578ef43a363..1dca19632fab15a7625d759cf73a44a7c598eb4d 100755 (executable)
--- a/cpu/src/common_pkg.vhd
+++ b/cpu/src/common_pkg.vhd
@@ -35,7 +35,7 @@ package common_pkg is
        subtype instruction_word_t is std_logic_vector(WORD_WIDTH-1 downto 0);
        subtype instruction_addr_t is std_logic_vector(INSTR_ADDR_WIDTH-1 downto 0);
        
-       subtype gp_addr_t       is unsigned(REG_ADDR_WIDTH-1 downto 0);
+       subtype gp_addr_t       is std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
        subtype data_ram_word_t is std_logic_vector(WORD_WIDTH-1 downto 0);
        subtype data_ram_addr_t is std_logic_vector(DATA_ADDR_WIDTH-1 downto 0);
 
@@ -79,6 +79,8 @@ package common_pkg is
 
                carry, sreg_update, high_low, fill, signext, bp, arith, left_right : std_logic;
 
+               op_detail : op_pot_t;
+
        end record;
 
 
@@ -87,6 +89,7 @@ package common_pkg is
                rtw_reg : gp_register_t;
                rtw_reg1 : std_logic;
                rtw_reg2 : std_logic;
+               immediate : gp_register_t;
 
        end record;
 

diff --git a/cpu/src/decode_stage_b.vhd b/cpu/src/decode_stage_b.vhd
index 28c04c35aaf5aa0353af073505d90f28ffba4476..54cf7284440f736dfcac200da4bf006ddb3944cd 100644 (file)
--- a/cpu/src/decode_stage_b.vhd
+++ b/cpu/src/decode_stage_b.vhd
@@ -8,7 +8,6 @@ use work.core_pkg.all;
 use work.common_pkg.all;
 
 
-
 architecture behav of decode_stage is
 
 signal instr_spl : instruction_rec;
@@ -60,6 +59,29 @@ begin
 end process; 
 
 
+--     type dec_op is record
+--             condition : condition_t;
+--             op_group : op_info_t;
+--             op_detail : op_opt_t;
+--             brpr : std_logic;
+--             
+--             src1 : gp_register_t;
+--             src2 : gp_register_t;
+--             
+--             saddr1 : gp_addr_t;
+--             saddr2 : gp_addr_t;
+--             
+--             daddr   : gp_addr_t;
+--             
+--     end record;
+
+to_alu: process(instr_spl)
+
+begin
+
+
+end process;
+
 -- async process: decides between memory and read-through-write buffer on output
 output: process(rtw_rec, reg1_mem_data, reg2_mem_data)
 
@@ -87,6 +109,8 @@ begin
        rtw_rec_nxt.rtw_reg1 <= '0';
        rtw_rec_nxt.rtw_reg2 <= '0';
 
+       rtw_rec_nxt.immediate <= instr_spl.immediate;
+
        if (reg_w_addr = instr_spl.reg_src1_addr) then
                rtw_rec_nxt.rtw_reg1 <= '1';
        end if;

diff --git a/cpu/src/decoder_b.vhd b/cpu/src/decoder_b.vhd
index 1804811a9efac1583bd20e450b6c0d1afe32b734..9e043b2a8a80488e67fab0c20f5c31947b368117 100644 (file)
--- a/cpu/src/decoder_b.vhd
+++ b/cpu/src/decoder_b.vhd
@@ -34,6 +34,7 @@ begin
        instr_s.signext := '0';
        instr_s.bp := '0';
        instr_s.arith := '0';
+       instr_s.op_detail := (others => '0');
 
 --  special function register operations missing
 
@@ -46,6 +47,17 @@ begin
                instr_s.reg_src2_addr := instruction(14 downto 11);
                instr_s.carry := instruction(1);
                instr_s.sreg_update := instruction(0);
+
+               instr_s.op_detail(NO_PSW_OPT) := instruction(0); --instr_s.sreg_update;
+               
+               if (instr_s.opcode = "00000") then              
+                       instr_s.op_detail(CARRY_OPT) := instruction(1); --instr_s.carry;
+               end if;
+
+               if (instr_s.opcode = "00001") then
+                       instr_s.op_detail(SUB_OPT) := '1';
+                       instr_s.op_detail(CARRY_OPT) := instruction(1); --instr_s.carry;
+               end if;
        end if;
 --     when "00001" =>         --sub
 --             instr_s.reg_dest_addr := instruction(22 downto 19);
@@ -90,8 +102,15 @@ begin
                if (instr_s.signext = '1' and instr_s.immediate(11) = '1') then
                        instr_s.immediate(31 downto 12) := (others => '1');
                end if;
-       end if;
 
+               instr_s.op_detail(IMM_OPT) := '1';
+               instr_s.op_detail(CARRY_OPT) := instruction(1);
+               instr_s.op_detail(NO_PSW_OPT) := instruction(0);
+
+               if (instr_s.opcode = "00011") then
+                       instr_s.op_detail(SUB_OPT) := '1';
+               end if;
+       end if;
 
 --     when "00011" =>         --subi
 --             instr_s.reg_dest_addr := instruction(22 downto 19);
@@ -114,6 +133,13 @@ begin
                instr_s.high_low := instruction(2);             
                instr_s.fill := instruction(1);
                instr_s.sreg_update := instruction(0);
+
+               if (instr_s.fill = '1') then
+                       instr_s.immediate(31 downto 16) := (others => '1');
+               end if;
+
+               instr_s.op_detail(IMM_OPT) := '1';
+               instr_s.op_detail(NO_PSW_OPT) := instruction(0);
        end if;
 
 --     when "00111" =>         --orx
@@ -143,6 +169,11 @@ begin
                instr_s.arith := instruction(2);                
                instr_s.carry := instruction(1);
                instr_s.sreg_update := instruction(0);
+
+               instr_s.op_detail(RIGHT_OPT) := instruction(3);
+               instr_s.op_detail(NO_PSW_OPT) := instruction(0);
+               instr_s.op_detail(CARRY_OPT) := instruction(1);
+               instr_s.op_detail(ARITH_OPT) := instruction(2);
        end if;
 
 --     when "01011" =>         --stackop
@@ -165,8 +196,11 @@ begin
                instr_s.signext := instruction(2);
                instr_s.high_low := instruction(1);
 
-               if (instr_s.signext = '1' and instr_s.immediate(11) = '1') then
-                       instr_s.immediate(31 downto 16) := (others => '1');
+               if (instr_s.opcode = "11010") then
+                       if (instr_s.signext = '1' and instr_s.immediate(11) = '1') then
+                               instr_s.immediate(31 downto 16) := (others => '1');
+                       end if;
+                       instr_s.op_detail(IMM_OPT) := '1';
                end if;
        end if;
 
@@ -242,7 +276,18 @@ begin
 --     when "11000" =>         --cmp
                instr_s.reg_src1_addr := instruction(22 downto 19);
                instr_s.reg_src2_addr := instruction(18 downto 15);
-               instr_s.immediate(15 downto 0) := instruction(18 downto 3);
+
+               if (instr_s.opcode = "11001") then
+                       instr_s.immediate(15 downto 0) := instruction(18 downto 3);
+                       instr_s.signext := instruction(2);              
+
+                       if (instr_s.signext = '1' and instr_s.immediate(15) = '1') then
+                               instr_s.immediate(31 downto 16) := (others => '1');
+                       end if;
+
+                       instr_s.op_detail(IMM_OPT) := '1';
+               end if;
+
        end if;
 
 --     when "11001" =>         --cmpi

diff --git a/cpu/src/exec_op/add_op_b.vhd b/cpu/src/exec_op/add_op_b.vhd
index e3d62c6b52dc4d7b662497ebe5c88c925be99964..919c795d23a76eae9f9149eae22dda568226ddec 100755 (executable)
--- a/cpu/src/exec_op/add_op_b.vhd
+++ b/cpu/src/exec_op/add_op_b.vhd
@@ -1,61 +1,61 @@
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-use IEEE.numeric_std.all;\r
-\r
-use work.common_pkg.all;\r
-use work.alu_pkg.all;\r
-\r
-architecture add_op of exec_op is\r
-\r
-signal sub, addc : std_logic;\r
-\r
-begin\r
-\r
-sub <= op_detail(SUB_OPT);\r
-addc <= op_detail(CARRY_OPT);\r
-\r
-calc: process(left_operand, right_operand, alu_state, sub, addc)\r
-       variable alu_result_v : alu_result_rec;\r
-       variable complement             : gp_register_t;\r
-       variable carry_res              : unsigned(gp_register_t'length downto 0);\r
-       variable tmp_right_operand : unsigned(gp_register_t'length downto 0);\r
-       variable oflo1, oflo2, l_neg, r_neg : std_logic;\r
-       variable addcarry               : unsigned(carry_res'range);\r
-begin\r
-               alu_result_v := alu_state;\r
-               \r
-               addcarry := (others =>'0');\r
-               addcarry(0) := alu_state.status.carry and addc;\r
-               \r
-               complement := inc(not(right_operand));\r
-               l_neg := left_operand(gp_register_t'high);\r
-               \r
-               carry_res := unsigned('0' & left_operand)+addcarry;\r
-               oflo1 := add_oflo(l_neg,'0',std_logic_vector(carry_res)(gp_register_t'high));\r
-               \r
-               if sub = '1' then\r
-                       tmp_right_operand := unsigned('0' & complement);\r
-               else\r
-                       tmp_right_operand := unsigned('0' & right_operand);\r
-               end if;\r
-               \r
-               l_neg := std_logic_vector(carry_res)(gp_register_t'high);\r
-               r_neg := std_logic_vector(tmp_right_operand)(gp_register_t'high);\r
-               \r
-               carry_res := carry_res + tmp_right_operand;\r
-               oflo2 := add_oflo(l_neg,r_neg,std_logic_vector(carry_res)(gp_register_t'high));\r
-               \r
-\r
-               alu_result_v.result := std_logic_vector(carry_res)(gp_register_t'range);\r
-               alu_result_v.status.carry := std_logic_vector(carry_res)(carry_res'high);\r
-               \r
-               \r
-               alu_result_v.status.carry := oflo1 or oflo2;\r
-               \r
-               --sign will be set globally.\r
-               --zero will be set globally.\r
-               \r
-               alu_result <= alu_result_v;\r
-end process; \r
-\r
-end architecture add_op;\r
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.common_pkg.all;
+use work.alu_pkg.all;
+
+architecture add_op of exec_op is
+
+signal sub, addc : std_logic;
+
+begin
+
+sub <= op_detail(SUB_OPT);
+addc <= op_detail(CARRY_OPT);
+
+calc: process(left_operand, right_operand, alu_state, sub, addc)
+       variable alu_result_v : alu_result_rec;
+       variable complement             : gp_register_t;
+       variable carry_res              : unsigned(gp_register_t'length downto 0);
+       variable tmp_right_operand : unsigned(gp_register_t'length downto 0);
+       variable oflo1, oflo2, l_neg, r_neg : std_logic;
+       variable addcarry               : unsigned(carry_res'range);
+begin
+               alu_result_v := alu_state;
+               
+               addcarry := (others =>'0');
+               addcarry(0) := alu_state.status.carry and addc;
+               
+               complement := inc(not(right_operand));
+               l_neg := left_operand(gp_register_t'high);
+               
+               carry_res := unsigned('0' & left_operand)+addcarry;
+               oflo1 := add_oflo(l_neg,'0',std_logic_vector(carry_res)(gp_register_t'high));
+               
+               if sub = '1' then
+                       tmp_right_operand := unsigned('0' & complement);
+               else
+                       tmp_right_operand := unsigned('0' & right_operand);
+               end if;
+               
+               l_neg := std_logic_vector(carry_res)(gp_register_t'high);
+               r_neg := std_logic_vector(tmp_right_operand)(gp_register_t'high);
+               
+               carry_res := carry_res + tmp_right_operand;
+               oflo2 := add_oflo(l_neg,r_neg,std_logic_vector(carry_res)(gp_register_t'high));
+               
+
+               alu_result_v.result := std_logic_vector(carry_res)(gp_register_t'range);
+               alu_result_v.status.carry := std_logic_vector(carry_res)(carry_res'high);
+               
+               
+               alu_result_v.status.carry := oflo1 or oflo2;
+               
+               --sign will be set globally.
+               --zero will be set globally.
+               
+               alu_result <= alu_result_v;
+end process; 
+
+end architecture add_op;

diff --git a/cpu/src/exec_op/and_op_b.vhd b/cpu/src/exec_op/and_op_b.vhd
index 05c8f3eb9463ed285a09480b1501a8f1aa99f3e0..6cacc784c8ca477a5d28710086765219ba0ea39d 100755 (executable)
--- a/cpu/src/exec_op/and_op_b.vhd
+++ b/cpu/src/exec_op/and_op_b.vhd
@@ -1,22 +1,22 @@
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-use IEEE.numeric_std.all;\r
-\r
-use work.common_pkg.all;\r
-use work.alu_pkg.all;\r
-\r
-architecture and_op of exec_op is\r
-begin\r
-\r
-calc: process(left_operand, right_operand, alu_state)\r
-       variable alu_result_v : alu_result_rec;\r
-       \r
-begin\r
-               alu_result_v := alu_state;\r
-               \r
-               alu_result_v.result := left_operand and right_operand;\r
-               \r
-               alu_result <= alu_result_v;\r
-end process; \r
-\r
-end architecture and_op;\r
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.common_pkg.all;
+use work.alu_pkg.all;
+
+architecture and_op of exec_op is
+begin
+
+calc: process(left_operand, right_operand, alu_state)
+       variable alu_result_v : alu_result_rec;
+       
+begin
+               alu_result_v := alu_state;
+               
+               alu_result_v.result := left_operand and right_operand;
+               
+               alu_result <= alu_result_v;
+end process; 
+
+end architecture and_op;

diff --git a/cpu/src/exec_op/or_op_b.vhd b/cpu/src/exec_op/or_op_b.vhd
index fbe1ec862baa64c36b880100c559b1cdd91dfa14..bc6784d993022cea1a9f51d1912c23d1cda53b26 100755 (executable)
--- a/cpu/src/exec_op/or_op_b.vhd
+++ b/cpu/src/exec_op/or_op_b.vhd
@@ -1,22 +1,22 @@
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-use IEEE.numeric_std.all;\r
-\r
-use work.common_pkg.all;\r
-use work.alu_pkg.all;\r
-\r
-architecture or_op of exec_op is\r
-begin\r
-\r
-calc: process(left_operand, right_operand, alu_state)\r
-       variable alu_result_v : alu_result_rec;\r
-       \r
-begin\r
-               alu_result_v := alu_state;\r
-               \r
-               alu_result_v.result := left_operand or right_operand;\r
-               \r
-               alu_result <= alu_result_v;\r
-end process; \r
-\r
-end architecture or_op;\r
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.common_pkg.all;
+use work.alu_pkg.all;
+
+architecture or_op of exec_op is
+begin
+
+calc: process(left_operand, right_operand, alu_state)
+       variable alu_result_v : alu_result_rec;
+       
+begin
+               alu_result_v := alu_state;
+               
+               alu_result_v.result := left_operand or right_operand;
+               
+               alu_result <= alu_result_v;
+end process; 
+
+end architecture or_op;

diff --git a/cpu/src/exec_op/shift_op_b.vhd b/cpu/src/exec_op/shift_op_b.vhd
index 291b5902de21c62dce10663a71cbbf624fcaf485..0b5a73cb80bc72677b6bb8dedb511f0b2d509d31 100755 (executable)
--- a/cpu/src/exec_op/shift_op_b.vhd
+++ b/cpu/src/exec_op/shift_op_b.vhd
@@ -1,46 +1,46 @@
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-use IEEE.numeric_std.all;\r
-\r
-use work.common_pkg.all;\r
-use work.alu_pkg.all;\r
-\r
-architecture shift_op of exec_op is\r
-\r
-       signal logic, ls, carry : std_logic;\r
-\r
-begin\r
-\r
-       logic <=  op_detail(LOG_OPT);\r
-       ls      <=  op_detail(LEFT_OPT);\r
-       carry <= op_detail(CARRY_OPT);\r
-\r
-calc: process(left_operand, right_operand, logic,ls, carry, alu_state)\r
-               variable alu_result_v : alu_result_rec;\r
-               variable tmp_shift : bit_vector(gp_register_t'length+1 downto 0);\r
-               variable tmp_sb : std_logic;\r
-       begin\r
-               alu_result_v := alu_state;\r
-               \r
-               if ls = '1' then\r
-                       tmp_sb := (carry and alu_state.status.carry and logic);\r
-                       tmp_shift :=  to_bitvector(alu_state.status.carry & left_operand & tmp_sb);\r
-                       tmp_shift :=  tmp_shift sla to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0));\r
-                       \r
-                       alu_result_v.status.carry := to_stdlogicvector(tmp_shift)(tmp_shift'high);\r
-                       \r
-               else\r
-                       tmp_sb := (carry and alu_state.status.carry and logic) or (not(logic) and left_operand(gp_register_t'high));\r
-                       tmp_shift := to_bitvector(tmp_sb & left_operand & alu_state.status.carry);\r
-                       tmp_shift := tmp_shift sra to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0));\r
-                       \r
-                       alu_result_v.status.carry := to_stdlogicvector(tmp_shift)(0);\r
-               end if;\r
-               \r
-               alu_result_v.result := to_stdlogicvector(tmp_shift)(gp_register_t'length downto 1);\r
-               \r
-               alu_result <= alu_result_v;\r
-               \r
-end process;\r
-\r
-end architecture shift_op;\r
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.common_pkg.all;
+use work.alu_pkg.all;
+
+architecture shift_op of exec_op is
+
+       signal logic, ls, carry : std_logic;
+
+begin
+
+       logic <=  op_detail(LOG_OPT);
+       ls      <=  op_detail(LEFT_OPT);
+       carry <= op_detail(CARRY_OPT);
+
+calc: process(left_operand, right_operand, logic,ls, carry, alu_state)
+               variable alu_result_v : alu_result_rec;
+               variable tmp_shift : bit_vector(gp_register_t'length+1 downto 0);
+               variable tmp_sb : std_logic;
+       begin
+               alu_result_v := alu_state;
+               
+               if ls = '1' then
+                       tmp_sb := (carry and alu_state.status.carry and logic);
+                       tmp_shift :=  to_bitvector(alu_state.status.carry & left_operand & tmp_sb);
+                       tmp_shift :=  tmp_shift sla to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0));
+                       
+                       alu_result_v.status.carry := to_stdlogicvector(tmp_shift)(tmp_shift'high);
+                       
+               else
+                       tmp_sb := (carry and alu_state.status.carry and logic) or (not(logic) and left_operand(gp_register_t'high));
+                       tmp_shift := to_bitvector(tmp_sb & left_operand & alu_state.status.carry);
+                       tmp_shift := tmp_shift sra to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0));
+                       
+                       alu_result_v.status.carry := to_stdlogicvector(tmp_shift)(0);
+               end if;
+               
+               alu_result_v.result := to_stdlogicvector(tmp_shift)(gp_register_t'length downto 1);
+               
+               alu_result <= alu_result_v;
+               
+end process;
+
+end architecture shift_op;

diff --git a/cpu/src/exec_op/xor_op_b.vhd b/cpu/src/exec_op/xor_op_b.vhd
index 62c7db8e071a7ccbe65d391104db5ab156641e40..8d4089c6e26a7c3a01e34ed39fbe8e524114ebc7 100755 (executable)
--- a/cpu/src/exec_op/xor_op_b.vhd
+++ b/cpu/src/exec_op/xor_op_b.vhd
@@ -1,22 +1,22 @@
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-use IEEE.numeric_std.all;\r
-\r
-use work.common_pkg.all;\r
-use work.alu_pkg.all;\r
-\r
-architecture xor_op of exec_op is\r
-begin\r
-\r
-calc: process(left_operand, right_operand, alu_state)\r
-       variable alu_result_v : alu_result_rec;\r
-       \r
-begin\r
-               alu_result_v := alu_state;\r
-               \r
-               alu_result_v.result := left_operand xor right_operand;\r
-               \r
-               alu_result <= alu_result_v;\r
-end process; \r
-\r
-end architecture xor_op;\r
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.common_pkg.all;
+use work.alu_pkg.all;
+
+architecture xor_op of exec_op is
+begin
+
+calc: process(left_operand, right_operand, alu_state)
+       variable alu_result_v : alu_result_rec;
+       
+begin
+               alu_result_v := alu_state;
+               
+               alu_result_v.result := left_operand xor right_operand;
+               
+               alu_result <= alu_result_v;
+end process; 
+
+end architecture xor_op;