quartus tcl script für meinen cyclone II, top level entity für fetch und decode

diff --git a/cpu/.gitignore b/cpu/.gitignore
new file mode 100644 (file)
index 0000000..94654cb
--- /dev/null
+++ b/cpu/.gitignore
@@ -0,0 +1 @@
+/prj/*

diff --git a/cpu/create_project.tcl b/cpu/create_project.tcl
index d91b61021e1084bf2ffbc45266c3cc0896202272..6419c5aaf07cb6e4dc181f757ff8fb42de4f9e00 100755 (executable)
--- a/cpu/create_project.tcl
+++ b/cpu/create_project.tcl
@@ -1,107 +1,69 @@
-package require ::quartus::project\r
-\r
-set need_to_close_project 0\r
-set make_assignments 1\r
-\r
-# Check that the right project is open\r
-if {[is_project_open]} {\r
-       if {[string compare $quartus(project) "de1_cyclone"]} {\r
-               puts "Project de1_cyclone is not open"\r
-               set make_assignments 0\r
-       }\r
-} else {\r
-       # Only open if not already open\r
-       if {[project_exists de1_cyclone]} {\r
-               project_open -revision de1_cyclone de1_cyclone\r
-       } else {\r
-               project_new -revision de1_cyclone de1_cyclone\r
-       }\r
-       set need_to_close_project 1\r
-}\r
-\r
-# Make assignments\r
-if {$make_assignments} {\r
-       set_global_assignment -name FAMILY "Cyclone II"\r
-       set_global_assignment -name DEVICE EP2C20F484C7\r
-       set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"\r
-       set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation\r
-       set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga\r
-       set_global_assignment -name MISC_FILE "de1_cyclone.dpf"\r
-       set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"\r
-       set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"\r
-       set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"\r
-\r
-       set_global_assignment -name TOP_LEVEL_ENTITY de1_test_top\r
-       set_global_assignment -name VHDL_FILE ../../math_pkg.vhd\r
-       set_global_assignment -name VHDL_FILE ../../de1_test_top.vhd\r
-       set_global_assignment -name VHDL_FILE ../../DE1_7SEG/src/DE1_7SEG_PKG.vhd\r
-       set_global_assignment -name VHDL_FILE ../../DE1_7SEG/src/DE1_7SEG_ENT.vhd\r
-       set_global_assignment -name VHDL_FILE ../../DE1_7SEG/src/DE1_7SEG_ARC.vhd\r
-       set_global_assignment -name VHDL_FILE ../../UART/rs232_pak.vhd\r
-       set_global_assignment -name VHDL_FILE ../../UART/rs232_ent.vhd\r
-       set_global_assignment -name VHDL_FILE ../../UART/rs232_arc.vhd\r
-       set_global_assignment -name VHDL_FILE ../../PS2/ps2_pak.vhd\r
-       set_global_assignment -name VHDL_FILE ../../PS2/ps2_ENT.vhd\r
-       set_global_assignment -name VHDL_FILE ../../PS2/ps2_ARC.vhd\r
-       set_global_assignment -name VHDL_FILE ../../ram/ram_pkg.vhd\r
-       set_global_assignment -name VHDL_FILE ../../ram/dp_ram_ent.vhd\r
-       set_global_assignment -name VHDL_FILE ../../ram/dp_ram_arc.vhd\r
-       \r
-       set_location_assignment PIN_L1 -to sys_clk\r
-       set_location_assignment PIN_R22 -to sys_res\r
-\r
-       set_location_assignment PIN_J2 -to o_digit0[0]\r
-       set_location_assignment PIN_J1 -to o_digit0[1]\r
-       set_location_assignment PIN_H2 -to o_digit0[2]\r
-       set_location_assignment PIN_H1 -to o_digit0[3]\r
-       set_location_assignment PIN_F2 -to o_digit0[4]\r
-       set_location_assignment PIN_F1 -to o_digit0[5]\r
-       set_location_assignment PIN_E2 -to o_digit0[6]\r
-\r
-       set_location_assignment PIN_E1 -to o_digit1[0]\r
-       set_location_assignment PIN_H6 -to o_digit1[1]\r
-       set_location_assignment PIN_H5 -to o_digit1[2]\r
-       set_location_assignment PIN_H4 -to o_digit1[3]\r
-       set_location_assignment PIN_G3 -to o_digit1[4]\r
-       set_location_assignment PIN_D2 -to o_digit1[5]\r
-       set_location_assignment PIN_D1 -to o_digit1[6]\r
-\r
-       set_location_assignment PIN_G5 -to o_digit2[0]\r
-       set_location_assignment PIN_G6 -to o_digit2[1]\r
-       set_location_assignment PIN_C2 -to o_digit2[2]\r
-       set_location_assignment PIN_C1 -to o_digit2[3]\r
-       set_location_assignment PIN_E3 -to o_digit2[4]\r
-       set_location_assignment PIN_E4 -to o_digit2[5]\r
-       set_location_assignment PIN_D3 -to o_digit2[6]\r
-\r
-       set_location_assignment PIN_F4 -to o_digit3[0]\r
-       set_location_assignment PIN_D5 -to o_digit3[1]\r
-       set_location_assignment PIN_D6 -to o_digit3[2]\r
-       set_location_assignment PIN_J4 -to o_digit3[3]\r
-       set_location_assignment PIN_L8 -to o_digit3[4]\r
-       set_location_assignment PIN_F3 -to o_digit3[5]\r
-       set_location_assignment PIN_D4 -to o_digit3[6]\r
-\r
-       set_location_assignment PIN_F14 -to rxd\r
-       set_location_assignment PIN_G12 -to txd\r
-       \r
-       set_location_assignment PIN_H15 -to ps2_clk\r
-       set_location_assignment PIN_J14 -to ps2_data\r
-\r
-       set_global_assignment -name FMAX_REQUIREMENT "50.00 MHz" -section_id sys_clk\r
-       set_instance_assignment -name CLOCK_SETTINGS sys_clk -to sys_clk\r
-\r
-       set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"\r
-       set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"\r
-       set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top\r
-       set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top\r
-       set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top\r
-\r
-       # Commit assignments\r
-       export_assignments\r
-\r
-       # Close project\r
-       if {$need_to_close_project} {\r
-               project_close\r
-       }\r
-}\r
+package require ::quartus::project
+
+set need_to_close_project 0
+set make_assignments 1
+
+# Check that the right project is open
+if {[is_project_open]} {
+       if {[string compare $quartus(project) "de1_cyclone"]} {
+               puts "Project de1_cyclone is not open"
+               set make_assignments 0
+       }
+} else {
+       # Only open if not already open
+       if {[project_exists de1_cyclone]} {
+               project_open -revision de1_cyclone de1_cyclone
+       } else {
+               project_new -revision de1_cyclone de1_cyclone
+       }
+       set need_to_close_project 1
+}
+
+# Make assignments
+if {$make_assignments} {
+       set_global_assignment -name FAMILY "Cyclone II"
+       set_global_assignment -name DEVICE EP2C20F484C7
+       set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"
+       set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+       set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
+       set_global_assignment -name MISC_FILE "de1_cyclone.dpf"
+       set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+       set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
+       set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+
+       set_global_assignment -name TOP_LEVEL_ENTITY core_top
+       set_global_assignment -name VHDL_FILE ../src/core_top.vhd
+       set_global_assignment -name VHDL_FILE ../src/mem_pkg.vhd
+       set_global_assignment -name VHDL_FILE ../src/r_w_ram.vhd
+       set_global_assignment -name VHDL_FILE ../src/r_w_ram_b.vhd
+       set_global_assignment -name VHDL_FILE ../src/r2_w_ram.vhd
+       set_global_assignment -name VHDL_FILE ../src/r2_w_ram_b.vhd
+       set_global_assignment -name VHDL_FILE ../src/common_pkg.vhd
+       set_global_assignment -name VHDL_FILE ../src/core_pkg.vhd
+       set_global_assignment -name VHDL_FILE ../src/fetch_stage.vhd
+       set_global_assignment -name VHDL_FILE ../src/fetch_stage_b.vhd
+       set_global_assignment -name VHDL_FILE ../src/decoder.vhd
+       set_global_assignment -name VHDL_FILE ../src/decoder_b.vhd
+       set_global_assignment -name VHDL_FILE ../src/decode_stage.vhd
+       set_global_assignment -name VHDL_FILE ../src/decode_stage_b.vhd
+       
+       set_location_assignment PIN_L1 -to sys_clk
+       set_location_assignment PIN_R22 -to sys_res
+
+       set_global_assignment -name FMAX_REQUIREMENT "80.00 MHz" -section_id sys_clk
+       set_instance_assignment -name CLOCK_SETTINGS sys_clk -to sys_clk
+
+       set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+       set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+       set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+       set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+       set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+
+       # Commit assignments
+       export_assignments
+
+       # Close project
+       if {$need_to_close_project} {
+               project_close
+       }
+}

diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd
new file mode 100644 (file)
index 0000000..a636160
--- /dev/null
+++ b/cpu/src/core_top.vhd
@@ -0,0 +1,101 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.common_pkg.all;
+use work.core_pkg.all;
+
+entity core_top is
+
+       port(
+               --System input pins
+                       sys_clk : in std_logic;
+                       sys_res : in std_logic;
+                       reg1_rd_data : out gp_register_t;
+                       reg2_rd_data : out gp_register_t
+
+                       
+               );
+
+end core_top;
+
+architecture behav of core_top is
+
+               signal jump_result_pin : instruction_addr_t;
+               signal prediction_result_pin : instruction_addr_t;
+               signal branch_prediction_bit_pin : std_logic;
+               signal alu_jump_bit_pin : std_logic;
+               signal instruction_pin : instruction_word_t;
+
+               signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
+               signal reg_wr_data_pin : gp_register_t;
+               signal reg_we_pin : std_logic;
+--             signal reg1_rd_data_pin : gp_register_t;
+--             signal reg2_rd_data_pin : gp_register_t;
+
+
+begin
+
+       fetch_st : fetch_stage
+               generic map (
+       
+                       '0',
+                       '1'
+               )
+               
+               port map (
+               --System inputs
+                       clk => sys_clk, --: in std_logic;
+                       reset => sys_res, --: in std_logic;
+               
+               --Data inputs
+                       jump_result => jump_result_pin, --: in instruction_addr_t;
+                       prediction_result => prediction_result_pin, --: in instruction_addr_t;
+                       branch_prediction_bit => branch_prediction_bit_pin,  --: in std_logic;
+                       alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
+
+               --Data outputs
+                       instruction => instruction_pin --: out instruction_word_t
+               );
+
+       decode_st : decode_stage
+               generic map (
+                       -- active reset value
+                       '0',
+                       -- active logic value
+                       '1'
+                       
+                       )
+               port map (
+               --System inputs
+                       clk => sys_clk, --: in std_logic;
+                       reset => sys_res, -- : in std_logic;
+
+               --Data inputs
+                       instruction => instruction_pin, --: in instruction_word_t;
+                       reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
+                       reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
+                       reg_we => reg_we_pin, --: in std_logic;
+
+               --Data outputs
+                       reg1_rd_data => reg1_rd_data, --: gp_register_t;
+                       reg2_rd_data => reg2_rd_data, --: gp_register_t;
+                       branch_prediction_res => prediction_result_pin, --: instruction_word_t;
+                       branch_prediction_bit => branch_prediction_bit_pin --: std_logic
+                       
+               );
+
+               
+--init : process(all)
+
+--begin
+       jump_result_pin <= (others => '0');
+       alu_jump_bit_pin <= '0';
+       reg_w_addr_pin <= (others => '0');
+       reg_wr_data_pin <= (others => '0');
+       reg_we_pin <= '0';
+       
+--end process;
+       
+
+end behav;