reg_src2_addr : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
immediate : std_logic_vector(WORD_WIDTH-1 downto 0);
--- immediate_set : std_logic;
- displacement : std_logic_vector(DISPL_WIDTH-1 downto 0);
jmptype : std_logic_vector(1 downto 0);
instr_s.reg_src2_addr := (others => '0');
instr_s.immediate := (others => '0');
- instr_s.displacement := (others => '0');
instr_s.jmptype := (others => '0');
instr_s.high_low := '0';
instr_s.fill := '0';
-- when "01110" => --ldw
instr_s.reg_dest_addr := instruction(22 downto 19);
instr_s.reg_src1_addr := instruction(18 downto 15);
- instr_s.displacement(14 downto 0) := instruction(14 downto 0);
instr_s.immediate(15 downto 0) := instruction(18 downto 3);
instr_s.signext := instruction(2);
instr_s.high_low := instruction(1);
if (instr_s.signext = '1' and instr_s.immediate(11) = '1') then
instr_s.immediate(31 downto 16) := (others => '1');
end if;
+ instr_s.immediate(14 downto 0) := instruction(14 downto 0);
+ instr_s.immediate(WORD_WIDTH-1 downto 15) := (others => '0');
instr_s.op_detail(IMM_OPT) := '1';
end if;
end if;
--when "01111" => --stw
instr_s.reg_src1_addr := instruction(22 downto 19); -- register value
instr_s.reg_src2_addr := instruction(18 downto 15); -- mem addr
- instr_s.displacement(14 downto 0) := instruction(14 downto 0);
+ instr_s.immediate(14 downto 0) := instruction(14 downto 0);
end if;
-- when "10001" => --sth