begin
++<<<<<<< HEAD
+ arith <= op_detail(ARITH_OPT);
+ rs <= op_detail(RIGHT_OPT);
++=======
+ logic <= op_detail(ARITH_OPT);
+ ls <= op_detail(RIGHT_OPT);
++>>>>>>> 05fc0d5300956fef107bbb8507a6480ee11695ff
carry <= op_detail(CARRY_OPT);
-calc: process(left_operand, right_operand, logic,ls, carry, alu_state)
+calc: process(left_operand, right_operand, arith,rs, carry, alu_state)
variable alu_result_v : alu_result_rec;
variable tmp_shift : bit_vector(gp_register_t'length+1 downto 0);
variable tmp_sb : std_logic;