test pipe 2

diff --git a/cpu/sim/testcore.do b/cpu/sim/testcore.do
index 4f66a620be59e72dfc487b4582785ba444c55340..d0b5b3388cf2f3ab7d3191001588b69616fb51ef 100644 (file)
--- a/cpu/sim/testcore.do
+++ b/cpu/sim/testcore.do
@@ -60,4 +60,6 @@ add wave  -radix hexadecimal /pipeline_tb/decode_st/reg_w_addr
 add wave  -radix hexadecimal /pipeline_tb/decode_st/reg_wr_data
 add wave  -radix hexadecimal /pipeline_tb/decode_st/reg_we
 
+add wave  -radix hexadecimal /pipeline_tb/exec_st/gpm_inst/psw
+
 run 5000 ns

diff --git a/cpu/src/alu_b.vhd b/cpu/src/alu_b.vhd
index f3a25ee836032a96a0114b9a460a06d03d09a353..a24ade81c75f60b1d05b770c77d35c8df0fed03d 100755 (executable)
--- a/cpu/src/alu_b.vhd
+++ b/cpu/src/alu_b.vhd
@@ -25,17 +25,19 @@ architecture behaviour of alu is
        \r
 begin\r
 \r
-       add_inst : exec_op\r
+       add_inst : entity work.exec_op(add_op)\r
        port map(clk,reset,left_operand, right_operand, op_detail, alu_state, add_result);\r
        \r
-       and_inst : exec_op\r
+       and_inst : entity work.exec_op(and_op)\r
        port map(clk,reset,left_operand, right_operand, op_detail, alu_state, and_result);\r
-       or_inst : exec_op\r
+\r
+       or_inst : entity work.exec_op(or_op)\r
        port map(clk,reset,left_operand, right_operand, op_detail, alu_state, or_result);\r
-       xor_inst : exec_op\r
+\r
+       xor_inst : entity work.exec_op(xor_op)\r
        port map(clk,reset,left_operand, right_operand, op_detail, alu_state, xor_result);\r
        \r
-       shift_inst : exec_op\r
+       shift_inst : entity work.exec_op(shift_op)\r
        port map(clk,reset,left_operand, right_operand, op_detail, alu_state, shift_result);\r
 \r
 calc: process(left_operand, right_operand, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result)\r
@@ -121,24 +123,3 @@ end process calc;
 \r
 end architecture behaviour;\r
 \r
-configuration alu_cfg of alu is\r
-\r
-       for behaviour\r
-               for add_inst : exec_op \r
-                       use entity work.exec_op(add_op);\r
-               end for;\r
-               for and_inst : exec_op \r
-                       use entity work.exec_op(and_op);\r
-               end for;\r
-               for or_inst : exec_op\r
-                       use entity work.exec_op(or_op);\r
-               end for;\r
-               for xor_inst : exec_op\r
-                       use entity work.exec_op(xor_op);\r
-               end for;\r
-               for shift_inst : exec_op\r
-                       use entity work.exec_op(shift_op);\r
-               end for;\r
-       end for;\r
-               \r
-end configuration alu_cfg;\r

diff --git a/cpu/src/alu_pkg.vhd b/cpu/src/alu_pkg.vhd
index ead1ac694b63759ebbac2405d92dafb8bb1798cc..cc085c76889d6b5ef21bad97cd017c4b4b52c932 100755 (executable)
--- a/cpu/src/alu_pkg.vhd
+++ b/cpu/src/alu_pkg.vhd
@@ -42,7 +42,7 @@ package alu_pkg is
                \r
        end record alu_result_rec;\r
        \r
-       constant SHIFT_WIDTH : integer := 1;--log2c(gp_register_t'length);\r
+       constant SHIFT_WIDTH : integer := log2c(gp_register_t'length);\r
        \r
        constant COND_ZERO : condition_t := "0001";\r
        constant COND_NZERO : condition_t := "0000";\r
@@ -71,8 +71,8 @@ package alu_pkg is
        -- function xor_op(left_operand, right_operand : gp_register_t; alu_result : alu_result_rec) return alu_result_rec;\r
        \r
        -- function shift_op(left_operand, right_operand : gp_register_t; arith,sleft,carry : std_logic ;alu_result : alu_result_rec) return alu_result_rec;\r
-       
-        component alu is
+       \r
+        component alu is\r
         --some modules won't need all inputs\r
        port(\r
        --System inputs\r
@@ -86,10 +86,10 @@ package alu_pkg is
                        right_operand : in gp_register_t;\r
                        op_detail : in op_opt_t;\r
                        alu_state  : in alu_result_rec;\r
-                       alu_result : out alu_result_rec;
-                        addr : out gp_register_t;
+                       alu_result : out alu_result_rec;\r
+                        addr : out gp_register_t;\r
                         data : out gp_register_t\r
-               );
+               );\r
         end component alu;\r
        \r
 end package alu_pkg;\r

diff --git a/cpu/src/decode_stage_b.vhd b/cpu/src/decode_stage_b.vhd
index fbaf0101d7804730f7ff60632e9fdae7f44dc765..d5ea6474bc1895a83ec620ac6784799030548d63 100644 (file)
--- a/cpu/src/decode_stage_b.vhd
+++ b/cpu/src/decode_stage_b.vhd
@@ -57,8 +57,9 @@ begin
                rtw_rec.immediate <= (others => '0');
                rtw_rec.imm_set <= '0';
 
-               dec_op_inst.condition <= (others => '0');
+               dec_op_inst.condition <= (others => '1');
                dec_op_inst.op_detail <= (others => '0');
+               dec_op_inst.op_group <= ADDSUB_OP;
                dec_op_inst.brpr <= '0'; --branch_prediction_bit;
                dec_op_inst.src1 <= (others => '0');
                dec_op_inst.src2 <= (others => '0');
@@ -114,6 +115,7 @@ begin
        dec_op_inst_nxt.saddr1 <= instr_spl.reg_src1_addr;
        dec_op_inst_nxt.saddr2 <= instr_spl.reg_src2_addr;
        dec_op_inst_nxt.daddr <= (others => '0');
+       dec_op_inst_nxt.op_group <= instr_spl.op_group;
 
 end process;
 

diff --git a/cpu/src/exec_op/add_op_b.vhd b/cpu/src/exec_op/add_op_b.vhd
index 0e28af8af56b68303baa28adb1eb9bda4f1e0508..77cd90116469e657b299534e20a5363af78f234d 100644 (file)
--- a/cpu/src/exec_op/add_op_b.vhd
+++ b/cpu/src/exec_op/add_op_b.vhd
@@ -30,8 +30,7 @@ begin
                complement := inc(not(right_operand));
                l_neg := left_operand(gp_register_t'high);
                
-               --carry_res := unsigned('0' & left_operand)+addcarry;
-               carry_res := unsigned('0' & left_operand);
+               carry_res := unsigned('0' & left_operand)+addcarry;
                oflo1 := add_oflo(l_neg,'0',carry_res(gp_register_t'high));
                
                if sub = '1' then
@@ -49,9 +48,9 @@ begin
 
                alu_result_v.result := std_logic_vector(carry_res(gp_register_t'range));
                alu_result_v.status.carry := carry_res(carry_res'high);
+       --      alu_result_v.result := (0 => '1', others => '0');
                
-               
-               alu_result_v.status.carry := oflo1 or oflo2;
+               alu_result_v.status.oflo := oflo1 or oflo2;
                
                --sign will be set globally.
                --zero will be set globally.

diff --git a/cpu/src/r2_w_ram_b.vhd b/cpu/src/r2_w_ram_b.vhd
index d067ad3a9589ec053ac9a67edb6e52bec2da58fe..a0b163939bd2667f73fc2311d1a82e5211a62d50 100644 (file)
--- a/cpu/src/r2_w_ram_b.vhd
+++ b/cpu/src/r2_w_ram_b.vhd
@@ -13,7 +13,7 @@ architecture behaviour of r2_w_ram is
        signal ram : RAM_TYPE := (
                                0 => x"00000000",
                                1 => x"00000001",
-                               2 => x"00000002",
+                               2 => x"FFFFFFFF",
                                3 => x"00000003",
                                others=> x"00000000");
 

diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd
index c9de81aab4d9d41194836885abee7ac44d67ccdb..3664ea109adc72d064b8d5dedf146f016eee0683 100644 (file)
--- a/cpu/src/r_w_ram_b.vhd
+++ b/cpu/src/r_w_ram_b.vhd
@@ -10,11 +10,12 @@ architecture behaviour of r_w_ram is
        subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
        type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
        
-       signal ram : RAM_TYPE := (0 => "11100000000000011001000000000000", 
-                                 1 => "11110000000000001001000000000000", 
-                                 2 => "11100000000010001001000000000000", 
-                                 3 => "11100001000110010111011001101100", 
-                                 others => x"00000000");
+       signal ram : RAM_TYPE := (0 => "11100000000000011001000000000000",  -- r0 = r3 + r2 (always)
+                                 1 => "11100101000000001000100000000010",  -- r0 = r1 << 0 (always)
+                                 2 => "11100000000010000001100000000000",  -- r1 = r0 + r3 (always)
+                                 3 => "11100000101000000001000000000000",
+                                 4 => "11100001000110010111011001101100", 
+                                 others => x"E0000000");
 
 begin
        process(clk)