Seperation to differen execute operations.

diff --git a/cpu/src/alu.vhd b/cpu/src/alu.vhd
new file mode 100755 (executable)
index 0000000..b94421a
--- /dev/null
+++ b/cpu/src/alu.vhd
@@ -0,0 +1,26 @@
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+use IEEE.numeric_std.all;\r
+\r
+use work.common_pkg.all;\r
+use work.alu_pkg.all;\r
+\r
+entity alu is\r
+       --some modules won't need all inputs\r
+       port(\r
+       --System inputs\r
+       \r
+                       clk : in std_logic;\r
+                       reset : in std_logic;\r
+       --operation inputs\r
+                       condition       :       condition_t;\r
+                       op_group : in op_info_t;\r
+                       left_operand : in gp_register_t;\r
+                       right_operand : in gp_register_t;\r
+                       op_detail : in op_opt_t;\r
+                       alu_state  : in alu_result_rec;\r
+                       alu_result : out alu_result_rec\r
+               );\r
+               \r
+end alu;\r
+\r

diff --git a/cpu/src/alu_b.vhd b/cpu/src/alu_b.vhd
index 533ed7f8742b08082ed3b477bce0d90295371dfe..511b15426f36e640b167936aea137bc07290dd9c 100755 (executable)
--- a/cpu/src/alu_b.vhd
+++ b/cpu/src/alu_b.vhd
@@ -2,37 +2,139 @@ library IEEE;
 use IEEE.std_logic_1164.all;\r
 use IEEE.numeric_std.all;\r
 \r
-use work.core_pkg.all;\r
 use work.alu_pkg.all;\r
 \r
-architecture behaviour of alu is\r
 \r
+architecture behaviour of alu is\r
+       component exec_op is\r
+       port(\r
+               --System inputs\r
+               \r
+               clk : in std_logic;\r
+               reset : in std_logic;\r
+               --operation inputs\r
+               left_operand : in gp_register_t;\r
+               right_operand : in gp_register_t;\r
+               op_detail  : in op_opt_t;\r
+               alu_state  : in alu_result_rec;\r
+               alu_result : out alu_result_rec\r
+       );                      \r
+       end component exec_op;\r
+       \r
+       signal add_result, and_result, or_result, xor_result, shift_result : alu_result_rec;\r
+       \r
 begin\r
 \r
-syn: process(sys_clk, reset)\r
+       add_inst : exec_op\r
+       port map(clk,reset,left_operand, right_operand, op_detail, alu_state, add_result);\r
+       \r
+       and_inst : exec_op\r
+       port map(clk,reset,left_operand, right_operand, op_detail, alu_state, and_result);\r
+       or_inst : exec_op\r
+       port map(clk,reset,left_operand, right_operand, op_detail, alu_state, or_result);\r
+       xor_inst : exec_op\r
+       port map(clk,reset,left_operand, right_operand, op_detail, alu_state, xor_result);\r
+       \r
+       shift_inst : exec_op\r
+       port map(clk,reset,left_operand, right_operand, op_detail, alu_state, shift_result);\r
 \r
+calc: process(condition, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result)\r
+       variable result_v : alu_result_rec;\r
+       variable res_prod : std_logic;\r
+       variable cond_met : std_logic;\r
+       variable mem_en : std_logic;\r
 begin\r
-\r
-       if (reset = RESET_VALUE) then\r
-                               \r
-       elsif rising_edge(sys_clk) then\r
-               \r
+       result_v := alu_state;\r
+       \r
+       result_v.result := add_result.result;\r
+       res_prod := '1';\r
+       mem_en := '0';\r
+       \r
+       case condition is\r
+       when COND_NZERO =>\r
+               cond_met := not(alu_state.status.zero);\r
+       when COND_ZERO =>\r
+               cond_met := alu_state.status.zero;\r
+       when COND_NOFLO =>\r
+               cond_met := not(alu_state.status.oflo);\r
+       when COND_OFLO =>\r
+               cond_met := alu_state.status.oflo;\r
+       when COND_NCARRY =>\r
+               cond_met := not(alu_state.status.carry);\r
+       when COND_CARRY =>\r
+               cond_met := alu_state.status.carry;\r
+       when COND_NSIGN =>\r
+               cond_met := not(alu_state.status.sign);\r
+       when COND_SIGN =>\r
+               cond_met := alu_state.status.sign;\r
+       when COND_ABOVE =>\r
+               cond_met := not(alu_state.status.carry) and not(alu_state.status.zero);\r
+       when COND_BEQ =>\r
+               cond_met := alu_state.status.carry or alu_state.status.zero;\r
+       when COND_GEQ =>\r
+               cond_met := not(alu_state.status.sign xor alu_state.status.oflo);\r
+       when COND_LT =>\r
+               cond_met := alu_state.status.sign xor alu_state.status.oflo;\r
+       when COND_GT =>\r
+               cond_met := not(alu_state.status.zero) and not(alu_state.status.sign xor alu_state.status.oflo);\r
+       when COND_LEQ =>\r
+               cond_met := alu_state.status.zero or (alu_state.status.sign xor alu_state.status.oflo);\r
+       when COND_ALWAYS =>\r
+               cond_met := '1';\r
+       when COND_NEVER =>\r
+               cond_met := '0';\r
+       end case;\r
+       \r
+       case op_group is\r
+       when ADDSUB_OP =>\r
+               result_v := add_result;\r
+       when AND_OP =>\r
+               result_v := and_result;\r
+       when OR_OP =>\r
+               result_v := or_result;\r
+       when XOR_OP =>\r
+               result_v := xor_result;\r
+       when SHIFT_OP =>\r
+               result_v := shift_result;\r
+       end case;\r
+       \r
+       if result_v.result = REG_ZERO then\r
+               result_v.status.zero := '1';\r
        end if;\r
        \r
-end process syn; \r
-\r
-\r
-nxt_calc: process(sys_clk, reset)\r
-\r
-begin\r
+       result_v.status.sign := result_v.result(gp_register_t'high);\r
 \r
+       if (op_detail(NO_PSW_OPT) = '1') or (cond_met = '0') then\r
+               result_v.status := alu_state.status;\r
+       end if;\r
        \r
-       case new_op is\r
-       when ADD_SUB =>\r
-               \r
-       when others => null;\r
-       end case;\r
+       result_v.new_val := not(op_detail(NO_DST_OPT)) and res_prod and cond_met;\r
+       result_v.mem_en := mem_en and cond_met;\r
+       \r
+       alu_result <= result_v;\r
        \r
-end process nxt_calc; \r
+end process calc; \r
 \r
 end architecture behaviour;\r
+\r
+configuration alu_cfg of alu is\r
+\r
+       for behaviour\r
+               for add_inst : exec_op \r
+                       use entity work.exec_op(add_op);\r
+               end for;\r
+               for and_inst : exec_op \r
+                       use entity work.exec_op(and_op);\r
+               end for;\r
+               for or_inst : exec_op\r
+                       use entity work.exec_op(or_op);\r
+               end for;\r
+               for xor_inst : exec_op\r
+                       use entity work.exec_op(xor_op);\r
+               end for;\r
+               for shift_inst : exec_op\r
+                       use entity work.exec_op(shift_op);\r
+               end for;\r
+       end for;\r
+               \r
+end configuration alu_cfg;\r

diff --git a/cpu/src/alu_pkg.vhd b/cpu/src/alu_pkg.vhd
index 9ab238450639badc6906b0dbfa41fa6d984a09f6..05e040d1a8873303a02b259c5213b37292018ea7 100755 (executable)
--- a/cpu/src/alu_pkg.vhd
+++ b/cpu/src/alu_pkg.vhd
@@ -17,9 +17,9 @@ package alu_pkg is
        end record;\r
        \r
        subtype status_t is byte_t;\r
-       type alu_interal_rec is record\r
-               \r
-       end record alu_internal_rec;\r
+       --type alu_interal_rec is record\r
+       --      \r
+       --end record alu_internal_rec;\r
        \r
        type alu_result_rec is record\r
                result : gp_register_t;\r
@@ -33,22 +33,44 @@ package alu_pkg is
                reg_op : std_logic;\r
                mem_op  : std_logic;\r
                \r
+               new_val : std_logic;\r
+               mem_en : std_logic;\r
+               \r
                hw_op   : std_logic;\r
                byte_op : std_logic;\r
                sign_xt : std_logic;\r
                \r
        end record alu_result_rec;\r
        \r
-       constant SHIFT_WIDTH : integer := log2c(gp_register_t'length);\r
+       constant SHIFT_WIDTH : integer := 1;--log2c(gp_register_t'length);\r
+       \r
+       constant COND_ZERO : condition_t := "0001";\r
+       constant COND_NZERO : condition_t := "0000";\r
+       constant COND_NOFLO : condition_t := "0010";\r
+       constant COND_OFLO : condition_t := "0011";\r
+       constant COND_NCARRY : condition_t := "0100";\r
+       constant COND_CARRY : condition_t := "0101";\r
+       constant COND_NSIGN : condition_t := "0110";\r
+       constant COND_SIGN : condition_t := "0111";\r
+       \r
+       constant COND_ABOVE : condition_t := "1000";\r
+       constant COND_BEQ: condition_t := "1001";\r
+       constant COND_GEQ : condition_t := "1010";\r
+       constant COND_LT : condition_t := "1011";\r
+       constant COND_GT : condition_t := "1100";\r
+       \r
+       constant COND_LEQ : condition_t := "1101";\r
+       constant COND_ALWAYS : condition_t := "1110";\r
+       constant COND_NEVER : condition_t := "1111";\r
        \r
        function add_oflo(l_neg, r_neg, res_neg : std_logic) return std_logic;\r
-       function addsub_op(left_operand, right_operand : gp_register_t; sub, addc : std_logic; alu_result : alu_result_rec) return alu_result_rec;\r
+       -- function addsub_op(left_operand, right_operand : gp_register_t; sub, addc : std_logic; alu_result : alu_result_rec) return alu_result_rec;\r
        \r
-       function and_op(left_operand, right_operand : gp_register_t; alu_result : alu_result_rec) return alu_result_rec;\r
-       function or_op(left_operand, right_operand : gp_register_t; alu_result : alu_result_rec) return alu_result_rec;\r
-       function xor_op(left_operand, right_operand : gp_register_t; alu_result : alu_result_rec) return alu_result_rec;\r
+       -- function and_op(left_operand, right_operand : gp_register_t; alu_result : alu_result_rec) return alu_result_rec;\r
+       -- function or_op(left_operand, right_operand : gp_register_t; alu_result : alu_result_rec) return alu_result_rec;\r
+       -- function xor_op(left_operand, right_operand : gp_register_t; alu_result : alu_result_rec) return alu_result_rec;\r
        \r
-       function shift_op(left_operand, right_operand : gp_register_t; arith,sleft,carry : std_logic ;alu_result : alu_result_rec) return alu_result_rec;\r
+       -- function shift_op(left_operand, right_operand : gp_register_t; arith,sleft,carry : std_logic ;alu_result : alu_result_rec) return alu_result_rec;\r
        \r
        \r
 end package alu_pkg;\r
@@ -61,94 +83,94 @@ package body alu_pkg is
                                (not(l_neg) AND not(r_neg) AND res_neg);\r
        end function add_oflo;\r
        \r
-       function addsub_op(left_operand, right_operand : gp_register_t; sub, addc : std_logic; alu_result : alu_result_rec) return alu_result_rec is\r
-               variable alu_result_out : alu_result_rec;\r
-               variable complement             : gp_register_t;\r
-               variable carry_res              : unsigned(gp_register_t'length downto 0);\r
-               variable tmp_right_operand : unsigned(gp_register_t'length downto 0);\r
-               variable oflo1, oflo2, l_neg, r_neg : std_logic;\r
-               variable addcarry               : unsigned(carry_res'range);\r
-       begin\r
-               alu_result_out := alu_result;\r
+       -- function addsub_op(left_operand, right_operand : gp_register_t; sub, addc : std_logic; alu_result : alu_result_rec) return alu_result_rec is\r
+               -- variable alu_result_out : alu_result_rec;\r
+               -- variable complement          : gp_register_t;\r
+               -- variable carry_res           : unsigned(gp_register_t'length downto 0);\r
+               -- variable tmp_right_operand : unsigned(gp_register_t'length downto 0);\r
+               -- variable oflo1, oflo2, l_neg, r_neg : std_logic;\r
+               -- variable addcarry            : unsigned(carry_res'range);\r
+       -- begin\r
+               -- alu_result_out := alu_result;\r
                \r
-               addcarry := (others =>'0');\r
-               addcarry(0) := unsigned(alu_result.status.carry and addc);\r
+               -- addcarry := (others =>'0');\r
+               -- addcarry(0) := unsigned(alu_result.status.carry and addc);\r
                \r
-               complement := inc(not(right_operand));\r
-               l_neg := left_operand(gp_register_t'high);\r
+               -- complement := inc(not(right_operand));\r
+               -- l_neg := left_operand(gp_register_t'high);\r
                \r
-               carry_res := unsigned('0' & left_operand)+addcarry;\r
-               oflo1 := add_oflo(l_neg,'0',std_logic_vector(carry_res)(gp_register_t'high));\r
+               -- carry_res := unsigned('0' & left_operand)+addcarry;\r
+               -- oflo1 := add_oflo(l_neg,'0',std_logic_vector(carry_res)(gp_register_t'high));\r
                \r
-               if sub = '1' then\r
-                       tmp_right_operand := unsigned('0' & complement);\r
-               else\r
-                       tmp_right_operand := unsigned('0' & right_operand);\r
-               end if;\r
+               -- if sub = '1' then\r
+                       -- tmp_right_operand := unsigned('0' & complement);\r
+               -- else\r
+                       -- tmp_right_operand := unsigned('0' & right_operand);\r
+               -- end if;\r
                \r
-               l_neg := std_logic_vector(carry_res)(gp_register_t'high);\r
-               r_neg := std_logic_vector(tmp_right_operand)(gp_register_t'high);\r
+               -- l_neg := std_logic_vector(carry_res)(gp_register_t'high);\r
+               -- r_neg := std_logic_vector(tmp_right_operand)(gp_register_t'high);\r
                \r
-               carry_res := carry_res + tmp_right_operand;\r
-               oflo2 := add_oflo(l_neg,r_neg,std_logic_vector(carry_res)(gp_register_t'high));\r
+               -- carry_res := carry_res + tmp_right_operand;\r
+               -- oflo2 := add_oflo(l_neg,r_neg,std_logic_vector(carry_res)(gp_register_t'high));\r
                \r
 \r
-               alu_result_out.result := std_logic_vector(carry_res)(gp_register_t'range);\r
-               alu_result_out.status.carry := std_logic_vector(carry_res)(carry_res'high);\r
+               -- alu_result_out.result := std_logic_vector(carry_res)(gp_register_t'range);\r
+               -- alu_result_out.status.carry := std_logic_vector(carry_res)(carry_res'high);\r
                \r
                \r
-               alu_result_out.status.carry := oflo1 or oflo2;\r
+               -- alu_result_out.status.carry := oflo1 or oflo2;\r
                \r
-               --sign will be set globally.\r
-               --zero will be set globally.\r
+               -- --sign will be set globally.\r
+               -- --zero will be set globally.\r
                \r
-               return alu_result_out;\r
-       end function addsub_op;\r
+               -- return alu_result_out;\r
+       -- end function addsub_op;\r
        \r
-       function and_op(left_operand, right_operand : gp_register_t; alu_result : alu_result_rec) return alu_result_rec is\r
-               variable alu_result_out : alu_result_rec;\r
-       begin\r
-               alu_result_out := alu_result;\r
-               alu_result_out.result := left_operand and right_operand;\r
-       end function and_op;\r
+       -- function and_op(left_operand, right_operand : gp_register_t; alu_result : alu_result_rec) return alu_result_rec is\r
+               -- variable alu_result_out : alu_result_rec;\r
+       -- begin\r
+               -- alu_result_out := alu_result;\r
+               -- alu_result_out.result := left_operand and right_operand;\r
+       -- end function and_op;\r
        \r
-       function or_op(left_operand, right_operand : gp_register_t; alu_result : alu_result_rec) return alu_result_rec is\r
-               variable alu_result_out : alu_result_rec;\r
-       begin\r
-               alu_result_out := alu_result;\r
-               alu_result_out.result := left_operand or right_operand;\r
-       end function or_op;\r
+       -- function or_op(left_operand, right_operand : gp_register_t; alu_result : alu_result_rec) return alu_result_rec is\r
+               -- variable alu_result_out : alu_result_rec;\r
+       -- begin\r
+               -- alu_result_out := alu_result;\r
+               -- alu_result_out.result := left_operand or right_operand;\r
+       -- end function or_op;\r
        \r
-       function xor_op(left_operand, right_operand : gp_register_t; alu_result : alu_result_rec) return alu_result_rec is\r
-               variable alu_result_out : alu_result_rec;\r
-       begin\r
-               alu_result_out := alu_result;\r
-               alu_result_out.result := left_operand xor right_operand;\r
-       end function xor_op;\r
-       \r
-       function shift_op(left_operand, right_operand : gp_register_t; arith,rs,carry : std_logic ;alu_result : alu_result_rec) return alu_result_rec is\r
-               variable alu_result_out : alu_result_rec;\r
-               variable tmp_shift : bit_vector(gp_register_t'length+1 downto 0);\r
-               variable tmp_sb : std_logic;\r
-       begin\r
-               alu_result_out := alu_result;\r
-               \r
-               if rs = '1' then\r
-                       tmp_sb := (carry and alu_result.status.carry and not(arith)) or (arith and left_operand(gp_register_t'high));\r
-                       tmp_shift := bit_vector(tmp_sb & left_operand & alu_result.status.carry);\r
-                       tmp_shift := tmp_shift sra to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0));\r
+       -- function xor_op(left_operand, right_operand : gp_register_t; alu_result : alu_result_rec) return alu_result_rec is\r
+               -- variable alu_result_out : alu_result_rec;\r
+       -- begin\r
+               -- alu_result_out := alu_result;\r
+               -- alu_result_out.result := left_operand xor right_operand;\r
+       -- end function xor_op;\r
+       \r
+       -- function shift_op(left_operand, right_operand : gp_register_t; arith,rs,carry : std_logic ;alu_result : alu_result_rec) return alu_result_rec is\r
+               -- variable alu_result_out : alu_result_rec;\r
+               -- variable tmp_shift : bit_vector(gp_register_t'length+1 downto 0);\r
+               -- variable tmp_sb : std_logic;\r
+       -- begin\r
+               -- alu_result_out := alu_result;\r
+               \r
+               -- if rs = '1' then\r
+                       -- tmp_sb := (carry and alu_result.status.carry and not(arith)) or (arith and left_operand(gp_register_t'high));\r
+                       -- tmp_shift := bit_vector(tmp_sb & left_operand & alu_result.status.carry);\r
+                       -- tmp_shift := tmp_shift sra to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0));\r
                        \r
-                       alu_result_out.status.carry := std_logic_vector(tmp_shift)(0);\r
-               else\r
-                       tmp_sb := (carry and alu_result.status.carry and not(arith));\r
-                       tmp_shift :=  bit_vector(alu_result.status.carry & left_operand & tmp_sb);\r
-                       tmp_shift :=  tmp_shift sla to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0));\r
+                       -- alu_result_out.status.carry := std_logic_vector(tmp_shift)(0);\r
+               -- else\r
+                       -- tmp_sb := (carry and alu_result.status.carry and not(arith));\r
+                       -- tmp_shift :=  bit_vector(alu_result.status.carry & left_operand & tmp_sb);\r
+                       -- tmp_shift :=  tmp_shift sla to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0));\r
                        \r
-                       alu_result_out.status.carry := std_logic_vector(tmp_shift)(tmp_shift'high);\r
-               end if;\r
+                       -- alu_result_out.status.carry := std_logic_vector(tmp_shift)(tmp_shift'high);\r
+               -- end if;\r
                \r
-               alu_result_out.result := std_logic_vector(tmp_shift)(gp_register_t'length downto 1);\r
+               -- alu_result_out.result := std_logic_vector(tmp_shift)(gp_register_t'length downto 1);\r
                \r
-       end function shift_op;\r
+       -- end function shift_op;\r
 \r
 end package body alu_pkg;\r

diff --git a/cpu/src/common_pkg.vhd b/cpu/src/common_pkg.vhd
old mode 100644 (file)
new mode 100755 (executable)
index c54829b..9398fb2
--- a/cpu/src/common_pkg.vhd
+++ b/cpu/src/common_pkg.vhd
@@ -28,7 +28,7 @@ package common_pkg is
        constant DATA_ADDR_WIDTH        : INTEGER := 32;
        constant PHYS_DATA_ADDR_WIDTH   : INTEGER := 32;
        
-       constant NUM_OP_OPT_WIDTH       : INTEGER := 5;
+       constant NUM_OP_OPT_WIDTH       : INTEGER := 6;
        constant COND_WIDTH : INTEGER := 4;
 
        
@@ -46,19 +46,20 @@ package common_pkg is
        --currently not complete, might need option increase too.
        --IMMEDIATE always in right_operand (src2)
        
-       constant IMM_OPT : integer := 0;
+       constant IMM_OPT : integer := 0; -- no sharing
        
        constant SUB_OPT : integer := 1;
-       constant LOG_SHIFT : integer := 1;
+       constant LOG_OPT : integer := 1;
        
        constant CARRY_OPT : integer := 2;
        
-       constant LEFT_SHIFT : integer := 3;
+       constant LEFT_OPT : integer := 3;
        
-       constant PSW_DISABLE : integer := 4;
+       constant NO_PSW_OPT : integer := 4;--no sharing
+       constant NO_DST_OPT : integer := 5; --no sharing
        
        type op_info_t is (ADDSUB_OP,AND_OP,OR_OP, XOR_OP,SHIFT_OP);
-       subtype op_opt_rec is std_logic_vector(NUM_OP_OPT_WIDTH-1 downto 0);
+       subtype op_opt_t is std_logic_vector(NUM_OP_OPT_WIDTH-1 downto 0);
        
        
        type instruction_rec is record
@@ -92,7 +93,7 @@ package common_pkg is
        type dec_op is record
                condition : condition_t;
                op_group : op_info_t;
-               op_detail : op_opt_rec;
+               op_detail : op_opt_t;
                brpr : std_logic;
                
                src1 : gp_register_t;

diff --git a/cpu/src/exec_op.vhd b/cpu/src/exec_op.vhd
index b3ef75b8978eeebb04f6554235ca6a6b06c40872..0c2b8bd352d689d7e43ff8756ae15921f3a85b10 100755 (executable)
--- a/cpu/src/exec_op.vhd
+++ b/cpu/src/exec_op.vhd
@@ -2,24 +2,22 @@ library IEEE;
 use IEEE.std_logic_1164.all;\r
 use IEEE.numeric_std.all;\r
 \r
-entity exec_op is\r
+use work.common_pkg.all;\r
+use work.alu_pkg.all;\r
 \r
-       generic (\r
-                       -- active reset value\r
-                       RESET_VALUE : std_logic;\r
-                       -- active logic value\r
-                       LOGIC_ACT : std_logic\r
-                       \r
-                       );\r
+entity exec_op is\r
+       --some modules won't need all inputs\r
        port(\r
-               --System inputs\r
+       --System inputs\r
+       \r
                        clk : in std_logic;\r
                        reset : in std_logic;\r
-               --\r
-                       \r
-                       \r
-                       alu_state : in alu_result_rec;\r
-                       alu_state_out : out alu_result_rec\r
+       --operation inputs\r
+                       left_operand : in gp_register_t;\r
+                       right_operand : in gp_register_t;\r
+                       op_detail  : in op_opt_t;\r
+                       alu_state  : in alu_result_rec;\r
+                       alu_result : out alu_result_rec\r
                );\r
                \r
-end execute_stage;\r
+end exec_op;\r

diff --git a/cpu/src/exec_op/add_op_b.vhd b/cpu/src/exec_op/add_op_b.vhd
new file mode 100755 (executable)
index 0000000..e3d62c6
--- /dev/null
+++ b/cpu/src/exec_op/add_op_b.vhd
@@ -0,0 +1,61 @@
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+use IEEE.numeric_std.all;\r
+\r
+use work.common_pkg.all;\r
+use work.alu_pkg.all;\r
+\r
+architecture add_op of exec_op is\r
+\r
+signal sub, addc : std_logic;\r
+\r
+begin\r
+\r
+sub <= op_detail(SUB_OPT);\r
+addc <= op_detail(CARRY_OPT);\r
+\r
+calc: process(left_operand, right_operand, alu_state, sub, addc)\r
+       variable alu_result_v : alu_result_rec;\r
+       variable complement             : gp_register_t;\r
+       variable carry_res              : unsigned(gp_register_t'length downto 0);\r
+       variable tmp_right_operand : unsigned(gp_register_t'length downto 0);\r
+       variable oflo1, oflo2, l_neg, r_neg : std_logic;\r
+       variable addcarry               : unsigned(carry_res'range);\r
+begin\r
+               alu_result_v := alu_state;\r
+               \r
+               addcarry := (others =>'0');\r
+               addcarry(0) := alu_state.status.carry and addc;\r
+               \r
+               complement := inc(not(right_operand));\r
+               l_neg := left_operand(gp_register_t'high);\r
+               \r
+               carry_res := unsigned('0' & left_operand)+addcarry;\r
+               oflo1 := add_oflo(l_neg,'0',std_logic_vector(carry_res)(gp_register_t'high));\r
+               \r
+               if sub = '1' then\r
+                       tmp_right_operand := unsigned('0' & complement);\r
+               else\r
+                       tmp_right_operand := unsigned('0' & right_operand);\r
+               end if;\r
+               \r
+               l_neg := std_logic_vector(carry_res)(gp_register_t'high);\r
+               r_neg := std_logic_vector(tmp_right_operand)(gp_register_t'high);\r
+               \r
+               carry_res := carry_res + tmp_right_operand;\r
+               oflo2 := add_oflo(l_neg,r_neg,std_logic_vector(carry_res)(gp_register_t'high));\r
+               \r
+\r
+               alu_result_v.result := std_logic_vector(carry_res)(gp_register_t'range);\r
+               alu_result_v.status.carry := std_logic_vector(carry_res)(carry_res'high);\r
+               \r
+               \r
+               alu_result_v.status.carry := oflo1 or oflo2;\r
+               \r
+               --sign will be set globally.\r
+               --zero will be set globally.\r
+               \r
+               alu_result <= alu_result_v;\r
+end process; \r
+\r
+end architecture add_op;\r

diff --git a/cpu/src/exec_op/and_op_b.vhd b/cpu/src/exec_op/and_op_b.vhd
new file mode 100755 (executable)
index 0000000..05c8f3e
--- /dev/null
+++ b/cpu/src/exec_op/and_op_b.vhd
@@ -0,0 +1,22 @@
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+use IEEE.numeric_std.all;\r
+\r
+use work.common_pkg.all;\r
+use work.alu_pkg.all;\r
+\r
+architecture and_op of exec_op is\r
+begin\r
+\r
+calc: process(left_operand, right_operand, alu_state)\r
+       variable alu_result_v : alu_result_rec;\r
+       \r
+begin\r
+               alu_result_v := alu_state;\r
+               \r
+               alu_result_v.result := left_operand and right_operand;\r
+               \r
+               alu_result <= alu_result_v;\r
+end process; \r
+\r
+end architecture and_op;\r

diff --git a/cpu/src/exec_op/or_op_b.vhd b/cpu/src/exec_op/or_op_b.vhd
new file mode 100755 (executable)
index 0000000..fbe1ec8
--- /dev/null
+++ b/cpu/src/exec_op/or_op_b.vhd
@@ -0,0 +1,22 @@
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+use IEEE.numeric_std.all;\r
+\r
+use work.common_pkg.all;\r
+use work.alu_pkg.all;\r
+\r
+architecture or_op of exec_op is\r
+begin\r
+\r
+calc: process(left_operand, right_operand, alu_state)\r
+       variable alu_result_v : alu_result_rec;\r
+       \r
+begin\r
+               alu_result_v := alu_state;\r
+               \r
+               alu_result_v.result := left_operand or right_operand;\r
+               \r
+               alu_result <= alu_result_v;\r
+end process; \r
+\r
+end architecture or_op;\r

diff --git a/cpu/src/exec_op/shift_op_b.vhd b/cpu/src/exec_op/shift_op_b.vhd
new file mode 100755 (executable)
index 0000000..291b590
--- /dev/null
+++ b/cpu/src/exec_op/shift_op_b.vhd
@@ -0,0 +1,46 @@
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+use IEEE.numeric_std.all;\r
+\r
+use work.common_pkg.all;\r
+use work.alu_pkg.all;\r
+\r
+architecture shift_op of exec_op is\r
+\r
+       signal logic, ls, carry : std_logic;\r
+\r
+begin\r
+\r
+       logic <=  op_detail(LOG_OPT);\r
+       ls      <=  op_detail(LEFT_OPT);\r
+       carry <= op_detail(CARRY_OPT);\r
+\r
+calc: process(left_operand, right_operand, logic,ls, carry, alu_state)\r
+               variable alu_result_v : alu_result_rec;\r
+               variable tmp_shift : bit_vector(gp_register_t'length+1 downto 0);\r
+               variable tmp_sb : std_logic;\r
+       begin\r
+               alu_result_v := alu_state;\r
+               \r
+               if ls = '1' then\r
+                       tmp_sb := (carry and alu_state.status.carry and logic);\r
+                       tmp_shift :=  to_bitvector(alu_state.status.carry & left_operand & tmp_sb);\r
+                       tmp_shift :=  tmp_shift sla to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0));\r
+                       \r
+                       alu_result_v.status.carry := to_stdlogicvector(tmp_shift)(tmp_shift'high);\r
+                       \r
+               else\r
+                       tmp_sb := (carry and alu_state.status.carry and logic) or (not(logic) and left_operand(gp_register_t'high));\r
+                       tmp_shift := to_bitvector(tmp_sb & left_operand & alu_state.status.carry);\r
+                       tmp_shift := tmp_shift sra to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0));\r
+                       \r
+                       alu_result_v.status.carry := to_stdlogicvector(tmp_shift)(0);\r
+               end if;\r
+               \r
+               alu_result_v.result := to_stdlogicvector(tmp_shift)(gp_register_t'length downto 1);\r
+               \r
+               alu_result <= alu_result_v;\r
+               \r
+end process;\r
+\r
+end architecture shift_op;\r

diff --git a/cpu/src/exec_op/xor_op_b.vhd b/cpu/src/exec_op/xor_op_b.vhd
new file mode 100755 (executable)
index 0000000..62c7db8
--- /dev/null
+++ b/cpu/src/exec_op/xor_op_b.vhd
@@ -0,0 +1,22 @@
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+use IEEE.numeric_std.all;\r
+\r
+use work.common_pkg.all;\r
+use work.alu_pkg.all;\r
+\r
+architecture xor_op of exec_op is\r
+begin\r
+\r
+calc: process(left_operand, right_operand, alu_state)\r
+       variable alu_result_v : alu_result_rec;\r
+       \r
+begin\r
+               alu_result_v := alu_state;\r
+               \r
+               alu_result_v.result := left_operand xor right_operand;\r
+               \r
+               alu_result <= alu_result_v;\r
+end process; \r
+\r
+end architecture xor_op;\r