gpm module and exec first buggy version.

diff --git a/cpu/src/alu.vhd b/cpu/src/alu.vhd
index 8928ece1cc6a76f220f83bc4b028632cb8de1db5..02401dbbd062ea82aaa6604497b02573dcf8e02b 100755 (executable)
--- a/cpu/src/alu.vhd
+++ b/cpu/src/alu.vhd
@@ -19,7 +19,9 @@ entity alu is
                        right_operand : in gp_register_t;\r
                        op_detail : in op_opt_t;\r
                        alu_state  : in alu_result_rec;\r
-                       alu_result : out alu_result_rec\r
+                       alu_result : out alu_result_rec;
+                        addr : out gp_register_t;
+                        data : out gp_register_t\r
                );\r
                \r
 end alu;\r

diff --git a/cpu/src/alu_b.vhd b/cpu/src/alu_b.vhd
index 511b15426f36e640b167936aea137bc07290dd9c..78696f2e619635e818e91a10fd46c1e10d566e3a 100755 (executable)
--- a/cpu/src/alu_b.vhd
+++ b/cpu/src/alu_b.vhd
@@ -48,7 +48,8 @@ begin
        \r
        result_v.result := add_result.result;\r
        res_prod := '1';\r
-       mem_en := '0';\r
+       mem_en := '0';
+        addr <= add_result;\r
        \r
        case condition is\r
        when COND_NZERO =>\r
@@ -109,8 +110,10 @@ begin
        end if;\r
        \r
        result_v.new_val := not(op_detail(NO_DST_OPT)) and res_prod and cond_met;\r
-       result_v.mem_en := mem_en and cond_met;\r
-       \r
+       result_v.mem_en := mem_en and cond_met;
+
+        \r
+       data <= add_result;\r
        alu_result <= result_v;\r
        \r
 end process calc; \r

diff --git a/cpu/src/alu_pkg.vhd b/cpu/src/alu_pkg.vhd
index 088565bd28342f3d18c6aa04e1353e79367ce38a..893653594aabf6e751da78fe7413990330c387e9 100755 (executable)
--- a/cpu/src/alu_pkg.vhd
+++ b/cpu/src/alu_pkg.vhd
@@ -86,7 +86,9 @@ package alu_pkg is
                        right_operand : in gp_register_t;\r
                        op_detail : in op_opt_t;\r
                        alu_state  : in alu_result_rec;\r
-                       alu_result : out alu_result_rec\r
+                       alu_result : out alu_result_rec;
+                        addr : out gp_register_t;
+                        data : out gp_register_t\r
                );
         end component alu;\r
        \r

diff --git a/cpu/src/execute_stage.vhd b/cpu/src/execute_stage.vhd
index 925c579ff6526fafbf2cefb44c3758193057aaa0..9ca96bcf2e9921f9386e4e34c4993b05d3025937 100644 (file)
--- a/cpu/src/execute_stage.vhd
+++ b/cpu/src/execute_stage.vhd
@@ -8,14 +8,27 @@ entity execute_stage is
                        -- active reset value
                        RESET_VALUE : std_logic;
                        -- active logic value
-                       LOGIC_ACT : std_logic;
+                       --LOGIC_ACT : std_logic;
                        
                        );
        port(
                --System inputs
                        clk : in std_logic;
                        reset : in std_logic;
-                        dec_instr : in dec_op
+                        dec_instr : in dec_op;
+
+                --System output
+                        result : out gp_register_t;--reg
+                        result_addr : out gp_addr_t;--reg
+                        addr : out word_t; --memaddr
+                        data : out gp_register_t; --mem data --ureg
+                        alu_jump : out std_logic;--reg
+                        brpr  : out std_logic;  --reg
+                        wr_en : out std_logic;--regop --reg
+                        dmem  : out std_logic;--memop
+                        dmem_wr_en : out std_logic;
+                        hword  : out std_logic;
+                        byte_s : out std_logic
                );
                
 end execute_stage;

diff --git a/cpu/src/execute_stage_b.vhd b/cpu/src/execute_stage_b.vhd
index 095d4dc5e813bc1a00a3be9882ca5d49261199cc..080fb00accba7186704cd9e474927f4c8c5a4beb 100644 (file)
--- a/cpu/src/execute_stage_b.vhd
+++ b/cpu/src/execute_stage_b.vhd
@@ -12,28 +12,41 @@ signal op_group : op_info_t;
 signal op_detail : op_opt_t;
 signal left_operand, right_operand : gp_register_t;
 signal alu_state, alu_nxt : alu_result_rec;
-
 signal psw : status_rec;
 
+type exec_internal is record
+        result : gp_register_t;
+        res_addr : gp_addr_t;
+        alu_jump : std_logic;
+        brpr    : std_logic;
+        wr_en   : std_logic;
+end record;
+
+signal reg, reg_nxt : exec_internal;
+
 begin
 
 alu_inst : alu
 port map(clk, reset, condition, op_group, 
-        op_detail, left_operand, right_operand, alu_state, alu_nxt);
+        op_detail, left_operand, right_operand, alu_state, alu_nxt,addr,data);
 
-syn: process(sys_clk, reset)
+syn: process(clk, reset)
 
 begin
 
-       if (reset = RESET_VALUE) then
-               condition <=                    
-       elsif rising_edge(sys_clk) then
-               
+       if reset = RESET_VALUE then
+               reg.alu_jmp <= '0';
+                reg.brpr <= '0';
+                reg.wr_en <= '0';
+                reg.result <= (others =>'0');
+                reg.res_addr <= (others => '0');                       
+       elsif rising_edge(clk) then
+               reg <= reg_nxt;
        end if;
        
 end process;
 
-asyn: process(reset,condition)
+asyn: process(reset,dec_instr, alu_nxt, psw)
 begin
 
         condition <= dec_instr.condition;
@@ -42,20 +55,33 @@ begin
         left_operand <= dec_instr.src1;
         right_operand <= dec_instr.src2;
 
-        alu_state.status <= psw;
-        alu_state.result_addr <= dec_instr.daddr;
-        alu_state.brpr <= brpr;
-        alu_state.reg_op <= '0';
-        alu_state.mem_op <= '0';
-        alu_state.
+
+        alu_state <= (reg.result,dec_instr.daddr,psw,'0',dec_instr.brpr,'0','0','0','0','0','0'); 
+        
 
         if reset = RESET_VALUE then
                 condition <= COND_NEVER;
         else
                 
         end if;
+        
+        reg_nxt.brpr <= alu_nxt.brpr;
+        reg_nxt.alu_jump <= alu_nxt.alu_jump;
+        reg_nxt.wr_en <= alu_nxt.reg_op;
+        reg_nxt.result <= alu_nxt.result;
+        reg_nxt.reg_addr <= alu_nxt.result_addr;
 
 end process asyn;
 
+result <= reg.result;
+result_addr <= reg.res_addr;
+alu_jmp <= reg.alu_jump;
+brbr <= reg.brpr;
+wr_en <= reg.wr_en;
+dmem <= alu_nxt.mem_op;
+dmem_write_en <= alu_nxt.mem_en;
+hword <= alu_nxt.hw_op;
+byte_s <= alu_nxt.byte_op;
+
 end behav;
 

diff --git a/cpu/src/gpm.vhd b/cpu/src/gpm.vhd
index 7bba4007c08164e749058416262f9c40e6c83d16..428bdbb3454c7867428e0e2cf105bdb03f3ddba9 100644 (file)
--- a/cpu/src/gpm.vhd
+++ b/cpu/src/gpm.vhd
@@ -12,7 +12,7 @@ entity gpm is
                        -- active reset value
                        RESET_VALUE : std_logic;
                        -- active logic value
-                       LOGIC_ACT : std_logic
+                       --LOGIC_ACT : std_logic
                        
                        );
        port(
@@ -20,7 +20,7 @@ entity gpm is
                 clk : in std_logic;
                reset : in std_logic;
 
-                exti : in extmod_rec;
+                --exti : in extmod_rec;
                 --alu outpus
                 alu_nxt : in alu_result_rec;
                 --input
@@ -28,12 +28,12 @@ entity gpm is
                 --output
                 psw     : out status_rec;
                 --to memcnt
-                addr : out gp_register_t;
-                mem_en : out std_logic;
-                ldst : out std_logic;
+                --addr : out gp_register_t;
+                --mem_en : out std_logic;
+                --ldst : out std_logic;
                 --, hw,byte: std_logic;
                 --to output bus
-                exto : out data_ram_word_t
+                --exto : out data_ram_word_t
                         
         );
                

diff --git a/cpu/src/gpm_b.vhd b/cpu/src/gpm_b.vhd
new file mode 100644 (file)
index 0000000..0818304
--- /dev/null
+++ b/cpu/src/gpm_b.vhd
@@ -0,0 +1,63 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.common_pkg.all;
+use work.alu_pkg.all;
+
+entity gpm is
+
+       generic (
+                       -- active reset value
+                       RESET_VALUE : std_logic;
+                       -- active logic value
+                       --LOGIC_ACT : std_logic
+                       
+                       );
+       port(
+               --System inputs
+                clk : in std_logic;
+               reset : in std_logic;
+
+                --exti : in extmod_rec;
+                --alu outpus
+                alu_nxt : in alu_result_rec;
+                --input
+                
+                --output
+                psw     : out status_rec;
+                --to memcnt
+                --addr : out gp_register_t;
+                --mem_en : out std_logic;
+                --ldst : out std_logic;
+                --, hw,byte: std_logic;
+                --to output bus
+                --exto : out data_ram_word_t
+                        
+        );
+               
+end gpm;
+
+architecture behaviour of gpm is
+type gpm_internal is record
+        status : status_rec;
+end record gpm_internal;
+
+reg, reg_nxt : gpm_internal;
+
+begin
+syn : process (clk, reset)
+        if reset = RESET_VALUE then
+                reg <= (('0','0','0','0'));
+        elsif rising_edge(clk) then
+                reg <= reg_nxt;
+        end if;
+end process syn;
+
+asyn : process (clk, reset)
+        reg_nxt <= alu_nxt.status;
+end process asyn;
+
+psw <= reg;
+        
+end architecture behaviour;